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Engr354 - Chapter 7, Brown 1
Engr354: Digital Logic Circuits
Chapter 7Sequential Logic Elements
Dr. Curtis Nelson
Sequential Logic Elements
In this chapter you will learn about:• Logic circuits that can store information;• Basic cells, latches, and flip-flops;• State diagrams;• Design techniques for circuits that use flip-flops.
Engr354 - Chapter 7, Brown 2
Circuit Types
• Combinational – output depends only on the input.• Sequential – output depends on input and past behavior:
– Requires use of storage elements;– Contents of the storage elements is called state;– Circuit goes through a sequence of states as a result of changes in
inputs.• Synchronous – controlled by a clock.
Clock Signals
Engr354 - Chapter 7, Brown 3
A B
A Bistable Memory Element
• Bistable – possessing two stable states.
A Set/Reset (SR) Memory Element
• Called a Basic Cell;• NOR centered Basic Cell:
– Circuit (a), Function table (b).
• Inputs are active when they are high;• Blocking side inputs.
Engr354 - Chapter 7, Brown 4
Typical Operation of a Basic Cell
• Reset, clear.• Set, preset.
0
sr +
1
r
¯Q
rsr
1
State Diagram
NOR-Centered (Reset Dominant) Basic Cell
S R Action Qn+1
0 00 11 01 1
reset 0set 1reset 0
hold Qn
Operation Table
Reset
Set Q
Circuit
Qn®Qn+1
Inputs
0 ® 0
110
0 f
0 ® 11 ® 01 ® 1
RS
0f
f
1
Excitation Table
f
Engr354 - Chapter 7, Brown 5
NAND-Centered (Set Dominant) Basic Cell• Inputs are active low (when they are asserted);• Operation table indicates assertion, not voltage, levels.
Qn®Qn+1
Inputs
0 ® 010 11
0 f
0 ® 11 ® 01 ® 1
RS
f
ff0
Excitation Table
0
s
1
rs +
¯Q
sr s
1
State Diagram
Set
Reset Q
Circuit
S R Action QN+1
0 00 11 01 1
reset 0set 1set 1
hold
Operation Table
QN
Combined Form of the Basic Cell
Qn®Qn+1
Inputs
0 ® 010 11
0 f
0 ® 11 ® 01 ® 1
RS
f
ff0
Excitation TableNAND-centered
Qn®Qn+1
Inputs
0 ® 0
110
0 f
0 ® 11 ® 01 ® 1
RS
0f
f
1
Excitation TableNOR-centered
f
Qn®Qn+1
Inputs
0 ® 010 1
0 f
0 ® 11 ® 01 ® 1
RS
0
f 0
Excitation TableCombined Form
Basic Cell
Engr354 - Chapter 7, Brown 6
Designing Latches - A Model
Qn®Qn+1
Inputs
0 ® 0
1
0 1
0 f
0 ® 1
1 ® 0
1 ® 1
RS
0
f 0
Excitation TableCombined Form
Next State Logic
Basic Cell
Set
Reset R
S Q(H)
Q(L)ClockInputs
• Latch - a logic circuit that transfers the input state to the output state when the clock signal is high and latches and holds the input when the clock signal goes low.
Design of a Clocked D (Data) Latch
Next State Logic
Basic Cell
Set
Reset R
S Q(H)
Q(L)ClockD
Engr354 - Chapter 7, Brown 7
Clk D Qn Qn+1 Set Reset0 0 0 0 0 f0 0 1 1 f 00 1 0 0 0 f0 1 1 1 f 01 0 0 0 0 f1 0 1 0 0 11 1 0 1 1 01 1 1 1 f 0
Qn®Qn+1
Inputs
0 ® 010 1
0 f
0 ® 11 ® 01 ® 1
RS
0
f 0
Excitation TableBasic Cell
Design of a Clocked D Latch
Next State Logic
Set
Reset
Q(H)
ClkD
Block Diagram
Truth Table
DclkResetDclkSet×=
×=
Equations
0
CLKD +
1
CLKD+
¯Q
CLKD × CLKD ×
1
State Diagram
Clk D Action QN+1
0 x1 01 1
reset 0set 1
hold QN
Operation Table
Clocked D Latch
Engr354 - Chapter 7, Brown 8
Clk T Qn Qn+1 Set Reset0 0 0 0 0 f0 0 1 1 f 00 1 0 0 0 f0 1 1 1 f 01 0 0 0 0 f1 0 1 1 f 01 1 0 1 1 01 1 1 0 0 1
Qn®Qn+1
Inputs
0 ® 010 1
0 f
0 ® 11 ® 01 ® 1
RS
0
f 0
Excitation TableBasic Cell
Design of a Clocked Toggle (T) Latch
Next State Logic
Set
Reset
Q(H)
ClkT
Block Diagram
Truth Table
QTclkResetQTclkSet××=
××=
EquationsFunction Table
0
CLKT +
1
CLKT +
¯Q
CLKT × CLKT ×
1
State Diagram
Clk T Action QN+1
0 x Hold QN
1 0 Hold QN
1 1 ToggleNQ
Qn®Qn+1
Inputs
0 ® 010 1
0 f
0 ® 11 ® 01 ® 1
RS
0
f 0
Excitation TableBasic Cell
Design of a Clocked JK Latch
Next State Logic
Set
Reset
Q(H)
Clk
J
Block Diagram
Truth Table
QKclkResetQJclkSet××=
××=
EquationsFunction Table
K
Clk J K Action QN+1
0 x x Hold QN
1 0 0 Hold QN
1 0 1 Reset 01 1 0 Set 11 1 1 Toggle
NQ
Clk J K Qn Qn+1 Set Reset0 0 0 0 0 0 f0 0 0 1 1 f 00 0 1 0 0 0 f0 0 1 1 1 f 00 1 0 0 0 0 f0 1 0 1 1 f 00 1 1 0 0 0 f0 1 1 1 1 f 01 0 0 0 0 0 f1 0 0 1 1 f 01 0 1 0 0 0 f1 0 1 1 0 0 11 1 0 0 1 1 01 1 0 1 1 f 01 1 1 0 1 1 01 1 1 1 0 0 1
Engr354 - Chapter 7, Brown 9
Design of a Set-Dominant Clocked SR Latch
Next State Logic
Basic Cell
Set
Reset R
S Q(H)
Q(L)Clock
SR
• Inputs – S, R, Clock, Q• Outputs – Set, Reset
Clk S R Qn Qn+1 Set Reset0 0 0 0 0 0 f0 0 0 1 1 f 00 0 1 0 0 0 f0 0 1 1 1 f 00 1 0 0 0 0 f0 1 0 1 1 f 00 1 1 0 0 0 f0 1 1 1 1 f 01 0 0 0 0 0 f1 0 0 1 1 f 01 0 1 0 0 0 f1 0 1 1 0 0 11 1 0 0 1 1 01 1 0 1 1 f 01 1 1 0 1 1 01 1 1 1 1 f 0
Qn®Qn+1
Inputs
0 ® 010 1
0 f
0 ® 11 ® 01 ® 1
RS
0
f 0
Excitation TableBasic Cell
Next State Logic
Set
Reset
Q(H)
Clk
SR
Block Diagram
Truth Table
SRclkResetSclkSet
××=
×=
Equations
S R Action QN+1
0 00 11 01 1
reset 0set 1set 1
hold QN
Operation Table
Design of a Set-Dominant Clocked SR Latch
Engr354 - Chapter 7, Brown 10
SR Latch with Enable (Clock)
Design of a Clocked JK Latch – Version II
Next State Logic
D-LatchD D
Q(H)
Q(L)Clk
JK
• Inputs – J, K, Clk, Q• Output – D
• Replace the basic cell with a D-latch as the memory element.
Engr354 - Chapter 7, Brown 11
Qn®Qn+1
0 ® 010
00 ® 11 ® 01 ® 1
D
1
Excitation Table
Design of a Clocked JK Latch – Version II
Truth Table
QJclkclkQQKD ××+×+×=
EquationFunction Table
Clk J K Action QN+1
0 x x Hold QN
1 0 0 Hold QN
1 0 1 Reset 01 1 0 Set 11 1 1 Toggle
NQ
Next State Logic
Q(H)
Clk
J
Block Diagram
K D
Clk J K Qn Qn+1 D0 0 0 0 0 00 0 0 1 1 10 0 1 0 0 00 0 1 1 1 10 1 0 0 0 00 1 0 1 1 10 1 1 0 0 00 1 1 1 1 11 0 0 0 0 01 0 0 1 1 11 0 1 0 0 01 0 1 1 0 01 1 0 0 1 11 1 0 1 1 11 1 1 0 1 11 1 1 1 0 0
Terminology
• Latches are often called Transparent because the output will follow the input as long as the clock signal is high.
• Flip-flops are edge-triggered:– Positive-edge triggered (PET) is when action occurs on the rising
edge of the clock signal;– Negative-edge triggered (NET) is when action occurs on the
falling edge of the clock signal.• Types of Flip-flops:
– SR (rarely used);– D (very, very common, 74HC74);– JK (hardly ever used, 74HC109);– Toggle (occasionally used by CAD programs).
Engr354 - Chapter 7, Brown 12
t su
t h
Clk
D
Q
Setup and Hold Times
• Setup time (tSU) is the time interval preceding the active transition point of the CLK during which all data inputs must remain stable.
• Hold time (tH) is the time interval following the active transition point of the CLK during which all data inputs must remain stable.
• See data sheet for 74HC74
PET Master-Slave D Flip-Flop
• QM follows the D input whenever CLK is low.• When CLK goes high, QM is transferred to the output.
Engr354 - Chapter 7, Brown 13
Positive-Edge-Triggered D Flip-Flop
PET D Flip-Flop with Clear and Preset
• Synchronous – transitions or actions occur in relation to the CLK signal;• Asynchronous – transitions or actions are not related to the CLK signal.
Engr354 - Chapter 7, Brown 14
D Q
Q
D Q
Q
D Q
Q
D
Clock Q a
Q b
Q c
Q c
Q b
Q a
(a) Circuit
Clk
D
Clock
Q a
Q b
(b) Timing diagram
Q c
Level-Sensitive vs. Edge-Triggered
• Level-sensitive = latch• Edge-triggered = flip-flop
Design a T Flip-Flop from a D Flip-Flop
Qn®Qn+1
0 ® 010
00 ® 11 ® 01 ® 1
D
1
Excitation Table
T
0
1
Q n 1 +( )
Q n( )
Q n( )
Function Table
Next State Logic
D flip-flopD
Q(H)
Q(L)
Clk
T
• The memory element is now edge-triggered meaning the Clk signal is no longer part of the next-state logic.
Truth Table
T Qn Qn+1 D0 0 0 00 1 1 11 0 1 11 1 0 0
Engr354 - Chapter 7, Brown 15
D Q
Q
Q
Q T
Clock
(a) Circuit
T Q
Q
(c) Graphical symbol
Design a T Flip-Flop from a D Flip-Flop
J Q
Q
Graphical symbol
K
D Q
Q
Q
Q
J
Clock
Circuit
K
Design a JK Flip-Flop from a D Flip-Flop
K01
Q n 1+( )
Q n( )0
J00
0 111 Q n( )1
Function Table
Engr354 - Chapter 7, Brown 16
• Basic cell – cross-coupled NAND/NOR.• Gated latch – output changes only when Clk is asserted:
– Gated SR latch;– Gated D latch;– Gated JK latch.
• Flip-flop – output changes only on Clk edge:– Master-slave;– Edge-triggered;– Three main types:
• D (very, very common, 74HC74);• JK (hardly ever used, 74HC109);• Toggle (occasionally used by CAD programs).
Summary of Terminology
Sequential Logic Elements Summary
In this chapter you learned about:• Logic circuits that can store information;• Basic cells, latches, and flip-flops;• State diagrams;• Design techniques for circuits that use flip-flops.
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