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02131 Embedded Systems 1
jan@imm.dtu.dk
Jan Madsen
Informatics and Mathematical ModelingTechnical University of Denmark
Richard Petersens Plads, Building 321DK2800 Lyngby, Denmark
Mic-1microprocessor design
02131 Embedded Systems 2
The Mic-1 architecture
02131 Embedded Systems 2
02131 Embedded Systems 3
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 4
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 3
02131 Embedded Systems 5
Basic architecture
Processor
Controller Datapath
Memory
Next-state and control logic
ALU
RegisterPC IR
02131 Embedded Systems 6
Programmer’s view
?programmer does not need to know detailed information about the processor’s architecture?but, needs an architectural abstraction?two levels of programming:?Assembly-language programming, processor specific
instructions?Structured-language programming, processor
independent instructions
02131 Embedded Systems 4
02131 Embedded Systems 7
Instruction set
?Atomic processor operations that the programmer may invoke?Describes the bit-configurations allowed in the IR
(Instruction Register)?each configuration forms an assembly instruction?a sequence of such configurations forms an assembly
program
02131 Embedded Systems 8
Instruction
Opcode field Operand field
Types of instructions:
Data-transferArithmetic/logicalBranch
02131 Embedded Systems 5
02131 Embedded Systems 9
Data-transfer instructions
?Move data between registers?Move data between memory and registers?Move data between input/output channels and
registers
MOV: A = 47
2 byte ( 16 bit )
74 (Hex) 2F (Hex)
0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1
02131 Embedded Systems 10
Arithmetic/logical instructions
?Configure the ALU to carry out a particular function?Channel data from registers through the ALU?Channel data from the ALU back to a particular register
ADD: A = A + Rn
0 0 1 0 1 r r r 1 byte ( 8 bit )
ADD: A = A + R2 00101010 2A (Hex)
02131 Embedded Systems 6
02131 Embedded Systems 11
Branch instructions
?Determines the address of the next instruction? Types of branches:
Unconditional jumps
Conditional jumps
Procedure call and return
Long jump: LJMP addr1602 XX XX
Jump if accumulator zero: JZ addr860 XX (relative address)
Absolute subroutine call: ACALL addr11a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
02131 Embedded Systems 12
Operand field Register file Memory
Addressing modes
immediate
Register direct
Register indirect
Direct
indirect
Data
Register addr
Register addr
Memory addr
Memory addr
Data
Memory addr Data
Data
Memory addr
Data
02131 Embedded Systems 7
02131 Embedded Systems 13
Rn
A simple instruction set
MOV Rn, direct
MOV @Rn, Rm
ADD Rn, Rm
0000 Rn direct
0010 Rn
0100 Rn RmRn
Rn = M(direct)
M(Rn) = Rm
Rn = Rn + Rm
SUB Rn, Rm 0101 Rn Rn = Rn - Rm
MOV Rn, #immed. 0011 Rn immediate Rn = immediate
Assembly instruct. First byte Second byte Operation
JZ Rn, immediate 1000 Rn immediate PC = PC+ immed.(only if Rn is 0)
Rm
MOV direct, Rn 0001 Rn direct M(direct) = Rn
Rn Rm
02131 Embedded Systems 14
Example
int total = 0;for (int i=10; i!=0; i--)
total += i;// next instructions...
MOV 100, R0;// Put total at M[100]
MOV R0, #0; // total = 0
MOV R1, #10; // i = 10
JZ R1, Next; // Done if i=0
ADD R0, R1;// total += i
MOV R2, #1; // constant 1
JZ R3, Loop; // Jump always
Loop:
Next:
// next instructions...
SUB R1, R2;// i--
MOV R3, #0; // constant 0
02131 Embedded Systems 8
02131 Embedded Systems 15
Do we really need assembly programming?
?Ideally, the structured-language programmer does not need to know the instruction set?However, nearly every embedded system
requires the programmer to write at least some portion of the program in assembly language?Low/level input/output operations with devices
outside the processor, i.e. device drivers
02131 Embedded Systems 16
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 9
02131 Embedded Systems 17
Structure of Mic1
data & codememory
datapath controller
micromemory
02131 Embedded Systems 18
Structure of Mic1
data & codememory
datapath controller
micromemory
mic1_dp mic1_ctr
mic1_rom
ijvm_ram ram_dp
02131 Embedded Systems 10
02131 Embedded Systems 19
Dataflow
Clock signal
longest time required for data to travel from one register to another
Clock cycle:
Clock frequency: clock cycle1
Hz
02131 Embedded Systems 20
Mic-1 datapath
? The control signals are set up? The registers are loaded onto
the B bus? The ALU and shifter operate? The results propagate along the
C bus back to the registers
02131 Embedded Systems 11
02131 Embedded Systems 21
Mic-1 datapath + controller
? Controller must produce? The state of every control
signal in the system? The address of the next
microinstruction
? The control store implementsthe microprogram for eachsingle IJVM instruction
02131 Embedded Systems 22
Datapath cycle
02131 Embedded Systems 12
02131 Embedded Systems 23
Mic-1 datapath + controllerdp mic1_ctr(
out ctr_rd: ns(1);out ctr_wr: ns(1);out ctr_fetch: ns(1);
in mbr_out: ns(8);
in status_N, status_Z: ns(1);out B_sel: ns(4);out alu_fct: ns(8);out C_select: ns(9);out rom_adr: ns(9); // equivalent to mpcout rom_rd: ns(1);in rom_in: ns(36)
){sig jamz, jamn, jmpc: ns(1);
sig mpc: ns(9);
reg mir: ns(36);
// Local signals and registers
sfg c_0 { // action listctr_rd = mir[5]; ctr_wr = mir[6]; ctr_fetch = mir[4];jamz = mir[24]; jamn = mir[25]; jmpc = mir[26];mpc = (jmpc ? mbr_out | mir[27:35] : mir[27:35])
| ((jamz | jamn)<<8);B_sel = mir[0:3]; alu_fct = mir[16:23];C_select = mir[7:15];rom_adr = mpc; rom_rd = 1; mir = rom_in;
}}sequencer mic1_ctr_seq(mic1_ctr){ c_0; }
02131 Embedded Systems 24
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 13
02131 Embedded Systems 25
The microprogram for the Mic-1Label Operations Comments --------------------------------------------------------------------------------------------------------------------------------------------------------Main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch --------------------------------------------------------------------------------------------------------------------------------------------------------nop1 goto Main1 Do nothing --------------------------------------------------------------------------------------------------------------------------------------------------------iadd1 MAR = SP = SP - 1; rd Read in next-to-top word on stackiadd2 H = TOS H = top of stackiadd3 MDR = TOS = MDR + H; wr; goto Main1 Add top two words; write to top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------isub1 MAR = SP = SP - 1; rd Read in next-to-top word on stackisub2 H = TOS H = top of stackisub3 MDR = TOS = MDR - H; wr; goto Main1 Do subtraction; write to top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------iand1 MAR = SP = SP - 1; rd Read in next-to-top word on stackiand2 H = TOS H = top of stackiand3 MDR= TOS = MDR AND H; wr; goto Main1 Do AND; write to new top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------ior1 MAR = SP = SP - 1; rd Read in next-to-top word on stackior2 H = TOS H = top of stackior3 MDR = TOS = MDR OR H; wr; goto Main1 Do OR; write to new top of stack --------------------------------------------------------------------------------------------------------------------------------------------------------dup1 MAR = SP = SP + 1 Increment SP and copy to MARdup2 MDR = TOS; wr; goto Main1 Write new stack word --------------------------------------------------------------------------------------------------------------------------------------------------------pop1 MAR = SP = SP - 1; rd Read in next-to-top word on stackpop2 Wait for new TOS to be read from memorypop3 TOS = MDR; goto Main1 Copy new word to TOS
02131 Embedded Systems 26
Microinstructions
? IJVM instruction: iadd? Add the top two words from
stack
?Microinstructions?MAR = SP = SP - 1; rd?H = TOS?MDR = TOS = MDR + H;
wr; goto Main1
02131 Embedded Systems 14
02131 Embedded Systems 27
Microinstructions
? MAR = SP = SP - 1; rd? H = TOS? MDR = TOS = MDR + H; wr;
goto Main1
2c3
0
fffffed1
4000
6000
8002
59
10
fffffed1
8002
2c3
0
2c3
4000
6000
8002
59
10
194
8002
0
0
2c3
4000
6000
8002
59
10
2c3
8002
0H
0OPC
2c3TOS
4000CPP
6000LV
8003SP
64MBR
10PC
2c3MDR
8002MAR
B
Forwarding!
02131 Embedded Systems 28
Microinstructions
? MAR = SP = SP - 1; rd? H = TOS? MDR = TOS = MDR + H; wr;
goto Main1
2c3
0
fffffed1
4000
6000
8002
59
10
fffffed1
8002
2c3
0
2c3
4000
6000
8002
59
10
194
8002
0
0
2c3
4000
6000
8002
59
10
2c3
8002
0H
0OPC
2c3TOS
4000CPP
6000LV
8003SP
64MBR
10PC
2c3MDR
8002MAR
02131 Embedded Systems 15
02131 Embedded Systems 29
Microinstructions
? MAR = SP = SP - 1; rd? H = TOS? MDR = TOS = MDR + H; wr;
goto Main1
2c3
0
fffffed1
4000
6000
8002
59
10
fffffed1
8002
2c3
0
2c3
4000
6000
8002
59
10
194
8002
0
0
2c3
4000
6000
8002
59
10
2c3
8002
0H
0OPC
2c3TOS
4000CPP
6000LV
8003SP
64MBR
10PC
2c3MDR
8002MAR
B-A
02131 Embedded Systems 30
Microinstructions
? MAR = SP = SP - 1; rd? H = TOS? MDR = TOS = MDR + H; wr;
goto Main1
2c3
0
fffffed1
4000
6000
8002
59
10
fffffed1
8002
2c3
0
2c3
4000
6000
8002
59
10
194
8002
0
0
2c3
4000
6000
8002
59
10
2c3
8002
0H
0OPC
2c3TOS
4000CPP
6000LV
8003SP
64MBR
10PC
2c3MDR
8002MAR
800380028001
1942c3 SP
SP, MARMAR, MDR=fffffed1fffffed1
02131 Embedded Systems 16
02131 Embedded Systems 31
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 32
Mic-1 datapath
? ALU? 6 bit ALU? 2 bit Shift
?Registers? 4 Memory interface registers? 3 Initialized registers? 3 regular registers
? B bus?Only one register can be
written to the bus
?C bus? Bus can be written to any
number of registers
02131 Embedded Systems 17
02131 Embedded Systems 33
Register
dp fdl_register(in x: tc(32); out z: tc(32);in ld: ns(1)
){reg rx: tc(32);
sfg c_0 { rx = ld ? x : rx; z = rx; }}hardwired register_ctr(fdl_register){ c_0; }
x
ld
z
clk
Remember that register is
a reserved word in VHDL
02131 Embedded Systems 34
Initialized register?
dp register(in x: tc(32); out z: tc(32);in ld: ns(1)
){reg rx: tc(32);
sfg c_0 { rx = ld ? x : rx; z = rx; }}hardwired register_ctr(register){ c_0; }
x
ld
z
clk
02131 Embedded Systems 18
02131 Embedded Systems 36
Bus
ld_TOS
clk
ld_OPC
clk
OPC
TOS
C bus B bus
02131 Embedded Systems 37
Bus
ld_TOS
clk
ld_OPC
clk
OPC
TOS
C bus B bus
mux
1
0
B_sel
02131 Embedded Systems 19
02131 Embedded Systems 38
Cloning components
dp fdl_register(in x: tc(32); out z: tc(32);in ld: ns(1)
){reg rx: tc(32);
sfg c_0 { rx = ld ? x : rx; z = rx;
}}hardwired register_ctr(fdl_register){ c_0; }
dp TOS : fdl_registerdp OPC : fdl_registerdp H : fdl_register
02131 Embedded Systems 39
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 20
02131 Embedded Systems 40
Mic-1 controller
B_sel
N
Z
C_sel
ALU_sel
mic1_dp mic1_ctr
gcd
02131 Embedded Systems 41
Structure of Mic1
02131 Embedded Systems 21
02131 Embedded Systems 42
MicroInstruction Register (MIR)
02131 Embedded Systems 43
GCD on the Mic-1 datapath?
? Initialize? LV = y?CPP = x
?H = x? (LV – H) == 0?? (LV – H ) < 0??No? LV = LV – H
? Yes?H = LV – H?H = -H
02131 Embedded Systems 22
02131 Embedded Systems 44
Mic-1 controller
B_sel
N
Z
C_sel
ALU_sel
mic1_ctrmic1_dp
gcd
02131 Embedded Systems 45
Mic-1 controllerdp mic1_ctr(
out log: ns(1); // request log information
in status_N, // ALU result negativestatus_Z : ns(1); // ALU result zero
out B_sel : ns(4); // register to feed B-busout alu_fct : ns(8); // request for ALU functionout C_sel : ns(9) // registers to load from C-bus
){
reg s_z, s_n : ns(1);
// C_sel bit-sequence// H, OPC, TOS, CPP, LV, SP, PC, MDR, MARsig Csel : ns(9);
// B_sel register sequence// MDR, PC, MBR, MBRU, SP, LV, CPP, TOS, OPC, none ...// 0, 1, 2, 3, 4, 5, 6, 7, 8, 9-15sig Bsel : ns(4);
// ALU_sel bit-sequence// SLL, SRA, F0, F1, ENA, ENB, INVA, INCsig ALUsel : ns(8);
B_sel
N
Z
C_sel
ALU_sel
mic1_ctr
gcd
02131 Embedded Systems 23
02131 Embedded Systems 46
Mic-1 controller// utility actionssfg rep { log = 1; s_z = status_Z; s_n = status_N;
B_sel = Bsel; C_sel = Csel; alu_fct = ALUsel; }
sfg finish {$display($cycle, " THE END!!!");}
// No output to bus B, no input from bus C and ALU outputs a zerosfg idle {ALUsel = 0b00010000; Bsel = 9; Csel = 0b000000000;}
// The following are the actions necessary to compute GCD// read x, y - initially y is in LV and x in CPP// during iterations, y will stay in LV and x will be in H// LV is used as an auxillary register
// a1: move x (CPP) to Hsfg a1 { ALUsel = 0b00010100; Bsel = 6; Csel = 0b100000000; $display($cycle," ",$sfg);}
02131 Embedded Systems 47
Mic-1 controller// The following are the actions necessary to compute GCD// read x, y - initially y is in LV and x in CPP// during iterations, y will stay in LV and x will be in H// LV is used as an auxillary register
// a1: move x (CPP) to Hsfg a1 { ALUsel = 0b00010100; Bsel = 6; Csel = 0b100000000; $display($cycle," ",$sfg);}
// a2: (LV - H) == 0?sfg a2 { ALUsel = 0b00111111; Bsel = 5; Csel = 0b000000000; $display($cycle," ",$sfg);}
// a3: (LV - H) < 0?sfg a3 { ALUsel = 0b00111111; Bsel = 5; Csel = 0b000000000; $display($cycle," ",$sfg);}
// a4: LV = LV - Hsfg a4 { ALUsel = 0b00111111; Bsel = 5; Csel = 0b000010000; $display($cycle," ",$sfg);}
// a5: H = LV - Hsfg a5 { ALUsel = 0b00111111; Bsel = 5; Csel = 0b100000000; $display($cycle," ",$sfg);}
// a6: H = -Hsfg a6 { ALUsel = 0b00111011; Bsel = 9; Csel = 0b100000000; $display($cycle," ",$sfg);}
// a7: out = Hsfg a7 { ALUsel = 0b00011000; Bsel = 9; Csel = 0b100000000; $display($cycle," ",$sfg);}
}
02131 Embedded Systems 24
02131 Embedded Systems 48
Mic-1 controllerfsm ctr(mic1_ctr) {initial s0;state s1, s2, s3, s4, s5, s6;// The GCD program,// @s0 (rep,idle) -> s1; // we need an idle transition in order
// to get the registers initialized@s1 (rep,a1) -> s2;@s2 (rep,a2) -> s3;@s3 if (s_z) then (rep,idle) -> s6;
else (rep,a3) -> s4;@s4 if (s_n) then (rep,a5) -> s5;
else (rep,a4) -> s2;@s5 (rep,a6) -> s2;@s6 (rep,a7,finish) -> s6;
}
B_sel
N
Z
C_sel
ALU_sel
mic1_ctr
gcd
02131 Embedded Systems 49
Structure of Mic1
mic1_dp mic1_ctr
mic1_rom
ijvm_ram ram_dp
02131 Embedded Systems 25
02131 Embedded Systems 50
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 51
Memory interface
? 32-bit, word-addressablememory port? Address: MAR register?Data (R/W): MDR register
? 8-bit, byte-addressablememory port? Address: PC register?Data (R): MBR register
02131 Embedded Systems 26
02131 Embedded Systems 52
Memory structure
?Sequence of cells with consecutive addresses?Cell size, most commonly 8 bits = 1 byte ?Bytes are grouped into words?~ the size of which most instructions operate?Most commonly today, 32 bits or 4 bytes
0
1
2
02131 Embedded Systems 53
Memory structure
?How do we read the bytes of a word??Big endian?Little endian?Mic-1 uses little endian
0 1 2 3
3 2 1 0Big end
Little end
02131 Embedded Systems 27
02131 Embedded Systems 54
Memory structure
?MDR = M[MAR]?M[2] -> ABCD
?MBR = M[PC]?M[2] -> ---C
3 2 1 00
1
27 6 5 4
11 10 9 8A B C D
S T U V
D C B A
02131 Embedded Systems 55
MBR register
?MBR holds 8 bits read from memory?When written on to the B bus (32 bits) there are
two options:?Unsigned?B[7:0] = MBR, B[23:8] = 0b000000000000000000000000
?Signed (sign extension)?B[7:0] = MBR, B[i] = MBR[7] for i = [23:8]
02131 Embedded Systems 28
02131 Embedded Systems 56
IJVM memory model
? Constant Pool? Cannot be written by an IJVM program? Contains constants, strings and pointers? CPP register contains the address of the first word
? Local Variable Frame? Each invocation of a method results in an allocation
for storing variables during the lifetime of theinvocation
? LV register contains the address of the first location? Operand Stack? Allocated directly above the local variable frame? SP register
? Method Area? Contains the program ”text”? Treated as a byte array
Methodarea
Constantpool
Localvariableframe
Stack
SP
LV
CPP
PC
02131 Embedded Systems 57
IJVM memory model
?Initial register values in our Mic-1?SP = 0x150?LV = 0x150?CPP = 0x100?PC = -1
Methodarea
Constantpool
Localvariableframe
Stack
SP
LV
CPP
PC
02131 Embedded Systems 29
02131 Embedded Systems 58
Gezel library blocks
?Predesigned library blocks, called ipblock’s?Looks like Gezel datapath modules?but, the behavior is written in C++ and compiled
directly into the Gezel kernel.?An ipblock defines:?IO interface, like for the dp?type?An optional number of parameters
02131 Embedded Systems 59
Gezel RAM library block
ipblock MyRAM(in address : ns(7);in wr,rd : ns(1);in idata : tc(8);out odata : tc(8)
){iptype "ram";ipparm "size=128";ipparm "wl=8";
}
Names as well as the orderof the ports of a libraryblock is determined by thetype
02131 Embedded Systems 30
02131 Embedded Systems 60
Gezel RAM library blockdp test(
out address : ns(7);out wr,rd : ns(1); out idata : ns(8);in odata : ns(8)
) {// writes 4 values to RAM // and read them out againreg count : tc(8);
sfg init{count = 0;address = 0;rd = 1;wr = 0;idata = 0;$display("test: init");
}sfg read{count = count-1;address = count;rd = 1;wr = 0;idata = 0;$display("test: read ",odata,
" @",address);}
sfg write{count = count+1;address = count;rd = 0;wr = 1;idata = count+10;$display("test: write ",idata,
" @",address);}sfg finish{count = 0;address = count;rd = 1;wr = 0;idata = 0;$display("test: finished @”,address);
}sfg idle{count = count-1;address = count;rd = 1;wr = 0;idata = 0;$display("test: idle");
}}
02131 Embedded Systems 61
Gezel RAM library block
fsm test_ctr(test){initial s0;state s1, s2, s3;@s0 (init) -> s1;@s1 if (count<4) then (write) -> s1;
else (idle) -> s2;@s2 if (count>-1) then (read) -> s2;
else (finish)-> s3;@s3 (idle) -> s3;
}
system ram_test{MyRAM(a,w,r,id,od);test(a,w,r,id,od);
}
02131 Embedded Systems 31
02131 Embedded Systems 63
Agenda
?ISA?How does instructions get executed?
?Mic-1 ?Basic architecture?Microinstructions?Datapath?Controller?Memory interface
?Gezel issues
02131 Embedded Systems 64
Debugging Gezel designs
?Using simulation directives? $display(”The value of a is ”, a);? $display(”The value of a is ”, $bin, a);? $display($cycle, ”The value of a is ”, $bin, a);
?Has to be used inside sfg’s?$display, like printf in C, is very effective
but may be difficult to manage!
02131 Embedded Systems 32
02131 Embedded Systems 65
Debugging gezel designs
demux
mux
regA regB
ALU
Logger
log
$display ?
$display
02131 Embedded Systems 66
Debugging Gezel designsdp logger( in in_a : ns(32);in in_b : tc(32);in in_c, in_d : tc(12);in log : ns(1) // Debug information, activated only when log is on
){reg activate : ns(1);
sfg nop { activate = log; } // tells to report on next cyclesfg rep {
$display($cycle," Components");$display($cycle," ",“A: ",in_a);$display($cycle," ",“B: ",in_b);$display($cycle," ",“C: ",in_c);$display($cycle," ",“D: ",in_d);$display($cycle," ");
}}
fsm logger_ctr(logger){initial s0;@s0 if (activate) then (nop,rep) -> s0;
else (nop) -> s0;}
02131 Embedded Systems 33
02131 Embedded Systems 67
The GCD example
int gcd(int a; int b) {x = a; y = b;while x!=y {if x<y theny = y – x;
elsex = x – y;
}return x;
}
bb0 x=a; y=b; x!=ybb1 x<ybb2 y=y-x; x!=ybb3 x=x–y; x!=ybb4 return x
bb2
bb3
0bb0
1bb4
3
bb12
02131 Embedded Systems 68
Gezel
dp gcd(in a: ns(32); in b: ns(32); out res: ns(32)){
reg x, y, res: ns(32);reg xlessy, xneqy: ns(1);
sfg bb0 { x=a; y=b; xneqy=(x!=y); }sfg bb1 { xlessy=(x<y);}sfg bb2 { y=y-x; xneqy=(x!=y);}sfg bb3 { x=x-y; xneqy=(x!=y);}sfg bb4 { res=x;}
}
fsm gcd_ctl(gcd) {
initial s0;state s1, s2, s3;
@s0 (bb0) -> s1;@s1 if (xneqy) then (bb1) -> s2;
else (bb4) -> s3;@s2 if (xlessy) then (bb2) -> s1;
else (bb3) -> s1;@s3 (bb4) -> s3;
}
bb0 x=a; y=b; x!=ybb1 x<ybb2 y=y-x; x!=ybb3 x=x–y; x!=ybb4 return x
bb2
bb3
0bb0
1bb4
3
bb12
registers are updated at the end ofa cycle, so the test will be on the
old values!
02131 Embedded Systems 34
02131 Embedded Systems 69
Gezel register update
?We can solve the problem of register update, by splitting the basic block into two states.?One state doing the calculation?One state doing the test based on results from
calculationdp …sfg bb0a { x=a; y=b; }sfg bb0b { x!=y;}
fsm …state s1, s2, s3, sx;
@s0 (bb0a) -> sx;@sx (bb0b) -> s1;
0bb0a
xbb0b
1
02131 Embedded Systems 70
Gezel register update
?We can also solve the problem using techniquesfrom formal verification!
dp …sfg bb0 { x=a; y=b; x!=y;}
fsm …state s1, …;
@s0 (bb0) -> s1;
0bb0
1
{ x=a; y=b; status=(x!=y);}{ P’(?,?,?) } { P(x,y,status) }{ P(x,y,x!=y) }
{ P(x,b,x!=b) }
{ P(a,b,a!=b) }
{ P(a,b,a!=b) }
dp …sfg bb0 { x=a; y=b; x!=y;}
fsm …state s1, …;
@s0 (bb0) -> s1;
dp …sfg bb0 { x=a; y=b; a!=b;}
fsm …state s1, …;
@s0 (bb0) -> s1;
No extra state !
02131 Embedded Systems 35
02131 Embedded Systems 71
No extra state?
dp …sfg bb0 { x=a; y=b; x!=y;}
fsm …state s1, …;
@s0 (bb0) -> s1;
dp …sfg bb0 { x=a; y=b; a!=b;}
fsm …state s1, …;
@s0 (bb0) -> s1;
a b
yx
!=
status
a b
yx
!=
status
No extra hardware!
02131 Embedded Systems 72
No extra hardware?
dp …sfg bb2 {y=y-x; xneqy=(x!=y);}
a b
yx
!=
xneqy
-
y
a b
yx
!=
xneqy
-
y
a b
yx
!=
xneqy
-
y
signal
02131 Embedded Systems 36
02131 Embedded Systems 73
Run/done protocol
bb0 bb2
bb3
bb1
bb4
0
1
3
2
run
in
done
out
run
in
done
out
02131 Embedded Systems 74
Weazel
02131 Embedded Systems 37
02131 Embedded Systems 75
Weazel: www.mortician.dk
Weazel Design Tool for the Gezel Design Language
Note: This software is still under development.
Make sure you save your work often. Please report bugs to: feedback@bitempire.com
Installation:Download and install the .NET 2.0 runtime Download and install the Weazel Design Tool
Files:Microsoft .NET 2.0 Runtime - dotnetfx.zip
Weazel Design Tool - setup.zip
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