MultiCore ATPG 2010 IC/CAD Contest 組員：林中正、曾國賢. Goal

MultiCore ATPG

2010 IC/CAD Contest

組員：林中正、曾國賢

Goal

The goal is to develop an ATPG program with fast run time, few generated patterns and high fault coverage under the given multi‐core computing environment. The designed ATPG program should have the ability to handle single stuck‐at faults in combinational logic circuits. An evaluation set consist of several benchmarks is provided for verifying your program. A benchmark is a combinational logic circuit in the form of a Verilog gate‐level netlist.

Introduction

ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology

Program structure

We use the 2‐bit adder as an example to illustrate briefly the operation of pattern generation.First, the gate level netlist is read to construct the structure of design .Second, find all single stuck‐at faults in this design and generate the fault list. Third, collapse the faults. The collapsed faults are used to calculate the fault coverage. Forth, pick up the fault one by one from the fault list to generate test pattern by running test algorithm.

Flow chart

Test Output

Test pattern numberTotal backtrack numberTotal fault numberDetected fault numberUndetected fault numberAbort fault numberRedundant fault numberTotal equivalent fault numberEquivalent detected fault numberEquivalent undetected fault numberEquivalent abort fault numberEquivalent redundant fault numberFault CovergeEquivalent FCFault Efficiency

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