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戦略的研究シーズ育成事業
「革新的パワーゲーティングによる
超低消費電力回路・システムの開発」
目次用
KAST 平成26年度研究概要 2015.7.29- 147 -
PS-MOSFET
QB
Q
SRSR
CTRL
CB
DC
CB
C
C
CB
CB
C
CBCCLK
Ordinary LAT NV-LAT
NV-DFF
SR
(a)
(b)
PF
MTJ1 MTJ2PF
SR SRINV2
INV1
Q QB DBD
WL
CTRL
PS-MOSFET
(c)
KAST 平成26年度研究概要 2015.7.29- 148 -
PS-MOSFET
QB
Q
SRSR
CTRL
CB
DC
CB
C
C
CB
CB
C
CBCCLK
Ordinary LAT NV-LAT
NV-DFF
SR
(a)
(b)
PF
MTJ1 MTJ2PF
SR SRINV2
INV1
Q QB DBD
WL
CTRL
PS-MOSFET
(c)
KAST 平成26年度研究概要 2015.7.29- 149 -
KAST 平成26年度研究概要 2015.7.29- 150 -
KAST 平成26年度研究概要 2015.7.29- 151 -
100 102 104 106 10810-7
10-6
10-5
10-4
10-3
10-2
10-1
BET
(s)
exe (ns)
Write bias control
Leakage control
Store-free shutdown
VDD=0.9V
VSR=0.65VVCTRL=0.55V
VCTRL=0.07V
w/o BET control
MTJ2
QBQ
WL
D
Virtual VDD
VCTRL
VSRVSR
DB
PS-FinFET
MTJ1 fp
fp
VDD
VPGPower switch
Read
Write
Sleep (tSL)
Store
Shutdown (tSD)
Restore
nRW
Read
Write
Sleep 1 (tSL)
Sleep 2 (tSD)
Restore + Read + Short shutdown
Restore +Write + Store +Short shutdown
Shutdown 1 (tSL)
Shutdown 2 (tSD)
nRW nRW
6T cell NVPG cell NOF cellncyc ncyc ncycOrdinary SRAM
(OSR)NVPG NOF
0 0.2 0.4 0.6 0.8 118
20
22
24
26
28
6T-SRAMI L
NV (n
A)
VCTRL (V)
NV-SRAM
ILV
VDD = 0.9V
0.4 0.5 0.6 0.7 0.8 0.910
20
30
40
50
P AP
IC
I MTJ
PA
P (
A)
VSR (V)
VDD=0.9V
1.5 IC
0.3 0.4 0.5 0.6 0.7 0.8 0.910
20
30
40
50
AP P
IC
I MTJ
AP
P (A
)
VCTRL (V)
VSR=0.65VVDD=0.9V
1.5 IC
D
SG
MTJFinFET
PFMTJ
Gate
Drain
Source
FinFET VD
VG VGS0 VBS0
0 0.3 0.6 0.90
10
20
30
40
50
Drain bias VD (V)
Dra
in c
urre
nt I D
P , ID
AP (
A)
VG=0 - 0.9V in steps of 0.1V
IDP
P AP
L=20nmNF =1VDD=0.9V
IDAP
-0.9 -0.6 -0.3 0 0.3 0.6 0.9-80
-60
-40
-20
0
20
40
Drain bias VD (V)
Dra
in c
urre
nt I D
P, I
DA
P (A
)
IDP
IDAP
P AP
AP P
VG=VDD
0 0.3 0.6 0.90
10
20
30
40
50
60
Mag
neto
curre
nt ra
tio
MC (%
)
Drain bias VD (V)
VG=0 - 0.9V in steps of 0.1V
CIMSCIMS
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
VQ
B (V
)
(1,1,1,1)
(1,2,1,1)
0.285V
0.276V0 0.3 0.6 0.9
0
0.3
0.6
0.9
VQ (V)
V QB
(V)
(1,1,1,1)
(1,2,1,1) 0.097V
0.142V
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
V QB (V
)
(1,1,1,1)
(1,2,1,1)
0.277V
0.224V
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
V QB
(V)
VSR=0.9V
P AP
MTJ1: PMTJ2: AP
0.65V
0.157V0.220V
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
V QB (V
)
(VSR, VCTRL)=
MTJ2: AP P
MTJ1: AP P
MTJ1: APMTJ2: AP
(0.65V, 0.5V)(0.65V, 0.5V)(0.9V, 0.9V)
0.109V0.204V
0 0.3 0.6 0.90
0.3
0.6
0.9 VDD=0.9V
VQ (V)
VQ
B (V
)
VQ=VQB
MTJ1: APMTJ2: P
Vsupply=0.20.30.40.5
0.60.70.80.9V
TrajectoryP AP
VSR=0.65V
Trajectory( 5)
KAST 平成26年度研究概要 2015.7.29- 152 -
100 102 104 106 10810-7
10-6
10-5
10-4
10-3
10-2
10-1
BET
(s)
exe (ns)
Write bias control
Leakage control
Store-free shutdown
VDD=0.9V
VSR=0.65VVCTRL=0.55V
VCTRL=0.07V
w/o BET control
MTJ2
QBQ
WL
D
Virtual VDD
VCTRL
VSRVSR
DB
PS-FinFET
MTJ1 fp
fp
VDD
VPGPower switch
Read
Write
Sleep (tSL)
Store
Shutdown (tSD)
Restore
nRW
Read
Write
Sleep 1 (tSL)
Sleep 2 (tSD)
Restore + Read + Short shutdown
Restore +Write + Store +Short shutdown
Shutdown 1 (tSL)
Shutdown 2 (tSD)
nRW nRW
6T cell NVPG cell NOF cellncyc ncyc ncycOrdinary SRAM
(OSR)NVPG NOF
0 0.2 0.4 0.6 0.8 118
20
22
24
26
28
6T-SRAM
I LN
V (n
A)
VCTRL (V)
NV-SRAM
ILV
VDD = 0.9V
0.4 0.5 0.6 0.7 0.8 0.910
20
30
40
50
P AP
IC
I MTJ
PA
P (
A)
VSR (V)
VDD=0.9V
1.5 IC
0.3 0.4 0.5 0.6 0.7 0.8 0.910
20
30
40
50
AP P
IC
I MTJ
AP
P (A
)
VCTRL (V)
VSR=0.65VVDD=0.9V
1.5 IC
D
SG
MTJFinFET
PFMTJ
Gate
Drain
Source
FinFET VD
VG VGS0 VBS0
0 0.3 0.6 0.90
10
20
30
40
50
Drain bias VD (V)
Dra
in c
urre
nt I D
P , ID
AP (
A)
VG=0 - 0.9V in steps of 0.1V
IDP
P AP
L=20nmNF =1VDD=0.9V
IDAP
-0.9 -0.6 -0.3 0 0.3 0.6 0.9-80
-60
-40
-20
0
20
40
Drain bias VD (V)
Dra
in c
urre
nt I D
P, I
DA
P (A
)
IDP
IDAP
P AP
AP P
VG=VDD
0 0.3 0.6 0.90
10
20
30
40
50
60
Mag
neto
curre
nt ra
tio
MC (%
)
Drain bias VD (V)
VG=0 - 0.9V in steps of 0.1V
CIMSCIMS
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
VQ
B (V
)
(1,1,1,1)
(1,2,1,1)
0.285V
0.276V0 0.3 0.6 0.9
0
0.3
0.6
0.9
VQ (V)
V QB
(V)
(1,1,1,1)
(1,2,1,1) 0.097V
0.142V
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
V QB (V
)
(1,1,1,1)
(1,2,1,1)
0.277V
0.224V
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
V QB
(V)
VSR=0.9V
P AP
MTJ1: PMTJ2: AP
0.65V
0.157V0.220V
0 0.3 0.6 0.90
0.3
0.6
0.9
VQ (V)
V QB (V
)
(VSR, VCTRL)=
MTJ2: AP P
MTJ1: AP P
MTJ1: APMTJ2: AP
(0.65V, 0.5V)(0.65V, 0.5V)(0.9V, 0.9V)
0.109V0.204V
0 0.3 0.6 0.90
0.3
0.6
0.9 VDD=0.9V
VQ (V)
VQ
B (V
)
VQ=VQB
MTJ1: APMTJ2: P
Vsupply=0.20.30.40.5
0.60.70.80.9V
TrajectoryP AP
VSR=0.65V
Trajectory( 5)
KAST 平成26年度研究概要 2015.7.29- 153 -
100 101 102 10310-14
10-12
10-10
10-8
tSL = 0, 10n, 100n, 1 , 10 s
NOF cell
NVPG cell
6T cell
E cyc
per
cel
l (J)
nRW
M = N = 32 (128 B)tSD = 0 s
10-10 10-8 10-6 10-4 10-2 10010-10
10-8
10-6
10-4
NOF cell
NVPG cell
6T cell
Ecy
c(W
s)
tSD (s)
BET
nRW = 10M=32 N=256 (1 kB)
tSL = 100ns
T = 10 K
wFM = 100 μmsf = 120 ps
Magnetic field (Oe)
Nor
mal
ized
Han
le−e
ffect
sig
nal
Lorentz function
This workExperimentaldata
−5000 0 50000.0
0.5
1.0
0
20
40
60
80
Time
Power(W)
0
20
40
60
80
Power(W)
0
20
40
60
80
Power(W)
Read
Shutdown(tSD)
Sleep 2 (tSD)
Read Store
ReadShut-
down 2(tSD)
Sleep 1 (tSL)
nRW
Sleep (tSL)
nRW
Shut-down 1
(tSL)
N timesN times
N times
N timesN times
N times
N times
20 nsWrite
WriteNVPG
OSR
NOFnRWWrite/Store
0
20
40
60
80
Time
Power(W)
0
20
40
60
80
Power(W)
0
20
40
60
80
Power(W)
Restore
Read Write
Read Write
2 ns
NVPG
OSR
Wake-up/Read/Shutdown Shut-
downWrite
H-store L-storeNOFWake-up
100 101 102 10310-14
10-13
10-12
10-11
10-10
10-9
tSL=0, 10n, 100n, 1 s
NVPG
OSR
Ecy
c per
cel
l (J)
nRW
NOF
M=N=32 (128B)tSD= 0s
100 101 102 10310-5
10-4
10-3
10-2
10-1
nRW
BET
(s)
N=32, 256, 512, 1024, 2048
M=32tSL= 100ns
NOF
NVPG
MTJ2
QBQ
WL
D
VVDD
VCTRL
VSRVSR
DB
PS-MOSFET
MTJ1 fp
fp
VDD
VPGPowerswitch
QBQ
WL
D
VVDD
fp
fp
VDD
VPGPowerswitch
0 5 10 15 20
0.6
0.8
1
1.2
W/L
Virtu
al V
DD
(V)
Normal SRAM op. of NVPG cell
Write (Store) op.of NOF cell
(95%)
Store op. of NVPG cell
KAST 平成26年度研究概要 2015.7.29- 154 -
100 101 102 10310-14
10-12
10-10
10-8
tSL = 0, 10n, 100n, 1 , 10 s
NOF cell
NVPG cell
6T cell
E cyc
per
cel
l (J)
nRW
M = N = 32 (128 B)tSD = 0 s
10-10 10-8 10-6 10-4 10-2 10010-10
10-8
10-6
10-4
NOF cell
NVPG cell
6T cell
Ecy
c(W
s)
tSD (s)
BET
nRW = 10M=32 N=256 (1 kB)
tSL = 100ns
T = 10 K
wFM = 100 μmsf = 120 ps
Magnetic field (Oe)
Nor
mal
ized
Han
le−e
ffect
sig
nal
Lorentz function
This workExperimentaldata
−5000 0 50000.0
0.5
1.0
0
20
40
60
80
Time
Power(W)
0
20
40
60
80
Power(W)
0
20
40
60
80
Power(W)
Read
Shutdown(tSD)
Sleep 2 (tSD)
Read Store
ReadShut-
down 2(tSD)
Sleep 1 (tSL)
nRW
Sleep (tSL)
nRW
Shut-down 1
(tSL)
N timesN times
N times
N timesN times
N times
N times
20 nsWrite
WriteNVPG
OSR
NOFnRWWrite/Store
0
20
40
60
80
Time
Power(W)
0
20
40
60
80
Power(W)
0
20
40
60
80
Power(W)
Restore
Read Write
Read Write
2 ns
NVPG
OSR
Wake-up/Read/Shutdown Shut-
downWrite
H-store L-storeNOFWake-up
100 101 102 10310-14
10-13
10-12
10-11
10-10
10-9
tSL=0, 10n, 100n, 1 s
NVPG
OSR
Ecy
c per
cel
l (J)
nRW
NOF
M=N=32 (128B)tSD= 0s
100 101 102 10310-5
10-4
10-3
10-2
10-1
nRW
BET
(s)
N=32, 256, 512, 1024, 2048
M=32tSL= 100ns
NOF
NVPG
MTJ2
QBQ
WL
D
VVDD
VCTRL
VSRVSR
DB
PS-MOSFET
MTJ1 fp
fp
VDD
VPGPowerswitch
QBQ
WL
D
VVDD
fp
fp
VDD
VPGPowerswitch
0 5 10 15 20
0.6
0.8
1
1.2
W/L
Virtu
al V
DD
(V)
Normal SRAM op. of NVPG cell
Write (Store) op.of NOF cell
(95%)
Store op. of NVPG cell
KAST 平成26年度研究概要 2015.7.29- 155 -
業 績 【論文発表】 1. Yu Kawame, Taiju Akushichi, Yota Takamura, Yusuke
Shuto, and Satoshi Sugahara “Fabrication and characterization of a spin injector using a high-quality B2-ordered-Co2FeSi0.5Al0.5 /MgO /Si tunnel contact” J. Appl. Phys., to be published in 2015.
2. Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara “Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology” 18th Design, Automation and Test in Europe (DATE15), Grenoble, France, March 9-13, 2015, paper 7.7.3.
3. Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara “Comparative Study of Power-Gating Architectures for Nonvolatile SRAM Cells Based on spintronics Technology” 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014), Ishigaki, Okinawa, Japan, November 17-20, 2014.
4. Yu Kawame, Taiju Akushichi, Yota Takamura, Yusuke Shuto, and Satoshi Sugahara “Fabrication and characterization of a spin injector using a high-quality B2-ordered-Co2FeSi0.5Al0.5 /MgO /Si tunnel contact” 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper AH-09
5. Yota Takamura, Taiju Akushichi, Yusuke Shuto, and Satoshi Sugahara “Analysis and design of nonlocal spin devices with bias-induced spin-transport acceleration” 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper GS-07.
6. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara "0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture" 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014), Yokohama, Japan, September 9-11, 2014, paper 11-4.
7. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara "Design and performance of nonvolatile SRAM cells based on pseudo-spin-FinFET architecture" 2014 IEEE Silicon Nanoelectronics Workshop (SNW2014), Honolulu, HI, USA, June 8-9, 2014, submitted.
8. Y. Takamura, T. Akushichi, A. Sadano, T. Okishio, Y. Shuto, and S. Sugahara “Analysis of Hanle-effect signals observed in
Si-channel spin accumulation devices” J. Appl. Phys. 115, 17C307 (2014).
9. Y. Takamura, A. Sadano, T. Akushichi, T. Okishio, Y. Shuto, and S. Sugahara “Analysis of Hanle-effect signals observed in Si-channel spin accumulation devices” 58th Annual Conference on Magnetism and Magnetic Materials (MMM2013), Denver, CO, USA, November 4-8, 2013, paper AX-05.
10. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara "FinFET-based pseudo-spin-transistor: Design and performance" 2013 IEEE International Semiconductor Conference Dresden-Grenoble (ISCDG), Dresden, Germany, September 26-27, 2013.
11. 川目悠, 悪七泰樹, 髙村陽太, 周藤悠介, 菅原聡, “Fabrication of a (100)-oriented Co2FeSi0.5Al0.5/MgO/Si tunnel contact and its spin injector application” 第 19 回 半導体スピン工学の基礎と応用 (PASPS-19), 文京区, 東京, Dec. 15-16, 2014, paper P-20.
12. 川目悠, 悪七泰樹, 周藤悠介, 髙村陽太, 菅原聡, “B2 型 Co2FeSi0.5Al0.5/MgO/Si スピン注入源の作製と
評価” 第 38 回 日本磁気学会学術講演会, 横浜市, 神奈川, Sept. 2-5, 2014, paper 4aD-3.
13. 髙村陽太, 悪七泰樹, アディユダサドノ, 周藤悠介, 菅原聡 “Analysis of Hanle-effect signals observed in a Si-channel spin-accumulation device with a high-quality CoFe/MgO/Si spin injector” 2014 年 第 61 回応用物理学春季学術講演会, 相模
原市, 神奈川, March 17-20, 2014, paper 17a-E7-22. 14. 周藤悠介, 山本修一郎, 菅原聡
“FinFET を用いた擬似スピン MOSFET とその不揮発
性 SRAM への応用” 2014 年 第 61 回応用物理学春季学術講演会, 相模
原市, 神奈川, March 17-20, 2014, paper 19a-F12-6. 【特許】
国内特許出願 1 件 【記者発表、取材】
(1)「不揮発性パワーゲーティングが CMOS ロジックシス
テムの待機時電力削減に威力―不揮発性 SRAM を用い
た記憶回路で実証―」,神奈川科学技術アカデミー,
2015 年 3 月 12 日,東京工業大学,2015 年 3 月 20 日 https://www.newkast.or.jp/press/press_150312.html http://www.titech.ac.jp/news/2015/030190.html
目次用
【他機関(マスコミ)等による記事掲載】
(1) 不揮発性パワーゲーティング、メニーコアプロセッサの
待機電力削減に威力 EE TIMES Japan,2015 年 3 月 25 日 http://eetimes.jp/ee/articles/1503/25/news075.html
(2) 「不揮発性はパワーゲーティングにこそ生きる」、東工
大が SRAM+MTJ で実証 日経テクノロジーOnline,2015 年 3 月 31 日 http://techon.nikkeibp.co.jp/article/EVENT/20150328/411560/?rt=nocnt
KAST 平成26年度研究概要 2015.7.29- 156 -
業 績 【論文発表】 1. Yu Kawame, Taiju Akushichi, Yota Takamura, Yusuke
Shuto, and Satoshi Sugahara “Fabrication and characterization of a spin injector using a high-quality B2-ordered-Co2FeSi0.5Al0.5 /MgO /Si tunnel contact” J. Appl. Phys., to be published in 2015.
2. Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara “Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology” 18th Design, Automation and Test in Europe (DATE15), Grenoble, France, March 9-13, 2015, paper 7.7.3.
3. Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara “Comparative Study of Power-Gating Architectures for Nonvolatile SRAM Cells Based on spintronics Technology” 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014), Ishigaki, Okinawa, Japan, November 17-20, 2014.
4. Yu Kawame, Taiju Akushichi, Yota Takamura, Yusuke Shuto, and Satoshi Sugahara “Fabrication and characterization of a spin injector using a high-quality B2-ordered-Co2FeSi0.5Al0.5 /MgO /Si tunnel contact” 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper AH-09
5. Yota Takamura, Taiju Akushichi, Yusuke Shuto, and Satoshi Sugahara “Analysis and design of nonlocal spin devices with bias-induced spin-transport acceleration” 59th Annual Magnetism and Magnetic Materials Conference (MMM2014), Honolulu, HI, USA, November 3-7, 2014, paper GS-07.
6. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara "0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture" 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014), Yokohama, Japan, September 9-11, 2014, paper 11-4.
7. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara "Design and performance of nonvolatile SRAM cells based on pseudo-spin-FinFET architecture" 2014 IEEE Silicon Nanoelectronics Workshop (SNW2014), Honolulu, HI, USA, June 8-9, 2014, submitted.
8. Y. Takamura, T. Akushichi, A. Sadano, T. Okishio, Y. Shuto, and S. Sugahara “Analysis of Hanle-effect signals observed in
Si-channel spin accumulation devices” J. Appl. Phys. 115, 17C307 (2014).
9. Y. Takamura, A. Sadano, T. Akushichi, T. Okishio, Y. Shuto, and S. Sugahara “Analysis of Hanle-effect signals observed in Si-channel spin accumulation devices” 58th Annual Conference on Magnetism and Magnetic Materials (MMM2013), Denver, CO, USA, November 4-8, 2013, paper AX-05.
10. Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara "FinFET-based pseudo-spin-transistor: Design and performance" 2013 IEEE International Semiconductor Conference Dresden-Grenoble (ISCDG), Dresden, Germany, September 26-27, 2013.
11. 川目悠, 悪七泰樹, 髙村陽太, 周藤悠介, 菅原聡, “Fabrication of a (100)-oriented Co2FeSi0.5Al0.5/MgO/Si tunnel contact and its spin injector application” 第 19 回 半導体スピン工学の基礎と応用 (PASPS-19), 文京区, 東京, Dec. 15-16, 2014, paper P-20.
12. 川目悠, 悪七泰樹, 周藤悠介, 髙村陽太, 菅原聡, “B2 型 Co2FeSi0.5Al0.5/MgO/Si スピン注入源の作製と
評価” 第 38 回 日本磁気学会学術講演会, 横浜市, 神奈川, Sept. 2-5, 2014, paper 4aD-3.
13. 髙村陽太, 悪七泰樹, アディユダサドノ, 周藤悠介, 菅原聡 “Analysis of Hanle-effect signals observed in a Si-channel spin-accumulation device with a high-quality CoFe/MgO/Si spin injector” 2014 年 第 61 回応用物理学春季学術講演会, 相模
原市, 神奈川, March 17-20, 2014, paper 17a-E7-22. 14. 周藤悠介, 山本修一郎, 菅原聡
“FinFET を用いた擬似スピン MOSFET とその不揮発
性 SRAM への応用” 2014 年 第 61 回応用物理学春季学術講演会, 相模
原市, 神奈川, March 17-20, 2014, paper 19a-F12-6. 【特許】
国内特許出願 1 件 【記者発表、取材】
(1)「不揮発性パワーゲーティングが CMOS ロジックシス
テムの待機時電力削減に威力―不揮発性 SRAM を用い
た記憶回路で実証―」,神奈川科学技術アカデミー,
2015 年 3 月 12 日,東京工業大学,2015 年 3 月 20 日 https://www.newkast.or.jp/press/press_150312.html http://www.titech.ac.jp/news/2015/030190.html
【他機関(マスコミ)等による記事掲載】
(1) 不揮発性パワーゲーティング、メニーコアプロセッサの
待機電力削減に威力 EE TIMES Japan,2015 年 3 月 25 日 http://eetimes.jp/ee/articles/1503/25/news075.html
(2) 「不揮発性はパワーゲーティングにこそ生きる」、東工
大が SRAM+MTJ で実証 日経テクノロジーOnline,2015 年 3 月 31 日 http://techon.nikkeibp.co.jp/article/EVENT/20150328/411560/?rt=nocnt
KAST 平成26年度研究概要 2015.7.29- 157 -
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