TA ESE 555

CONTENTSWHAT IS A SCHEMATIC AND HOW TO MAKE ONEWHAT IS A SYMBOL AND HOW TO MAKE ONEPRE-LAYOUT SIMULATIONWHAT IS A LAYOUTHOW TO VISUALIZE A LAYOUT WRT A FABRICATED CHIPHOW TO COME UP WITH A LAYOUTPOST LAYOUT SIMULATION

SCHEMATIC

• Diagrammatic representation of a circuit which shows the constituent elements and also gives information about the circuit connections• Also has information about the properties of the transistors e.g. the

size, numbers and the inputs and outputs for the circuit.• Can have virtual connection to make the schematic less clumsy!!• DO NOT PLACE THE POWER AND GROUND SOURCES IN A SCHEMATIC

AT THE LOWER HEIRARCHY.

SYMBOL

• Short hand representation of a bigger circuitry without showing the internal circuitry.• Used on higher hierarchies to make the circuit visualization

less complicated.

PRE-LAYOUT SIMULATION

• Done in order to check whether the design meets the desired requirements.• Performed on the highest hierarchy of the design.• Place all the sources (including Power and Ground) at the

level which you will be simulating.

LAYOUT

• Layout is the diagrammatic representation of the real circuit that is finally fabricated.• Contains the layers and routing details of the circuit.• Place all the pins that are present in the corresponding

schematic taking care of the types e.g. input, output, inout etc.• NEVER USE VIRTUAL CONNECTIONS (LABELS) AS IT IS THE

FINAL CIRCUIT THAT IS FABRICATED

VISUALISING A LAYOUT

DESIGNING A LAYOUT• Use the stick diagram approach to get the placements and routing idea.• Try to share the terminals to maximum possible extent if area is a constraint.• Always place PMOS in one line and NMOS in another. NEVER PLACE THEM ON

SAME HORIZONTAL LINE!!!• Place the taps/substrate connections on the top and/or bottom of the devices.• Run and clear the DRCs as you progress with layout and never keep it for the

end. Results can be disastrous!!!• Always extract the layout before you run LVS• Do Not run DRC on the extracted file.• For a layout also use hierarchies same as schematic and use instances of

layouts in higher hierarchies.

POST LAYOUT SIMULATION

• Process is exactly same as schematic.• Write ‘extracted’ before the ‘schematic’ in the window which

pops up.• Best thing (as per me) is to replace ‘schematic’ with

‘extracted’ in the window.

GENERAL INSTRUCTIONS ON REPORTS

• The screenshots did not show the delay properly. Use markers/zoom-in• Include comparisons where it is mentioned. (pre vs post layout

simulation)• Do not need to show the steps. Only the simulation graphs with proper

markers.• Must include DRC and LVS reports screenshot.• Check and double check if all the things mentioned at the end of the

assignment is included in the report.

ADDITIONAL THINGS

• Demo of fixing DRC and LVS• How to measure propagation delay with an example