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Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 1 Lecture #6: More Complex Combinational Logic Circuits
Exclusive OR/Exclusive NOR (XOR/XNOR)
• XOR and XNOR are useful logic functions. • Both have two or more inputs. The truth
table for two inputs is shown at right. • a XOR b = 1 if and only if (iff) a ≠ b. • a XNOR b = 1 if and only if (iff) a = b. • Both may also have many inputs. For >2
inputs, the XOR output is 1 for an odd number of 1 inputs; XNOR has a 1 output for an even number of 1 inputs.
• Symbols are shown below and to the right.
XOR/XNOR Truth Table a b a XOR b a XNOR b 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1
Like NAND and NOR, XOR and XNOR are not basic Boolean functions, but can be made from AND, OR and NOT.
XOR = ab ab+
XNOR = ab ab+
a b
a b
XOR
XNOR
a b⊕
a b
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 2 Lecture #6: More Complex Combinational Logic Circuits
Quick Simplification Review • The first technique we studied to simplify a
Boolean expression used algebraic techniques. • For instance, consider the truth table at right. • The minterms shown represent the SOP
expression: • The Boolean expression is easily simplifiable
using the Boolean identities:
• The simplified circuit is shown below the
truth table.
a b c f 0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1 f abc abc abc abc= + + +( ) ( )f ab c c ac b b= + + +
1 1
f abc abc abc= + +
f ab ac= +
f abc abc abc= + +
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15
Quick Simplification Review (2) • We can also plot the minterms on a K-map
and graphically simplify the expression (and the circuit).
• On the K-map below, the three minterms ( ) are plotted.
• The simplified expression derived from the two prime implicants is the same as that using algebraic simplification.
3 Lecture #6: More Complex Combinational Logic Circuits
a b c f 0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
, , abc abc abc
0 1 3 2
4 5 7 6
000 001 011 010
100 101 111 110
aa
c b bc bc bc
1 1 1
Identical circuit solution using K-map method: f ab ac= +
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 4 Lecture #6: More Complex Combinational Logic Circuits
Exercise 1 • Let’s do another simplification exercise before moving on.
Consider this “spec:” The function f of three variables, x, y, and z, is 1 when x and y are both 1 or when x and z are both 1. Find the SOP expression, the simplified expression, and the simplified circuit. Use the K-map on the next slide to perform the same simplification.
x y z f 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0 0 1 1 1
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15
0 1 3 2
4 5 7 6
000 001 011 010
100 101 111 110
xx
z y yz yz yzK-Map Solution
5 Lecture #6: More Complex Combinational Logic Circuits
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 6 Lecture #6: More Complex Combinational Logic Circuits
Decoders • An n-to-2n decoder is a combinational logic circuit that has n inputs and
up to 2n outputs. That is, it can have 2n outputs, but it may have less. • Each output of a decoder will normally be true (i.e., go to logic 1) for only
one combination of the n inputs. • Consider the case of an n = 2 decoder. The decoder will have 2 inputs and
up to 2n = 22 = 4 outputs. • Assume that the decoder has the maximum possible number of outputs
(4). Then the truth table for the 2-input decoder will show that for each combination of y and x (00, 01, 10, 11), one of the outputs will go high (logic 1).
• Let us call the inputs y and x and the outputs a, b, c, and d (here, x is the more significant bit). Then let us define a = 1 for x = 0, y = 0; b = 1 for x = 0 and y = 1; c = 1 for x = 1 and y = 0, and d = 1 for x = 1 and y = 1.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 7 Lecture #6: More Complex Combinational Logic Circuits
Decoders (2) • The truth tables for a-d in our 2-to-4 decoder are: x y * a b c d 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 • Using the truth tables above, we can define a-d in terms of x and y.
Boolean expressions for a, b, c, and d in terms of x and y.
* Note that we put x first because we regard the xy pair as a number, with x the more significant bit.
a x y
b xy
c x yd xy
=
=
==
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 8 Lecture #6: More Complex Combinational Logic Circuits
Decoders (3)
• Remembering that • If we consider xy a binary number with x
the MSB and y the LSB, then a-d represent a true condition for each of the four possible binary numbers that x and y can represent.
• Thus we say that each output a-d has an address, which is a unique combination of the two bits in the binary number yx:
• Based on the logic expressions above, we can draw the decoder circuit as shown at right.
x y a
b
c
d
, , , :a x y b xy c x y and xy= = = =
For 00, 1; for 01, 1;for 10, 1; for 11, 1.
xy a xy bxy c xy d
= = = == = = =
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 9 Lecture #6: More Complex Combinational Logic Circuits
Decoders (4) • In the same way, a decoder with 3 inputs
may have up to 23 = 8 outputs, and each output will have a unique “address” that represents one of the eight possible combinations of the three inputs.
• Such a circuit is shown to the right. • In the same way, a 4-input decoder could
have up to 24 = 16 outputs, each of which is a unique combination of the inputs.
• Etc., for 5, 6, 7… • Two Notes:
– Any n-input decoder can have up to 2n outputs, but it may have less.
– In general, each output for an n-input decoder is created by a single n-input AND gate. Its inputs are the n decoder inputs, some of which may be inverted.
3-input, eight- output
decoder
a b c d e f g h
x y z
g x y z
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 10 Lecture #6: More Complex Combinational Logic Circuits
Definition of a Multiplexer
• A multiplexer is a combinational logic circuit that has up to 2n inputs, an n-bit address, and one output.
• The multiplexer connects one of the inputs to the output, depending on the value of the n-bit address.
• The n-bit address is decoded, just as we have studied in the last five slides.
• Thus the multiplexer uses a decoder and a selector circuit (which we will see in a subsequent slide) to tie one of its inputs to its output.
• The multiplexer is usually symbolized by the abbreviation MUX as the symbol for its function.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 11 Lecture #6: More Complex Combinational Logic Circuits
Multiplexer: An “Input to Output” Selector
• The truth table for a multiplexer is shown below. • Assume a 4-input MUX, with inputs labeled a, b, c, d. • Then there must be two address lines, x (MSB) and y (LSB). • The output is denoted as f.
x y f 0 0 a 0 1 b 1 0 c 1 1 d
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15
Decoder
Selector
Output*
* Note that the multiplexer has a 1-bit output.
a
b
c
d
x
y
f
12 Lecture #6: More Complex Combinational Logic Circuits
Components of a Multiplexer
• The multiplexer is shown above, with the various parts of the circuit labeled.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 13 Lecture #6: More Complex Combinational Logic Circuits
Differences in Decoder and Multiplexer • Decoder:
– A decoder has n inputs, which are called the address. – A decoder has up to 2n outputs (it can have that many, maximum; but it
might have less). Each output line is true (or 1) for a specific combinations of the input lines, called the address.
• Multiplexer: – A multiplexer has two sets of inputs: n address lines (just like the
decoder) and as many as 2n inputs, one of which is selected by each address for output (it may have less inputs).
– A multiplexer has only one output. The output is the value of the input selected by the address.
• Thus we see that a decoder makes up a part of a multiplexer.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 14 Lecture #6: More Complex Combinational Logic Circuits
Exercise 2 • Let’s design a simple decoder
and multiplexer. A decoder has a three-input address, x-z, with x = MSB, but although it may have up to 23, or 8 outputs, in this case, it has only three. Output 1 is true on address 3, 2 on address 6, and 3 on address 7. Design the decoder.
Now using the decoder and adding a selector circuit, design a MUX to output the inputs a-c on addresses 3, 6, and 7, respectively.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 15 Lecture #6: More Complex Combinational Logic Circuits
Binary Arithmetic Circuits • A binary adder is a large part of a computer central processor unit
(CPU). The CPU “figuring” unit is sometimes called the ALU, or arithmetic/logic unit, (Patterson and Hennessey call it the “datapath”).
• The ALU or datapath is a combinational logic unit that can add, subtract, or do logical operations such as AND, OR, NOT, etc.
• Consider the “rules of addition” (adding two numbers only*): – Numbers are added on a columnar basis, starting on the right. – If the sum of one column is a 2-digit number, the right number goes in
current column, and the left number (always a 1) becomes a “carry” to the next column to the left.
– Column addition always includes the carry from the column to the right. – The resulting sum in any column will be only a single digit.
* A computer never adds but two numbers together at one time.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 16 Lecture #6: More Complex Combinational Logic Circuits
Principles of Addition • Decimal addition example:
“Carries” → 1 1 5 8 7
6 4 3 1 2 3 0
• Binary numbers are added in exactly the same way: “Carries” → 1 1 1 1 1 1 1 1
1 0 1 0 1 0 0 0 1 1 1 + 0 1 1 1 1 1 1 0 1 0 1 (1) 0 0 1 0 0 1 1 1 1 0 0 • Basic principles for an n-column addition:
– Add column i plus carry from column i–1 (ci–1). – If a one-digit result, that number is the sum of column i, si. – If a 2-digit result, the right digit is si. The left digit is carry i, or ci. – The column i carry, ci, will be added to column (i+1).
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 17 Lecture #6: More Complex Combinational Logic Circuits
A “Half-Adder” Circuit • We would now like to design a digital
adder for two binary numbers. • Since addition is done on a columnar
basis, all that is necessary to add two n-bit numbers, is to use one binary “column adder” for each of the n bits.
• Thus, to add two 8-bit numbers, we simply use eight column adders.
• First we consider a 2-bit “half-adder.” The truth table on the right shows sum and carry bits for the 2 input bits a & b.
• Thus, “sum” is the simple SOP expression: . Likewise, carry out is defined as: The SOP representation of the 2-bit half adder is at the right.
Half-Adder Circuit
a
b S Co
a b S co S Exp co Exp 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
S ab ab= +oC ab=
ab
abab
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 18 Lecture #6: More Complex Combinational Logic Circuits
Alternate Construction of a Half-Adder • We note that in a half-adder, the sum s
is expressed as: • As noted on the first slide today, this is
the expression for the XOR gate. • Thus an alternate expression for s is: • Note that carry out is still: . • We can then construct the logic gate
equivalent of the half-adder as shown on the right.
• Note that this is no longer a “standard” SOP representation, but it is easier to build!
s ab ab= +
s a b= ⊕oC ab=
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 19 Lecture #6: More Complex Combinational Logic Circuits
“Half-Adder” in Action
= 0, =1
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 20 Lecture #6: More Complex Combinational Logic Circuits
The “Full Adder” • The half-adder circuit is an important step in
building a digital adder, but it is not the total solution to the binary addition problem.
• When adding binary numbers on a columnar basis, in addition to the column bits, ai and bi, there is also the possibility of a carry bit, ci-1 from the column to the right. Thus the 2-bit column adder must be a 3-bit adder.
• This 3-bit adder is called a “full adder.” • In adding two n-bit binary numbers, the right-
most bits of the two numbers of two numbers could be added with a half-adder (no carry in).
• However, most adder circuits use all full-adders, since carry-in for the least significant bit can be useful; we will see that use later in this lecture.
(ci–1) + ai + bi si
(ci) +
ai+1 +
bi+1 si+1
Col (i+1) Col (i) Col (i–1)
(ci–2) +
ai–1 +
bi–1 si–1
Columnar Addition
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 21 Lecture #6: More Complex Combinational Logic Circuits
Full Adder Boolean Equations • The full column adder
truth table is shown, along with SOP terms for the 1’s in the S and co columns.
• For the sum SOP function:*
• For the carry out SOP
function: • The SOP circuit for the
full adder is shown on the next slide.
a b ci S co S Exp co Exp 0 0 0 0 0 1 0 0 1 0 * 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1
* For simplicity, we represent “carry in” above simply as c.
abcabc
abc
abc abc
abc
abcabc
S abc abc abc abc= + + +
oC abc abc abc abc= + + +
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 22 Lecture #6: More Complex Combinational Logic Circuits
SOP Circuit for a Full Adder
• Above is the SOP equivalent circuit for a full adder. Note that sum and carry have a common term.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 23 Lecture #6: More Complex Combinational Logic Circuits
Alternate Construction of Full Adder • We note that since we can construct
a full-adder similarly to a half-adder, then we should be able to use the alternate half-adder (XOR logic) to construct a full adder.
• That is, for the full adder, – – – Where c = cin
• The equivalent logic construction is shown in the circuit on the right.
• The exact proof is left to the student. • Although this is an easier circuit to
build (XOR’s simplify the circuit), it is NOT in correct SOP or POS form.
( )S a b c= ⊕ ⊕( )oC ab a b c= + ⊕
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 24 Lecture #6: More Complex Combinational Logic Circuits
32-Bit Adder
• A 32-bit adder would be made up like this: The 32 1-digit full adders would be wired up so that each would add one column of two 32-bit numbers (a half-adder could be used in column 1).
1-digit (2-bit) full adder
32-digit (2-bit) adder May be a half-adder
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 25 Lecture #6: More Complex Combinational Logic Circuits
Subtraction • In the past, digital subtractors were constructed as well as digital adders.
However, it quickly became apparent that the subtraction function could be added very easily to a digital adder.
• Consider the following: – A 1-bit full adder produces carry out (cO) and sum (s) outputs from carry in
(ci) and numerical (a and b) inputs. • We note that , so that we can
subtract using an adder if we: – Invert b (can obtain via an XOR). – Set the carry in input (ci) of bit 0 to 1 (which is why we would need a full adder
even in column 1 of the binary adder circuit). • To select subtraction, we need two control signals: • “Invert b” – which selects instead of b. • Carry in, column 1 – which sets ci = 1 for bit 0. • We can combine these into one control signal, Add–/Sub+
2's complement( ) ( ) 1a b a b a b− = + = + +
b
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 26 Lecture #6: More Complex Combinational Logic Circuits
Four-Bit Binary Add/Subtract Circuit
B
Add-/Sub+
Ci
A
BCi
C0
Ci
CiB
B
A
A
A
C1
C3
S0S1S2S3
C2
A0A1A2A3
B0B1B2B3
4-Bit Adder Section Add/Subtract Selector
1-Bit Full Adder (Used 4 Times)
Outputs
Inputs
If the Add−/Sub+ input is high, the XOR’s invert the B input, while if it is low, the B input is not changed.
Carry in = 1 for subtract.
Note that the Add−/Sub+ line must be XOR’ed with the C3 line to be correct for the subtract case.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 27 Lecture #6: More Complex Combinational Logic Circuits
The ALU or “Datapath”
• We have already noted that the arithmetic/logical unit (ALU, or what P&H call the “datapath”) is the “calculating” unit of the computer central processor.
• The amazing thing about the ALU is that it is mostly combinational logic composed of the very logic functions that we have studied so far!
• Patterson & Hennessy discuss a simple version ALU in Chapter 4 of their book that only functions as an AND/OR/add/subtract/compare unit.
• This ALU takes the “columnar” approach we have discussed for a binary adder.
• Their 32-bit ALU (the prototype for the MIPS R2000 computer we will learn to program later on) is composed of 32 of the 1-bit ALUs.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 28 Lecture #6: More Complex Combinational Logic Circuits
A 1-Bit ALU
The 1-bit ALU provides all the possible results of logic/arithmetical analysis to the 4-1 MUX. The 2-bit select address (derived from decoding a part of the computer instruction) selects the desired result and outputs it. For instance, outputting the borrow signal provides a comparison of a and b.
1-bit Full Adder/ Subtractor 4-to-1 MUX
2-Bit MUX Select Address OR
AND
Sum
Carry/ Borrow
1-Bit Result Out
Carry In
a
b
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 29 Lecture #6: More Complex Combinational Logic Circuits
“Bit Slicing:” N 1-bit ALU’s = N-Bit Processor • Thirty-two of the one-bit ALU’s shown on the previous page may be
combined to form a 32-bit MIPS CPU (which we will study later). • In the 32-bit ALU, an operation is performed on all bits at once using
the 32 separate 1-bit ALU’s. This “slices” the data into 32 bits, which is where the name “bit slicing” comes from.
• This approach works well for AND and OR functions. • For add and subtract, we have to propagate carries from each lower
column to the next higher column. This means that in a 32-bit computer, we have 32 carries (the 32nd carry would be “overflow”).
• All these carries/borrows are VERY time-consuming, and so some special digital “fast carry” circuits have been developed to accelerate the carry/borrow action (they are not shown on the 1-bit ALU diagram).
• These accelerators are not covered in EE 2310.
Erik Jonsson School of Engineering and Computer Science
The University of Texas at Dallas
© N. B. Dodge 9/15 30 Lecture #6: More Complex Combinational Logic Circuits
Exercise 3 • As a special exercise in reviewing the
digital adder plus some of the principles we learned earlier, consider the following: The SOP Boolean expression for a full adder carry out is:
This expression can be simplified to three terms. Do so. Then show the circuit design.
, where o iC abc abc abc abc c c= + + + =
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