Προηγμένες Αρχιτεκτονικές Υπολογιστών Εισαγωγή. Κ. Διαμαντάρας Α. Βαφειάδης Τμήμα Πληροφορικής ΑΤΕΙ Θεσσαλονίικης 2011. Στοιχεία επικοινωνίας. Καθηγητής : Κώστας Διαμαντάρας Email: [email protected] URL: http://www.it.teithe.gr/~kdiamant Τηλ. 2310 013592 - PowerPoint PPT Presentation
. . 2011 1This ToolBox presentation is the sole property ofFORE
Systems, Inc. All Rights Reserved. / & 2 : Email:
[email protected]: http://www.it.teithe.gr/~kdiamant. 2310
013592, http://blackboard.teithe.gr
. . / & 3: , SISD, MISD, SIMD, MIMD, UMA, NUMA, ( , ), , , :
, cache, cache, cache, cache, cache, cache coherence, snooping,
directory-basedPipelining: pipeline , , DLX, pipeline DLX,
pipeline, pipeline , , , , pipeline. : Amdahl, , , , : , , , , , /
, /Clusters Grids: , cluster Google
. . , , / & 4 MPI (Message Passing Interface).MPI = cluster
desktop (. Windows) .: MPI 30% (+ 70% ) = 100% . . / & 5 CPU
Amdahl. . 5This ToolBox presentation is the sole property ofFORE
Systems, Inc. All Rights Reserved. Von Neumann / & 6 ALU 1 1 .
. . . .. . . . . / (Bus) (Bus) I/O. . / & 7Pipelining: , , : :
(cache) (virtual memory).. . / & 8 chip. chip (1cm 2cm) .
. . chip / & 9
. . CPU / & 10: Intel
. . 10This ToolBox presentation is the sole property ofFORE
Systems, Inc. All Rights Reserved. / & 11~2004 : , ( )
pipelining, . . : / & 12 . (cores) chip ( !). . : 1 / &
13
Intel Xeon (Nehalem): 8 . . : 2 / & 14 AMD Opteron (Magny
Cours): 12
. . / & . . 15 FlynnInstruction Stream: Data Stream:
SingleMultipleSingleSISDMISDMultipleSIMDMIMDInstruction
StreamDataStream / & . . 16 SISD: Single Instruction - Single
Data - ( )CU: Control UnitPU: Processing UnitM: MemoryI/O:
Input/OutputIS: Instruction StreamDS: Data StreamCUPUMISDS/ / &
. . 17MISD: Multiple Instruction - Single DataMISD = Pipeline MISD.
pipelining , instruction pipeline.CU2PU2MIS2DSCU1PU1IS1CUPUIS. . .
. . . . . / & . . 18SIMD: Single Instruction - Multiple Data .
Host (. Linux Pentium) CUPU2M1ISDS1PU1PU. . . . . . . .M2MDS2DSHost
/ & . . 19MIMD: Multiple Instruction - Multiple Data
CU1PU2M1IS1DS1PU1PU. . . . . . . .M2MDS2DSIS2ISCU2CU / & . .
20MIMD: Multiple Instruction - Multiple Data (2)CU1PU2MIS1DS1PU1PU.
. . . . . . .DS2DSIS2ISCU2CU Bus / & . . 21 MIMD MIMD (. Intel
Pentium)
MIMD- ( )- ( ) / & . . 22- .1cache1Bus.2cache2.NcacheN. . .
. ./ / & . . 23- 1.1cache1.2cache2.NcacheN. . . . .2/// / &
. . 24 : (. ). . : i i. . / & . . 25 - : . i j (message
passing) : . i / & . . 26 - . SISD. .Cache cache -Bus (
