Semu®

---Desktop Emulation

Hyper-Blue Co.,Ltd.

合肥海本蓝科技有限公司

Contents

About Hyper-Blue Co.,Ltd.

Product Over View

Product Key Benefits

Product Objectives

Target Customers

Product Design Flow

Application

Rich roadmap of features & capacities

About Hyper-Blue Co.,Ltd.

Founded in 2015

Headquarter in Hefei , Anhui , China

Be Ventured by HyperSilicon Co.,Ltd. And

China Hai Heng Investment Holding

Corporation

Registered Capital is 40 million RMB

Patented Technology from MIT

Unique, patented core technology

Uses guarded atomic transactions to implement a high-level parallel

programming language for mapping algorithms to optimized architectures.

About Hyper-Blue Co.,Ltd.

Office & Sales

Beijing; Shanghai; Taiwan; Singapore;

Europe; America

Select Customer Example (HyperSilicon Co.,Ltd.)

Product Over View

Build automation for easy bring-up and high-speed connectivity to test benches & models

Dynamically configurable hardware debug: 100% register state visibility & HW breakpoint

Clock speeds to 50 Mhz

2M-40M ASIC ASIC Gates

Ready-to-use VIP templates

Support Verilog RTL IP

Sēmu: The High-Speed of emulation, with the ease-of-use, debug visibility&price

point approaching simulation

Key Features:

Product Key Benefits

Cut Simulation Times by 1000x with FPGA Emulation

Problem: Long simulation runs required to validate today’s complex IP takes too long!

Examples: Video codecs; memory subsystems; wireless protocols; processors; packet

processors; memory controllers; cryptography; …

0 10 20 30 40 50 60

Hours

Compile time Simulation time

RTL Simulator: 10 minute compile + 56 hour simulation

RTL Emulator: 2 hour compile + 1 minute simulation

Product Key Benefits

easy-to-use emulation with Low Cost, Xilinx Development Boards

Verilog IP

High-speed

Co-emulation Link

Test Bench and/or Models

Initial setup in a day, not weeks/months:

• Specialized build automation

• Automatic C API co-emulation link creation for host-side test

benches

• VCD player example for validation tests

Debug iterations in minutes, not the hours required to

re-instrument and re-synthesize

• Complete register state visibility & HW breakpoints

• Emulation control GUI (run, run x cycles, stop, instrument)

Product Key Benefits

dynamic visibility & debug

Design Navigation: • Design hierarchy • Available signals

Signal Collection: • User collects useful signals • Dynamically selects signals:

- For vcd instrumentation - For display in waveform viewer

Complete register state visibility for

dynamic selection & rapid debug

Product Objectives

Objectives:

Break open the market with a desktop emulation product that pushes

the limits on ease- of-use and cost:

Test the hypothesis that there is an underserved market at the lower range of gate

capacity

Develop a shrink-wrap product that can eventually be taken to market with big

distribution channels

Create a lead generation vehicle to provide leads to direct sales for our

higher value products

Product Target Customers

Developers of complex IP blocks and subsystems up to 40M gates facing one or more of these problems:

Video codecs

Wireless protocols

Packet processors

Controllers

DMA

Graphics processors

Memory subsystems

Processors

Cryptographic engines

Individual Blocks and Subsystems

Simulators are way

too slow for

complete

verification

(regressions, corner

cases)

Emulators are too

expensive & too

slow

FPGA boards lack

control, visibility,

debug, and require

too many re-

compiles

Need connections to

host virtual

platforms

Target Application Description Target Users Why Semu?

Verification of Complex IP

Blocks & Subsystems for

ASICs & FPGAs

Software simulation is too slow to verify

adequately complex IP blocks &

subsystems (<=3.5M gates). Use Semu to:

Get through regressions quickly

Hit difficult-to-reach corner cases

Provide comprehensive verification

coverage

• Design engineer/teams

for FPGAs and ASICs

• Architect/modeler (who

prototypes with RTL)

• Verification

engineer/teams developing

synthesizable Verification

IP (VIP)

• Affordable

• Easy-to-use: build/C API co-

emulation/dynamic debug

• High-speeds with FPGA-based

emulation

vs. FPGA boards:

• FPGA boards too much

work/hassle to consider

vs. emulation solutions:

• Too costly & hard-to-use at unit

level

Hybrid Virtual Platforms Integrating Verilog IP into Virtual

Platforms for high-speed, more accurate

firmware development

• FPGA prototyping teams

• Virtual Platform teams

• Verification and design

teams within smaller

organizations

• Note: while firmware

developers are ultimate

“user”, someone else

develops

vs. FPGA boards:

• Deploy sooner (build/C API)

• Avoids infrastructure

development

• Dynamic debug visibility

diagnoses problems faster in

development and in field

vs. emulation solutions:

• Affordable deployment,

especially for firmware developers

Product Design Flow

Connect:

Build:

Go:

Install Xilinx FPGA board (2M-40M ASIC

Gates) into your Linux PC

Install Semu on your Linux PC

Integrate your Verilog RTL using Semu build

automation tools

Leverage one of our test bench templates

Run at speeds up to 50 Mhz

Debug with ease&100% register state visibility

for much faster iterations

Dynamically set a hardware breakpoint against

any register state

Product Design Flow

Product Design Flow

Typical Steps

user semu

Typically

once per

project

Once per

design or

TB

change

Verilog IP

Semu

Semu

Semu

Verilog IP

Product Design Flow

Typical Steps to bring up design on an FPGA(with C/C++ test bench

Step1:Copy Verilog IP for design onto Linux Host

Step2:In Semu: Configure Project(quick)

Step3:Semu reads top level I/O s

Step4: User characterizes I/O types with I/O GUI(quick)

Product Design Flow

Typical Steps to bring up design on an FPGA(with C/C++ test bench

Step5:Semu Generates C-API(quick)

Step6:User integrates/writes C test bench(or leverages

example) on Host(note: skip for manual stimulus)

Step7:In semu: Build project(quick)(e.g. for emulation)

Step8: semu runs Xilinx Synthesis and Place & Route

Product Design Flow

Typical Steps to bring up design on an FPGA(with C/C++ test bench

Step9:Semu Compiles test bench and builds co-emulation

Step10: In Semu: Run Project(quick)

Step11:Semu presents execution & debug control GUIs

Step12: In Semu: User runs/stops/instruments/opens waveform viewer(dynamically debugs)

Application

Verification of Complex IP Blocks &Subsystems for ASICs and FPGAs

Test bench RTL IP

Unit level verification at order-of-magnitude

faster speeds

Software simulation is too slow to verify adequately

complex IP blocks & subsystems (<=3.5M gates):

Get through regressions quickly

Hit difficult-to-reach corner cases

Provide comprehensive verification coverage

Emulation & FPGA prototyping are too hard-to-use &

expensive

Vs FPGA board : Raw FPGA boards are too hard to

use(bring up/connect/debug/…)

Vs emulation : individual engineers don’t get time on

emulators

Rich Roadmap of features & capacities

Q4 2015 Q1 2016 Q2 2016 Q3 2016 Future

Capacity

Features

20M+

20M

15M

10M

5M sēmu pe up to 2M gates ML605, KC705

sēmu se up to 3.5M gates VC707

sēmu xe up to 14M gates TBD

sēmu TBD

Standard: Build automation

C API

Dynamic visibility

Single breakpoint

Examples: VCD/…

MathWorks (Option) Matlab/Simulink I/F

Dynamic Debug (Option) Hardware breakpoints and

additional dynamically

configurable debug capabilities

AMBA transactors

(Option)

C Testbench

Libraries

(Option)