Генератор, Dikpost

285 \ 2750 / . 24 . 8 120 . . , , . ( ). , , . , , , . , , ( B = LI ). , . . , 90 . 2 U2 U3. U1 50 * 48 = 2400 . , . P0.7 P2.7 CPU. 360 / 48 = 7.5 , 24 . U8C U8D 40 , U7A U7B 1, . R3 R7 U9A U9B. 2 1V . R4 R5. C6R8 C7R9 , . , , 0. , ( ) . SW1 SW2 \ . . . 2 0.4 0.5 . 36 , . D14 D19 DC-DC U10 U12, . 3.75 , . U5 Vref , . R6. . . , , , , . . , \ . .

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

7.5 15 22.5 30 37.5 45 52.5 60 67.5 75 82.5 90 97.5 105 112.5 120 127.5 135 142.5 150 157.5 165 172.5 180 187.5 195 202.5 210 217.5 225 232.5 240 247.5 255 262.5 270 277.5 285 292.5 300 307.5 315 322.5 330 337.5 345 352.5 360

Sin 0.1305 0.2588 0.3827 0.5 0.6088 0.7071 0.7934 0.8660 0.9239 0.9659 0.9914 1.0 0.9914 0.9659 0.9239 0.8660 0.7934 0.7071 0.6088 0.5 0.3827 0.2588 0.1305 0.0 -0.1305 -0.2588 -0.3827 -0.5 -0.6088 -0.7071 -0.7934 -0.8660 -0.9239 -0.9659 -0.9914 -1.0 -0.9914 -0.9659 -0.9239 -0.8660 -0.7934 -0.7071 -0.6088 -0.5 -0.3827 -0.2588 -0.1305 0.0

Cos 0.9914 0.9659 0.9239 0.8660 0.7934 0.7071 0.6088 0.5 0.3827 0.2588 0.1305 0 -0.1305 -0.2588 -0.3827 -0.5 -0.6088 -0.7071 -0.7934 -0.8660 -0.9239 -0.9659 -0.9914 -1.0 -0.9914 -0.9659 -0.9239 -0.8660 -0.7934 -0.7071 -0.6088 -0.5 -0.3827 -0.2588 -0.1305 0.0 0.1305 0.2588 0.3827 0.5 0.6088 0.7071 0.7934 0.8660 0.9239 0.9659 0.9914 1.0

1 11h 21h 31h 3Fh 4Dh 5Ah 65h 6Eh 75h 7Bh 7Eh 7Fh 7Eh 7Bh 75h 6Eh 65h 5Ah 4Dh 3Fh 31h 21h 11h 0h 91h A1h B1h BFh CDh DAh E5h Eeh F5h FBh Feh FFh FEh FBh F5h EEh E5h DAh CDh BFh B1h A1h 91h 80h

1 16.6 32.9 48.6 63.5 77.3 89.8 100.8 110 117.3 122.7 125.9 127 125.9 122.7 117.3 110 100.8 89.8 77.3 63.5 48.6 32.9 16.6 0 1 + 16.6 1 + 32.9 1 + 48.6 1 + 63.5 1 + 77.3 1 + 89.8 1 + 100.8 1 + 110 1 + 117.3 1 + 122.7 1 + 125.9 1 + 127 1 + 125.9 1 + 122.7 1 + 117.3 1 + 110 1 + 100.8 1 + 89.8 1 + 77.3 1 + 63.5 1 + 48.6 1 + 32.9 1 + 16.6 1+0

2 2 7Eh 7Bh 75h 6Eh 65h 5Ah 4Dh 3Fh 31h 21h 11h 0h 91h A1h B1h BFh CDh DAh E5h EEh F5h FBh FEh FFh Feh FBh F5h Eeh E5h Dah CDh BFh B1h A1h 91h 80h 11h 21h 31h 3Fh 4Dh 5Ah 65h 6Eh 75h 7Bh 7Eh 7Fh 125.9 122.7 117.3 110 100.8 89.8 77.3 63.5 48.6 32.9 16.6 0 1 + 16.6 1 + 32.9 1 + 48.6 1 + 63.5 1 + 77.3 1 + 89.8 1 + 100.8 1 + 110 1 + 117.3 1 + 122.7 1 + 125.9 1 + 127 1 + 125.9 1 + 122.7 1 + 117.3 1 + 110 1 + 100.8 1 + 89.8 1 + 77.3 1 + 63.5 1 + 48.6 1 + 32.9 1 + 16.6 1+0 16.6 32.9 48.6 63.5 77.3 89.8 100.8 110 117.3 122.7 125.9 127


5

4

3

2

1

R13 6 .2k U8C

25 - 40 U8D

4

9 8 1074HC00D

12 11 1374HC00 C10

+5v

U7A

+ 5 v +36v

D3 - D10 50V 2AC5 C9

PRE

2 3R10 4.7k

D

Q

5 6

C4

0100n 100n

0100uF/50V

0D

CLK Q 1

CLR

9

4

2

2

2 1

74HC74 U8A

1

1

10

0+ 12v

5 3 7 6 10 6 12 11

U7B

1 2 974HC00

A Q1 B Q2 INH1 Q3 C D GND INH2 S1 S2 Q4

2JP1

PRE

3 13 14 2 2 2 2 8

1

2.2n

Vdd

Vcc

2

U6

12+ 36v + 12v -12v +5v

D

Q

CLK Q 13

CLR

11JP2

8U8B

1 2 3 4

1 2 3 4 5 6 7

74HC74

4 5

JP1 1 - 2 3 - 4 B

3

U9A

1

1

1

1+5v LM339

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L298N

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C6 470p

5 4

2

0LM339 R4 1k + 12v

R7 0.5R

0R5 1k

0+12v R25 10k R1 10k U5 A4N32 R6 50k/5W

R26 10kB

14

Vss

-12v

Vref Rfb Iout1

16 11 2 3 1 1D1

2

1MC34084

Iout1 GND Iout2

2

GND

Iout2

4

U4A

1

+ 12v

522

0

5721

R14 +5v

10k

0

10 11 12 13 14 15 16 17 30 29

P3.0/RXD P1.0/T2 P3.1/TXD P1.1/T2-EX P3.2/INT0 P1.2 P3.3/INT1 P1.3 P3.4/T0 P1.4 P3.5/T1 P1.5 P3.6/WR P1.6 P3.7/RD P1.7 ALE/PROG PSEN XTAL1 XTAL2 EA/VPP RST

1 2 3 4 5 6 7 8 19 18 31 9

3

3

5721

0

522

0X1 11.0592

SW1A

SW2

R15 10k C11 100n C12 100n U1

R12 10k

C1 22p

C2 22p

0C8

0

" " 05

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CPU Reset10uF

+5V

4

3


+

2

2

D2

5

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I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

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21 22 23 24 25 26 27 28

P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15

P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7

39 38 37 36 35 34 33 32

I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

Vss

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13 12 11 10 9 8 7 6 5 4

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16MC34084

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A

Title

GEN Document Number

Size B D ate:2

1

R ev 01 Sheet1

Saturday, June 12, 2004

1

of

1

5

4

3

2

1

0

02 1

0

1N5819D

1

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U10

1N5819

U11

D12

D

8R16 0.33R

DC PK VCC COMP

SWC SWE TCAP GND

1 2

D11

8 2R19 0.5R

DC PK VCC COMP

SWC SWE TCAP GND

1 2 2 3C17 R22 0.5R L2 100uH 470p

8 7 6 5

DC PK VCC COMP

SWC SWE TCAP GND

1 2 3 4C19 470p D13 1N5819

7 6

7 6 5

1 2

C14 470p

3 4L1 220uH

1

2

100n C13

5

4

C16 100n MC33063

0

+5V C15

2

MC33063

0

+12V 1 100uF/16V C18

MC33063 -12V R23 8.2k 910 R24 100uF/16VC

0C

R17 1.2k

3.6k R18

0

R20 910

8.2k R21

C20

100uF/10V

0

0

0

0

0

1

0

2

2

1

1

B

1 2 3 . JP5 3300uF/50V C21

1

JP4

D14

D17

2

+36V D18B

JP3

1 2 2 2~ 36V

1 2 3 4 5 6 7

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D15

D16

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1

1

1

A

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A

R ev 01 Sheet 11

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C GENN.ASM

;***************************************************************** ;* PWM based sinewave generator, table based ;************************************************************************** .include "8535def.inc" ; Registers definitions ; .def tmp = r16 .def sin_angle = r17 .def cos_angle = r18 .def amp = r19 .def itmph = r20 .def itmp = r21 .def adclb = r22 .def adchb = r23

; (0- 255) ; ; ( 0 -255 )

;************************************************************************** ; Reset and interrupt vectors handlers ; .cseg .org $00 reset_hnd: rjmp start ; .org OVF1addr tim1_hnd: rjmp tim1_ovf .org ADCCaddr rjmp ADC_intr ;.org ADCIaddr ; rjmp ana_comp ;Analog Comparator Handle ;************************** mul******************************************** multb: ; , push amp mula_0: clr itmph ldi itmp,8 lsr amp ;clear result High byte ;init loop counter ;rotate multiplier

mula_1: brcc mula_2 ;carry set add itmph,r0 ; add multiplicand to result High byte mula_2: ror itmph ;rotate right result High byte ror amp ;rotate right result L byte and multiplier dec itmp ;decrement loop counter brne mula_1 ;if not done, loop more pop amp ret ;************************************************************************** ; Timer 1 interrupt handler ; tim1_ovf: push amp ; 1 sbi PORTD, PD2

inc sin_angle inc cos_angle ldi ZL,low(sine_tbl*2) ldi ZH,high(sine_tbl*2) add ZL,sin_angle clr tmp adc ZH, tmp lpm lsl r0 brcc set_ph1 brcs clr_ph1 next1:

;

;

;

rcall multb out OCR1AH, tmp out OCR1AL,itmph ldi ldi add adc lpm lsl ZL,low(sine_tbl*2) ZH,high(sine_tbl*2) ZL,cos_angle ZH, tmp

; ; ;

r0 brcc set_ph2 brcs clr_ph2 out OCR1BH, tmp next2: rcall multb out OCR1BL, itmph rjmp return set_ph1: sbi PORTD,PD0 rjmp next1 clr_ph1: cbi PORTD,PD0 rjmp next1 set_ph2: sbi PORTD,PD1 rjmp next2 clr_ph2: cbi PORTD,PD1 rjmp next2 return: cbi PORTD,PD2 pop amp sbi ADCSR, ADSC reti

; U4 ;

;*************** ***************************** ADC_intr: AD0_1: sbic ADCSR,ADSC ; rjmp AD0_1 in adclb,ADCL lsr adclb ; 10- 8- lsr adclb in adchb,ADCH lsl adchb lsl adchb lsl adchb lsl adchb lsl adchb lsl adchb or adchb,adclb mov amp,adchb ; amp reti ;ana_comp: ; dec amp ;reti ;************************************************************************** ; Reset handler. Initalizes port and Timer 1, and stay in a endless loop ; start: sbi DDRD, PD4 sbi DDRD, PD5 ; Set pin PD4 PD5 as output (is OC1A OC1B pin) sbi DDRD, PD0 sbi DDRD, PD1 ; Set pin PD0 PD1 as output (is ph1 ph2 ) sbi DDRD, PD2 ; Set pin PD2 as output (is trigger clock ) ldi out ldi out tmp,low(RAMEND) SPL,tmp tmp,high(RAMEND) SPH, tmp ; Init Stack pointer

ldi tmp,(1

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Генератор, Dikpost