정 용 군 ( 전자공학과 대학원 )jdragon@trut.chungbuk.ac.kr

대상 : VLSI 설계 연구회 1,2,3

학년

기간 : 99.1.11 ~ 99.1.13

Synopsys Tool 교육

Synopsys 교육 1

Synopsys 교육 1

Design AnalyzerHDL Compiler Family

HDL Synthesis

HDL Compiler TM VHDL Compiler TM

(verilog)

Design Compiler FamilyCircuit optimization

Design Compiler TM FPGA Compiler TM

(CMOS)

Test Compiler Family

Test Compiler TM Test Compiler Plus TM

VHDLSystem

Simulation

SGE

VHDL

NetlistSchematicsState tables

TestVector

TechnologyLibrary

LibraryCompiler

NetlistSchematicsState tables

Goals

Verilog

DesignWareDevelop

Synopsys 의 구조

Synopsys 교육 1

Synopsys 환경 설정

- 자신의 .cshrc 파일에 다음을 추가한다 .(donald 기준 )

################# setup for synopsys #################### setenv SYNOPSYS /tools/synopsys set path = ( $path $SYNOPSYS/sparcOS5/syn/bin ) set path = ( $path $SYNOPSYS/sparcOS5/sim/bin ) set path = ( $path $SYNOPSYS/sparcOS5/sge/bin ) set path = ( $path $SYNOPSYS/iview2/bin ) set path = ( $path /opt/SUNWspro/bin ) source $SYNOPSYS/admin/install/sim/environ.csh ######################################################

Synopsys 교육 1

VHDL System Simulator

Synthesis with VHDL

sge : Simulation Graphical Environment vhdlan : VHDL analyzergvan : Graphical VHDL analyzervhdlsim : VHDL simulatorvhdldbx : VHDL debugger

=> Design Analyzer

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VHDL System Simulator

1. SGE 시작Ex : [donald:home/grad/dragon]sge &

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2. Drawing circuits (Schematic editor)

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2.1. Drawing circuits (Schematic editor) (cont.) : Add / Symbol command

Select components to place

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2.2. Drawing circuits (Schematic editor) (cont.) : Add / Wire command

Draw the line to input/output port of symbols

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2.3. Drawing circuits (Schematic editor) (cont.) : Add / Netname command => determine netname

enter net name

* If net is BUS, enter the net name ; A(3:0), B(4:0) etc.

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2.4. Drawing circuits (Schematic editor) (cont.) : Add / I/O Marker command => determine input/output

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2.5. Drawing circuits (Schematic editor) (cont.) : File / Save command => .sch, ._sc

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3. Compile circuits (Schematic editor) : Netlist => VHDL code

3.1. Creating a symbol

If select this block,display information of

designed circuits

automatically generated by Schematic editor

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3.1.1. Creating a symbol (cont.)=> To simulate and synthesis after transforming netlist to VHDL code

=> To edit symbol by designer

=> Must create a symbol for each schematic : .sym

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3.1.2. Creating a symbol (cont.)

Draw / Rect=> draw box

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3.1.3. Creating a symbol (cont.)

Draw / Line=> draw line Add / Pin

=> determine in/out port

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3.1.4. Creating a symbol (cont.)

Add / Pin Attr=> determine pin name and polarity

BUS => A(3:0), B(5:0)

pin name

change polarity

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3.1.5. Creating a symbol (cont.)

determine position of pin name

Add / Pin Name Loc

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3.1.6. Creating a symbol (cont.)

Add / Window

Using the symbol created ,is placed with this shape

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3.1.7. Creating a symbol (cont.)

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3.2. Generate VHDL code

vi editor

Netlist => VHDL code

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4. Simulation

=> It is the most useful method using test bench.

4.1 Test Bench Generation

1) automatic generation by SGE

2) code test bench for yourself

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4.1.1 Automatic generation by SGE

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4.1.1 Automatic generation by SGE (cont.)

: Tools / Code VHDL Models => tb_(circuit-name).vhd

generate test bench

Test bench is automatically generated,but insert input signal to test bench with using editor program(vi)

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4.1.1 Automatic generation by SGE (cont.)

: Tools / Analyze VHDL Models => compile test bench

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4.1.1 Automatic generation by SGE (cont.)

: Tools / Start VHDL Simulator => compile test bench

VHDL debugger(vhdldbx)

WAVE

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4.1.2 Coding test bench for yourself

Designed circuit

test bench

input signal output signal

structual description

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Example of input signals for test bench

clock of 250 ns period

reset signal

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4.2 Simulation

vhdlan vhdldbx wavevhdl sourcetest bench

error

error

OK

< Flow >

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4.2.1 vhdlan (shell mode)

usage : vhdlan [option] (vhdl source, test bench)

[option] -l : read vhdl file and generate *.lis file having error message -c : generate object code compiled -v : display information of analyzer

Ex : vhdlan -l -c test.vhd

cf) graphic mode : gvan

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4.2.2 vhdldbx ( ex : [donald:home/grad/dragon/WORK]vhdldbx & )

select configuration

1. include *.log2. run 25000

edit *.log file : have information in/out port being displayed in wave window

ex) vi test.log trace clk trace a[0] . .

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4.2.3 wave ( ex : [donald:home/grad/dragon/WORK]waves & )

waveform file*.ow

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4.2.3 wave ( ex : [donald:home/grad/dragon/WORK]waves & ) (cont.)

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Synthesis with VHDL

Design Compiler

Design

OperatingEnvironmentDescription

Timing,Area andDesign RuleGoals

Optimized design

Reports

Schematics

Inputs and Outputs of Design Compiler`

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Menu

command line

Design Compiler

design_analyzer(graphical mode)dc_shell

(shell mode)

Design Compiler Interaction

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Design analyzer 실행

Ex : [donald:home/grad/dragon]design_analyzer &

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File / Read command => To read designs into Design Compiler

Read formats; DB EDIF Equation LSI Mentor PLA State table Tegas Verilog VHDL

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File / Analyze command => syntax checks VHDL code, .syn and .mra file 생성

vhdl source file

find file to analyze

Library is the name ofworking directory.

determine formatto analyze

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File / Elaborate command => elaborate after analyze to bring design into Design Compiler memory

select working directoryname

automatically re-analyzes out of date intermediate files if source can be found

* If you change VHDL code,analyze and elaborate again

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Analysis / Link Design command => To ensure all sub-elements of your hierarchical designs are available.

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Analysis / Check Design command => execute check design before you optimize your design

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Attributes / Clock command

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Design Optimization

1. Constraints

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2. Design optimization => type of CLB and IOB of Xilinx

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FPGA