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경종민 kyung@ee.kaist.ac.kr

Packaging and Interconnection

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References• H.B.Bakoglu, ‘Circuits, Interconnections, and Packagin

g for VLSI’, Addison-Wesley, 1990

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Packaging

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1. Overview• Agony of interconnection :

– Device becomes smaller, faster while chip size and routing length becomes bigger.

– IR voltage drop, delay, power dissipation due to interconnects, and max. current density, noise coupling/crosstalk are serious problems in future VLSI and now.

• Typical distribution of interconnection lines.

Clock, bus

5• Multi-level interconnection

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2. Packaging• Package Types : 2-side : DIP(Dual In-Line) : thru-hole

4-side : QFP(Quad Flat Package) : SMT (Surface

Mount Tech.)

area type : PGA(Pin Grid Array) : thru-hole

BGA(Ball Grid Array)

• Chip to package bonding : wire bonding

TAB (Tape Automated Bonding)

Flip-chip bonding

7• MCN(Multi-Chip Module)

Level 0 Level 1 Level 2 Level 3

Level 15

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• MCM 제품의 형태 및 비표– MCM-L(Laminated) :

극세선 다층구조 PCB 기판 , 저가 , 중성능 , Cache 메모리

모듈 등 다양한 용도

– MCM-C(Ceramic) :

하이브리드 기술 , 대형 컴퓨터 , 군사 / 항공용 특수용도

– MCM-D(Deposited) :

반도체 칩 공정으로부터 파생 , 구리 / 폴리이미드 다층구조 ,

컴퓨터 , 정보통신 , Workstation, PC, 이동전화기 등

광범위한 용도

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• MCM 요소 기술– MCM 설계 기술 :

기판재료 , 절연체 재료 , 접착재료 , PCB 재료 등 재료설계 (

재료 , 화공 ), 전기적 회로 설계 ( 전자 ), 열적 냉각 설계 ( 기계 )

– MCM 단위공정 기술

coating, etching, metallization, lithography 등

– 안정된 베어 (bare) 칩 세트 확보

– Known Good Die(KGD) 문제 : MCM Yield

– MCM 테스트 기술

– Inter-disciplinary collaboration

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• MCM 시장 및 기술 예측 (1997 년도 예상 )– 1998 년 MCM 시장 : $1.6 billion

– MCM 시장의 큰 driver :

데이터 처리 , 정보 통신 (B-ISDN) (HDTV, CATV, ATM 등 )

내장형 콘트롤러 (DSP, GPS, RISC 등 ), Workstation/PC,

이동전화기

– 저가의 MCM-L 시장

기존 PCB 와 경쟁

– 고가의 MCM-D 시장 : > 100MHz

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Multi-Chip Module Technique 구조 :

i) IC 칩 : 한 개 이상의 칩 실장ii) Substrate : ( 열팽창계수 (TCE), 유전상수 , 열 전도율 , 비용 )

• type MCM-L : FR-4, Polyimide Glass, MCM-D : Si, SiC, SiN, SiO2 MCM-C : Alumina, Hybrid MCM

• Routing : 배선층 , I/O 배정 , 칩 배치 , 고밀도 배선 (via 사용 )• 배선구조 : 도체 - 절연체

기판 - 배선 (Cr/Cu-Polymer-Cu-Polymer-Cu/Au)-chip

공정 :i) 칩 bonding(die bonding)ii) 칩과 기판 연결 : wire bonding, TAB, flip chip

전기적 시험

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MCM Package StructuresTechnology Thin Film Thick Film PCB

(type) (MCM-D) (MCM-C) (MCM-L)

A. Dielectric Polyimide/SiO2 Alumina Epoxy-Glass

Glass+Ceramic Polyimide-glass

Dielectric Constant Er 3.2/3.8 9-10/4-8 4.7/2.5

Resistivity(-cm) 1016/1014 1014/1014 1014/1014

Thickness(m) < 20 100 and up 100 and upB. Conductors Cu-Al W, Mo, Cu, Au Cu, Au

Sheet resistance(m/sq) 3-4.2 2-15 3Thickness(m) 10 20-30 18-35Line width(m) 25 100 and up 70 and upVia hole size(m) 40 100 and up 50 and upMin Via Grid(m) 100 250 and up 250 and upNo. of Layers 1-6 30 and up 50

C. Dielectric and Via Coat/Deposit+Litho Tape/Punch Punch/DrillingD. Conductor Sputter Screen Laminate/Deposi

t electroplate,Photolitho

E. Firing/Curing/Arm 400 C(Oxidizing) 900C(N2) < 100C

G. I/O Connection Solder Bond Solder/Braze Solder/Braze

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• MCM design flow– Chip placement– wiring design

i) # of I/O ports, module area, wire length/layer, via– Chip placement– Electrical considerations

• Electrical Design Considerationsa) Key design factors :

1. Physical dimension(space)2. Electrical consideration3. Thermal consideration

b)Information transfer process :1. Change in the signal level2. Signal transition time

c)Electrical parameters : RequirementsR- Voltage drops Faster switching speedsC- RC delays Reducing input capacitanceL- delay noise Optimizing the driving

impedance

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• Module Package - MCM-C Package

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• MCM-C Cross-section

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Interconnection Modelling as a Transmission Line

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Interconnection Modelling :• Modelling of interconnection line as

i) lumped C model : treated as lumped capacitive loads

ii) lumped RC mode : first-order consideration of R when R is significant

iii) distributed RC model : better consideration of R’s (intra-chip wire)

iv) transmission line model : if the interconnection wire is sufficiently long or circuits very fast s.t. signal rise time is comparable to the time of flight across the line, i.e, L is not negligible.(PCB wire)v) lossy transmission line model : (MCB substrate wire)

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Interconnection wire 의 전송선 modelling l : wire length : signal 의 wavelength

t=l/v : time of flight

t=/v : signal 의 rise time1. t << Tr (i.e., l << ) 인 경우 :

wire 는 lumped capacitance 로 model 가능2. 그렇지 않은 경우 :

1) lossless 일 때 (R 성분이 L 성분에 비해 작을 때 ) : transmission line 으로 model2) lossy 인 경우 :

R 성분이 L 성분보다 크므로 Transmission line 효과 보다는 RC distributed 회로로 model 가능 . 즉 , wire R >> Zo(

특성저항 ) 인 경우

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Observations1. High-speed chip 의 detailed modelling 을 위해서는

pin, lead frame, bonding wire 등을 전송선으로 보고 2-D 해석을 해야 함 .

2. 대략의 chip-to-chip delay 계산을 위해서는 board wiring 은 전송선으로 , pin, lead frame 등은 lumped C or L load 로 model 하면 충분 .

3. * Power ground line 은 Signal line 과 달리 C 는 키우고 L 은 줄이는 것이 좋다 . ( 스위칭 noise)L

di

dt

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Transmission line model

• Lossless transmission line

– Inductance of a device = Magnetic flux

Electric current carried

LI

L'I

'

(L’ and ’ are inductance, and magnetic flux per line length.)

(IL) IL' X

Vt

IL'x

tIL'AD

( )1

A B

D C

I

I

V

X

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Similarly for C = Q

V Q CV VC X ( ) '

IQ

t

CV

tV C

x

tV CAD AD

( )' ' ( ) 2

From( )& ( ),1 2 V L'C VL'CAD AD '

' 2 1

V

I

L'

C

L

CAD

'Zo(char imp) =

1 C

Co

r ro o o( )

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• Reflected waveforms for inductive & capacitive discontinuity (time constant ; L/2Z, ZC/2)

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• Magnitudes of Reflected & Transmitted components of voltage(current) wave at the transmission line discontinuity.

Vi

Vr Vt Z2Z1 Vi Vr Vt

Ii Ir It

V V Vt i r ( ),1 I I It i r ( )2V Z I

V Z I

V Z I

t t

r r

i i

2

1

1Define (reflection coeff.)=

and T(transmission coeff.)=

V

Vr

i V

Vt

i

Then, from(1), T = 1+ and from(2), 1 1

1 12 1 1

1 2

Z Z ZZ Z( ) ( )

Z Z

Z ZT

Z

Z Z2 1

2 1

2

2 1

12

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• Reflected waveforms at the unterminated transmission line ;

V-source 에 의한 VG 에 대한 영향R-divider 로 볼 때는 V=VS 로 , X-mission line 으로 볼 때는 V=VS /2 로놓는다 .

Z R

Z RS

S

9

11RS=0.1 Z 일때 : s

SG V

VVT

t 11

10

11

20

211

200

RS=10 Z 일때 : 9

11 11

2T

11

1)1(

)1(1()1(

)1()1()1( 322

S

S

SS

V=VS /2

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• When Rs=10Z, Rs=Z, and Rs=0.1Z, respectively(not in the same scale)

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• Waveforms for finite rise-time signal

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34• Waveform propagating along lossy transmission line.

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36• Transmission line 의 termination :

i) RS=0, RL=(no termination) (dotted line : RS=0.1 Zo

일때 )

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ii) Term. at receiving end (RS=0, RL=Zo)

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iii) Source-end termination

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v) RC-termination at receiving end : RS=0, RL=Zo(C

L>> )t

Zf

o

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iv) 기타

43• Driver and termination circuits for tr. lines.i) term. at receiver end

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46ii) term. at the source end(series termination)

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What limits bandwidth?• Circuit speed• Impedance discontinuity

– Pad capacitance– Bonding wire– Package trace– PCB trace

• PLL & DLL jitter in the receiver• Wire limits

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Copper vs Fiber• Copper:

– Coaxial Cable, Twin-axial Cable, UTP (unshielded Twisted Pair), STP (Shielded Twisted Pair), etc.

– High bandwidth over short distance– Low cost– EMI, ground isolation, interference problem

• Fiber: – Multi-mode fiber (Step-index, Graded-index), Single-mode fiber– Light sources: Laser diode or LED– Material: Silica or plastic– High bandwidth over long distance– High cost– No interference, no crosstalk, no EMI– Interface with electrical signals through a limiting amplifier (TX)

and a trans-resistance amplifier (RX)

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Basic Electrical Problem over Wire

• Transmitter – convert bits to an analog voltage

• Channel (Wire) – propagate the voltage/current

• Receiver – convert the analog voltage to bits

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Signal Reflection & Wave Diagram

VS

RS

RL

Z0

V1+

V1-

V2+

V2

-

V1

+

V1+ = VS

Z

0RS + Z0 V1- = V1

+

RL - Z0

RL +

Z0

V2- = V1

-

RS - Z0

RS + Z0

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Unterminated Linetd

P

at P

0 td/2 3td/2

VS

VS

ZO

td

2td

VS

5td/2

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Parallel Termination

RL = ZO

td

td

2td

VS

P

at P0 td/2 3td/2

VS

VS

ZO

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Series Termination

openRS= ZO

td

td

2td

VS/2

VS

P

at P0 td/2 3td/2

VS/2 VS

VS

ZO

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Conclusion• Signal reflection at discontinuity points• Signal rise time must be longer than travel time for ju

stifying lumped element analysis, otherwise transmission line modelling is necessary.