计算机组成与结构 Lecture 6 - Logic & Arithmetic Reading: 3.1-3.3, B.5, B.6 ORACLE Arithmetic Unit Image Source: Oak Ridge National Laboratory 本课件内容源于美国 Lafayette

计算机组成与结构

Lecture 6 - Logic & Arithmetic

Reading: 3.1-3.3, B.5, B.6

ORACLE Arithmetic UnitImage Source: Oak Ridge National Laboratory

本课件内容源于美国 Lafayette 大学 John Nestor 教授的课件

ECE 313 Fall 2006 Lecture 6 - Logic & Arithmetic2/43

Roadmap for the Term: Major Topics

Computer Systems Overview Technology Trends Instruction Sets (and Software) Logic and Arithmetic Performance Processor Implementation Memory Systems Input/Output


Outline - Logic & Arithmetic

Review: Numbers & Arithmetic Positional Number Systems Signed Number Representation

Review: Addition & Subtraction Carry Lookahead: Making Addition Fast ALU Design Shifters Summary


Review: Positional Notation of Numbers( 数的位置计数法 )

Example: Binary (base 10) numbers Base = 2 Digits = {0,1} Note “bit” == “Binary digit” N = 1001two = X + X + X + X = 1ten + 8ten = 9ten

Example: Hexadecimal (base 16) numbers Base = 16 Digits = {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F} N = 1A3Fhex = X + X + X + X

= 15ten + 48ten + 2560ten + 4096ten = 6719ten

= 0001101000111111two


Range of Unsigned Binary Numbers

Number of Digits Smallest Value Largest Value

n 0 2n-1

8 0 28-1 = 255

16 0 216-1 = 65,535

32 0 232-1 =4,294,967,295

64 0 264-1 =1.8446 X 1019


Review: Unsigned vs. Signed Numbers

Basic binary - allows representation of non-negative numbers only

In C, Java, etc: unsigned int x;Useful for unsigned quantities like addresses

Most of us need negative numbers, too!In C, Java, etc: int x;

How can we do this? … Use a signed representation


Sign/Magnitude Representation

Approach: Use binary number and added sign bit

Problems: Two values of zero Difficult to implement in hardware - consider addition

• Must first check signs of operands

• Then compute value

• Then compute sign of result

1Sign

0 0 1 1 0 0 1Magnitude

= -25


Two’s Complement Representation2的补码表示 Goal: make the hardware easy to design Approach: explicitly represent result of “borrow” in

subtract 最左边符号位的权重为 -2n-1

使用符号位为表示最后的借位N = 1111tc = X + X + X + X- = 7ten + -8ten = -1ten

N = 1001tc = X + X + X + X- = 1ten + -8ten = -7ten

N = 0101tc = X + X + X + X- = 1ten + 4ten = 5ten

所有的负数在符号位上都是 1 0 只有一种表示方法


Range of Two’s Complement Numbers

Number of Digits Most NegativeValue

Most PositiveValue

n -2n-1 +2n-1-1

8 -27 = -128 +27-1 = +127

16 -215 = -32,768 +215-1 = +32,767

32 -231 =-2,147,483,648

+231-1 =+2,147,483,647

64 -263 =-9.22 X 1018

+263-1 =+9.22 X 1018


Sign Extension 符号扩展

如何把一个符号数放入一个能够表示更大范围数的空间中？把符号数的数值位 copy 到该范围的低位将符号位 copy 到该范围内所有剩余的位中

Example: Converting signed 8-bit byte to 32-bit word:

11111010 Orignal byte: -6

00101011 Orignal byte: 45

00101011 Result word: 45000000000000000000000000

Result word: -611111010111111111111111111111111


填充 0 - for unsigned numbers

To convert a “narrower” unsigned number to a “wider” one Copy the bits of the narrower number into the lower bits Copy “zeros” into upper bits of wider number


11000001 Result word: 193


00101011 Result word: 45000000000000000000000000

zeros

000000000000000000000000

zeros


Sign Extension in MIPS

Load-byte (lb) instruction Loads an 8-bit signed number from memory Performs sign extension before placing in 32-bit register

Load-byte unsigned (lbu) Loads an 8-bit unsigned number (e.g., ASCII character)

from memory No sign extension - places byte with leading “0’s” in 32-bit

register


Sign Extension in MIPS I-Format Instructions

I 型指令包括一个 16 位的立即数域 immediate field MIPS operations are defined on 32-bit registers 符号扩展是在立即数（立即数有意义时）上进行操作

Sign extension used for addi, beq, bne, ... Zero-padding used for andi, ori, ...


有符号和无符号数的比较指令

MIPS provides two versions of “set less than-slt” slt - signed comparison - useful when comparing signed

numbers sltu - unsigned comparison - useful when comparing

unsigned numbers (e.g. addresses)

Example: suppose $s0=1111 1111 1111 1111 1111 1111 1111 1111$s1=0000 0000 0000 0000 0000 0000 0000 0001

what do the following instructions do?sltu $t0, $s0, $s1

slt $t1, $s0, $s1

231-1 > 1, so $t0 = 0

-1 < 1, so $t1 = 1


大纲 - Logic & Arithmetic 算术和逻辑运算




Review: Binary Addition 二进制加法

关键组成模块 : Full Adder- 全加器

Ai Bi

Si

CiCi+1

Ai Bi Ci Si Ci+1

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1 Bi

Ai

Bi

Ai

Ci Ci+1

Bi

Ai

CiSi


Multiple-Bit Adders 多位加法器

String together Full Adders to form a Ripple Adder：把全加器连贯起来形成逐位 /行波进位加法器

A1 B1

S1

C1C2

A2 B2

S2

C2C3

A3 B3

S3

C3C4

A0 B0

S0

C0C1 0


A0 B0

S0

C0C1

A1 B1

S1

C1C2

A2 B2

S2

C2C3

A3 B3

S3

C3C4

How to Subtract with an Adder

回忆 Definition of subtraction: A-B = A + (-B) Two’s Complement Negation Shortcut

• -B = bit_invert(B)+1

1


Designing an Adder/Subtractor

Recall Definition of subtraction: A-B = A + (-B) Two’s Complement Negation Shortcut

• -B = bit_invert(B)+1

A0 B0

S0

C0C1

A1 B1

S1

C1C2

A2 B2

S2

C2C3

A3 B3

S3

C3C4

ControlAdd/Sub

0 to add

1 to subtract


Overflow in addition & subtraction

Overflow – 当没有足够的空间爱你表示结果时 Example: unsigned 32-bit result ≥ 232

Example: signed 32-bit result < -231 or ≥ 231

Detecting overflow – 在操作数和结果中查找不同的标记：

Operation Operand A Operand B Result

A + B ≥ 0 ≥ 0 < 0

A + B < 0 < 0 ≥ 0A - B ≥ 0 < 0 < 0

A - B < 0 ≥ 0 ≥ 0


What to do when overflow occurs?

In some languages (e.g., C, Java) - nothing (“responsibility left to the programmer”)

In other languages (e.g. Ada, Fortran) - “notify programmer” through runtime exception

How MIPS handles overflow: add, sub, addi - runtime exception on overflow addu, subu, addiu - no runtime exception on overflow




Review: Addition & Subtraction Carry Lookahead( 超前进位 ): Making Addition Fast

ALU Design Shifters Summary


Delay in Adders 加法器中的延时

Review: full adder equations Sum: si = ai XOR bi XOR ci

Carry: ci+1 = ai*bi + ai*ci + bi*ci

Delay estimate: 32-bit ripple add 32 位的逐位加法器 Worst case: A0 or B0 to C32 (or S31)

Carry delay - each stage: 2 gate delays Total delay: 64 gate delays - too high!

A0 B0

S0

C0C1

A1 B1

S1

C1C2

A2 B2

S2

C2C3

A3 B3

S3

C3C4 0


Speeding up Carry - Carry Lookahead

Key idea: trade off delay, amount of logic used- 在延时和所使用的逻辑门数量之间进行折中 Benefit: Faster addition Cost: much more logic

Define two signals for each adder stage: Generate- 生成 gi = ai*bi

Propagate- 传播 pi = ai + bi

Why use these names? Adder i will always generate a carry if ai, bi both true

Adder i will propagate a carry input if either or both ai, bi true

A0 B0

S0

C0C1

1 1

X1

1 0

11


Carry Lookahead (cont’d)

Now rewrite carry output as function of ai,bi,pi,gi

Original eqn: ci+1 = ai*bi + ai*ci + bi*ci

New eqn: ci+1 = gi + pi*ci

根据 gi, 和 pi ，进位函数更加“扁平” gi和 pi 形成后只需要 2.5 个门延时即可生成全部进位

c1 = g0 + p0*c0

c2 = g1 + p1*c1

= g1 + p1*(g0 + p0*g0 ) = g1 + p1*g0 + p1*p0*c0

c3 = g2 + p2*g1 + p2*p1*g0 + p2*p1*p0*c0

c4 = g3 + p3*g2 + p3*p2*g1 + p3*p2*p1*g0 + p3*p2*p1*p0*c0

因此，超前进位 carry lookahead 逻辑可以根据 p0-p3和 g0-g3 计算进位 c1-c4


Using Carry Lookahead

Practical computation for 4-bit adders, but... Too expensive for 16 bits or 32 bits!

a0 b0

s0

c0 Carry Ing0p0

a1 b1

s1

c1

g1p1

a2 b2

s2

c2

g2p2

a3 b3

s3

c3

g3p3

g3p3 g0p0c1g1p1c2g2p2c3

c4 c0Carry OutG0P0

Carry Lookahead Unit


Using Carry Lookahead

费用是一个限制因素： Cost a limiting factor Practical computation for 4-bit adders, but... Too expensive for 16 bits or 32 bits!

Alternative: Combine 4-bit Carry-Lookahead Adders Ripple/Lookahead - string together CLAs 串联 CLAs Group-Lookahead - add another level of lookahead 增加另

一个级别的进位（组进位）注： CLAs 为超前进位加法器 Carry-Lookahead Adders


Ripple/Lookahead Adder

b3-b0a3-a0

A B

Sc0c4

4 4

4

s3-s0

A B

Sc0c4

4 4

4

A B

Sc0c4

4 4

4

A B

Sc0c4

4 4

4

b7-b4a7-a4b11-b8a11-a8b15-b12a15-a12

s7-s4s11-s8s15-s12

CLACLACLACLA

String together CLA’s Faster than ripple adder, but… Still long delays gi 和 pi 形成后总共需要 2.5x4=10 个门延时得到全部进位，如

果有 64 位，共 16 组，需要 16x2.5=40 个门延时可否使组间进位也同时产生呢？


Group Carry-Lookahead

Approach: use carry lookahead for 4-bit groups “Super Propagate” equations: 超级传播位

P0 = p3*p2*p1*p0

P1 = p7*p6*p5*p4

P2 = p11*p10*p9*p8

P3 = p15*p14*p13*p12

“Super Generate” equations: 超级生成位G0 = g3 + (p3*g2) + (p3*p2* g1) + (p3*p2 *p1 * g0)G1 = g7 + (p7*g6) + (p7*p6* g5) + (p7*p6 *p5 * g4)G2 = g11 + (p11*g10) + (p11*p10* g9) + (p11*p10 *p9 * g8)G3 = g15 + (p15*g14) + (p15*p14* g13) + (p15*p14 *p13 * g12)

Combine groups using second level


Group Carry-Lookahead

b3-b0a3-a0b7-b4a7-a4b11-b8a11-a8b15-b12a15-a12

s3-s0

A B

Sc0

4 4

4

CLAP G

A B

Sc0

4 4

4

CLAP G

A B

Sc0

4 4

4

CLAP G

A B

Sc0

4 4

4

CLAP G

G0P0C1G1P1C2G2P2C3G3P3

C4

s7-s4s11-s8s15-s12

Group Carry Lookahead Unitc16


Delay Comparision - 16 Bit Adder

Ripple Adder 2 gate delays per bit 16 bits Total: 32 gate delays

Group Lookahead Adder Generating C4 (c16) - 2 gate delays from Pi, Gi

Generating Pi, Gi - 2 gate delays from pi, gi

Generating pi, gi - 1 gate delay from ai, bi

Total: 2 + 2 + 1 = 5 gate delays






Arithmetic-Logic Units

能够实现多种功能的组合逻辑元件 : Arithmetic: add, subtract Logical: AND, OR

A

B

F(A,B)

OperationSelect

ALU


Constructing an ALU - First Cut

模仿逐位加法器，在位片 bit slices 层次上构造 Add gates, multiplexer for logic functions, subtract

Ai

Bi

Si

Ci

Ci+1

FAAi

Bi

Ci SELECTINVERTB

Ci+1

0

1

2


ALU Design - Putting it Together

Ai

Si

CiCi+1

Bi

ALU0SEL

INV

Ai

Si

CiCi+1

Bi

ALU1SEL

INV

Ai

Si

CiCi+1

Bi

ALU31SEL

INV

A1 B1A31 B31

S31 S1 S0

Binvert

CarryIn

OperationA0 B0


Overflow Detection in ALUs

Overflow occurs when conditions in Fig. 3.3 are met Problem B.25:检验是否溢出等同于检查最高有效位的进位输入是否和最高有效位的进位输出是否相同

Ci+1

Ai

Si

CiCi+1

Bi

ALU0SEL

INV

Ai

Si

CiCi+1

Bi

ALU1SEL

INV

Ai

Si

CiCi+1

Bi

ALU31SEL

INV

A1 B1A31 B31

S31 S1 S0

Binvert

CarryIn

Operation

OFLO

A0 B0


Supporting the MIPS slt Instruction

Want result of 000…001 when A < B 更改位片硬件



增加一个另外的多路选择输入“ Less” 到片中 Bit0 为 1 ，其他位为 0

Ai

Bi

Si

Ci

Ci+1

FAAi

Bi

Ci OperationBinvert

Ci+1

Lessi

0

1

2

3

Bit 31: 0•••

Bit 1: 0Bit 0: 1 if A<B Set



将 “ Set” 信号反馈到最低位的“ Less” 输入中由于溢出的存在，实际电路要比下图更为复杂

Less

Si

CiCi+1

Bi

ALU0SEL

INV

Less

Si

CiCi+1

Bi

ALU1SEL

INV

Less

Si

CiCi+1

Bi

ALU31SEL

INV

0 B10 B31

S31 S1 S0

Binvert

CarryIn

Operation

Ai

A1

Ai

A0 V0

Set

Ai

A31



Set “less” to “00….01” when result less than zero Details - see Fig. B.5.10, B.5.11 pp. B-33 - B-34

Use sign bit - “pass around” to LSB of “less” Complicated by overflow conditions


Final Result: ALU Function

ALU control input Function000 AND001 OR010 add110 subtract111 set on less than

A

B

Result

ALU Operation

ALUOverflow

Zero

CarryOut






附带 - 补码加减法实现

对于正数，原码 = 补码 = 反码对于负数，符号位为 1 ，然后：

求补码：将原码每位取反末位加 1 求反码：将原码每位取反

已知 y 的补码，求 (-y) 的补码：将 y 的补码连同符号位在内，按位求反，末尾加 1

补码表示很难直接判断其真值大小移码：补码与移码只差一个符号位


例 6.20 设机器数字长为 8 位（含 1 位符号位）且 A = 15 ， B = 24 ，用补码求 A – B

解： A = 15 = 0001111

B = 24 = 0011000

[A] 补 + [– B] 补

+

[A] 补 = 0, 0001111

[– B] 补 = 1, 1101000

= 1, 1110111 = [A – B] 补

[B] 补 = 0, 0011000

练习 1 设 x = y = 用补码求 x+y916

1116

x + y = – 0.1100 = 1216

–

练习 2 设机器数字长为 8 位（含 1 位符号位）且 A = – 97 ， B = +41 ，用补码求 A – B

A – B = + 1110110 = + 118

∴ A – B = – 1001 = –9

错

错

Documents

计算机组成与结构 Lecture 6 - Logic & Arithmetic Reading: 3.1-3.3, B.5, B.6 ORACLE Arithmetic Unit Image Source: Oak Ridge National Laboratory 本课件内容源于美国 Lafayette