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S3C2410

PART I S3C2410 overview

S3C2410architectureIntegrated system for hand-held devices and general embedded applications16/32-Bit RISC architecture and powerfull instruction set with ARM920T CPU coreEnhanced ARM architecture MMU to support WinCE, EPOC 32 and LinuxInstruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performanceARM920T CPU core supports the ARM debug architecture.Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB

S3C2410System ManagerLittle/Big Endian supportAddress space: 128M bytes for each bank (total1G bytes)Supports programmable 8/16/32-bit data bus width for each bankFixed bank start address from bank 0 to bank 6Programmable bank start address and bank size for bank 7Eight memory banks: Six memory banks for ROM, SRAM, and others. Two memory banks for ROM/SRAM/Synchronous DRAMSupports various types of ROM for booting(NOR/NAND Flash, EEPROM, and others)

S3C2410NAND Flash Boot LoaderSupports booting from NAND flash memory

4KB internal buffer for booting

Supports storage memory for NAND flash memory after booting

S3C2410Cache Memory64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB)8words length per line with one valid bit and two dirty bits per linePseudo random or round robin replacement algorithmWrite-through or write-back cache operation toupdate the main memoryThe write buffer can hold 16 words of data and four addresses.

S3C2410Clock & Power ManageThe clock & power management block consists of three parts: clock control, USB control, and power control.Clock can be fed selectively to each function block by software.Power mode: Normal, Slow, Idle, and Power-off modeNormal mode: Normal operating modeSlow mode: Low frequency clock without PLLIdle mode: The clock for only CPU is stopped.Power-off mode: The Core power including all peripherals is shut down.Woken up by EINT[15:0] or RTC alarm interrupt from Power-Off mode

S3C2410Interrupt Controller55 Interrupt sources One Watch dog timer 5 timers 9 UARTs 24 external interrupts 4 DMA 2 RTC 2 ADC 1 IIC 2SPI 1 SDI 2 USB 1 LCD 1 Battery FaultLevel/Edge mode on external interrupt sourceProgrammable polarity of edge and levelSupports Fast Interrupt request (FIQ) for veryurgent interrupt request

S3C2410Timer with Pulse Width Modulation (PWM)4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operationProgrammable duty cycle, frequency, and polarityDead-zone generationSupports external clock sources

S3C2410 RTC (Real Time Clock)Full clock feature: second, minute, hour, date,day, month, and year

32.768 KHz operation

Alarm interrupt

Time tick interrupt

S3C2410 General Purpose Input/Output Ports24 external interrupt ports

multiplexed input/output ports

S3C2410 UART3-channel UART with DMA-based or interruptbased operationSupports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive (Tx/Rx)Supports external clocks for the UART operation (UEXTCLK)Programmable baud rateSupports IrDA 1.0Loopback mode for testingEach channel has internal 16-byte Tx FIFO and 16-byte Rx FIFO.

S3C2410 DMA Controller4-ch DMA controller

Supports memory to memory, IO to memory,memory to IO, and IO to IO transfers

Burst transfer mode to enhance the transfer rate

S3C2410 A/D Converter & Touch Screen Interface

8-ch multiplexed ADC

Max. 500KSPS and 10-bit Resolution

S3C2410 LCD Controller STN LCD Displays Feature

Supports 3 types of STN LCD panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display typeSupports monochrome mode, 4 gray levels, 16 gray levels, 256 colors and 4096 colors for STN LCDSupports multiple screen sizeTypical actual screen size: 640x480320x240160x160 othersMaximum virtual screen size is 4 Mbytes.Maximum virtual screen size in 256 color mode: 4096x1024, 2048x2048, 1024x4096,and others

S3C2410 TFTColor Displays FeatureSupports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFTSupports 16 bpp non-palette true-color displays for color TFTSupports maximum 16M color TFT at 24 bpp modeSupports multiple screen sizeTypical actual screen size: 640x480320x240160x160 othersMaximum virtual screen size is 4 Mbytes.Maximum virtual screen size in 256 color mode: 2048x1024, and others

S3C2410 Watchdog Timer16-bit Watchdog Timer

Interrupt request or system reset at time-out

S3C2410 IIC-Bus Interface1-ch Multi-Master IIC-Bus

Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode.

S3C2410 IIS-Bus Interface1-ch IIS-bus for audio interface with DMA-based operationSerial, 8-/16-bit per channel data transfers128 Bytes (64-Byte + 64-Byte) FIFO for Tx/RxSupports IIS format and MSB-justified data format

S3C2410 USB Host2-port USB Host

Complies with OHCI Rev. 1.0

Compatible with USB Specification version 1.1

S3C2410 USB Device1-port USB Device

5 Endpoints for USB Device

Compatible with USB Specification version 1.1

S3C2410 SD Host InterfaceCompatible with SD Memory Card Protocol version 1.0Compatible with SDIO Card Protocol version 1.0Bytes FIFO for Tx/RxDMA based or Interrupt based operationCompatible with Multimedia Card Protocol version 2.11

S3C2410 Operating Frequency&packageUp to 266MHz

272-FBGA

S3C2410 Operating Voltage RangeCore: 1.8V for 200MHz (S3C2410A-20)2.0V for 266MHz (S3C2410A-26)

Memory & IO: 3.3V

S3C2410X

PART II S3C2410 Signal Descriptions

Bus controller

SDRAM/SRAM

NAND Flash

LCD Control Unit

Interrupt Control Unit

IIC-Bus&IIS-Bus

Touch Screen

USB Host&USB Device

SD&General Port &TIMMER

JTAG TEST LOGIC

Reset, Clock & Power

PART III S3C2410 Registers

S3c2410

0x480000000X60000000

*(volatile *(0x48000000)))=0x55aa

PART IV S3C2410 Watchdog

""(WATCHDOG)

TpTiTi>TpTpTi

S3C2410

MCLK

S3C2410128

t_watchdog = 1/( MCLK / (Prescaler value + 1) / Division_factor )T = WTCNT * t_watchdog

WTCONWTDATWTCNT

WATCHDOGrWATCNT = 8448 * 2;/* */rWATCON = BIT_WDT_ENABLE | BIT_WDT_RST_ENABLE | BIT_WDT_CLK_SEL | BIT_WDT_PRE_SCALER;/* */WDT_CLK_SELWDT_PRE_SCALER#define WDT_CLK_SEL(0X3

WTCNTWDTCNT0X1000rWATCNT = 8448 * 2 ; /* */

PART V S3C2410 RTC

S3C2410RTC

BCD

S3C2410RTC

PWM

RTC--#define YEAR 0X2006#define MONTH 0X11#define DAY 0X11#define DATE 0X06#define HOUR 0X23#define MIN0X34#define SEC 0X30void rtc_set(void){rRTCCON=0x01;rBCDYEAR=YEAR;rBCDMON=MONTH;rBCDDAY=DAY;rBCDDATE=DATE;rBCDHOUR=HOUR;rBCDMIN=MIN;rBCDSEC=SEC;}

RTCvoid rtc_display(void){int year,month,day,weekday,hour,min,sec;rRTCCON=0x01;year= rBCDYEAR ;month=rBCDMON;day=rBCDDAY;weekday=rBCDDATE;hour=rBCDHOUR;min=rBCDMIN;sec=rBCDSEC;//rRTCCON=0x00;}

24/RTC 1RTC2007-08-01-12:00:00 2 3RTC2007-08-01-12:01:0030

PART VI S3C2410 Memory Controller

BANK0 BUS WIDTHThe data bus of BANK0 (nGCS0) should be configured to either 16-bit or 32-bit accordingly. Because the BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will depend on the logic level of OM[1:0] at Reset.

MEMORY (SROM/SDRAM) ADDRESS PIN CONNECTIONS

ROM Memory Interface - Examples1

SRAM Memory Interface - Examples1

SRAM Memory Interface - Examples2

SDRAM Memory Interface - Examples1

SDRAM Memory Interface - Examples2

SDRAMDRAMSDRAMSDRAMDRAMDRAMSDRAMCLKCLKSDRAMSDRAMSDRAMSDRAMbankbankSDRAMbankbankbank

HY57V641620CMOSSDRAM4bankbank4M16100HHz~183MHz

SDRAMbankbankSDRAM32MB26BA1~BA0A25~A24(SDRAM)

16SDRAM 32SDRAM32

32SDRAM

SDRAM 1

SDRAM 2

SDRAM1. SDRAMBWSCONBANKCONnREFRESH

2. #define _WR(addr,data) *((volatile U32 *)(addr))=(U32)data#define _RD(addr) (*(volatile U32 *)(addr))

PART VII S3C2410 UART

()I/O I/O ()

5678ASCII1

10

11 1.5 2

1

1101503006001200240048009600

EIA RS-232C

(Electronic industries Association Recoil-mendedStandard)

25(DB25)

RS-232C PC/XT15(DB-15)I/OPC9(DB-9)

DB-25 DB-9

RS-232C

EIA,

-3V-25V1+3V+25V0

TTL(S3C2410)TTLTTL12V3.3V00V0.4V

RS-232SP3232SP3220TTLEIA

S3C2410UART3I/O DMA115.2KbpsUART216 FIFOS3C2410UART /12 5 6 7 8 UARTMCLK16 FIFOFIFOTxDnRxDnFIFO

S3C2410

S3C2410

16FIFO115.2KUART7UTRSTATnUERSTATn

S3C2410

S3C2410

UBRDIVnPCLKUBRDIVn = (int)[PCLK/(16)]1UCLKUBRDIVn = (int)[UCLK/(16)]1 PCLK40 MHz115 200 bpsUBRDIVn = (int)[40000000/(11520016)]1 = 20

UART

ULCONn

UCONn

FIFOUFCONn

UMCONn

UTRSTAT

UERSTAT FIFOUFSTAT

UTXHURXH

UBRDIV

ULCONn

FIFOUFCONn

MODEMUMCONn

UTRSTAT

UERSTAT

FIFOUFSTAT

UTXHURXH

UBRDIV

1. ChangeClockDivider(1,1); // 1:2:4 ChangeMPllValue(0xa1,0x3,0x1); // FCLK=202.8MHz 2. Port_Init(); 3. Uart_Init(0,115200); Uart_Select(0);

S3C2410GPIOGPH2-GPH3TXD0RXD0//BUSWIDTH=16/* PH15141312111098*//*ooo o oooo*//* 0000000000010101*//* PH76543210*//* oooooooo*//* 0101010101010101*/ rGPDATH= 0x0000;//All IO is lowrGPCONH = 0x5f555555;rGPUPH = 0x3000;//PULL UP RESISTOR should be enabled to I/OPORT

void UartInit(int ch, int baud){U8 a;if(!ch){//0rUFCON0 = 0x0; //FIFO rUMCON0 = 0x0; //AFC rULCON0 = 0x3; //8 rUCON0 = 0x45; //TX RX PULSELEVEL //rx=edge,tx=level,disable timeout int.,enable rx error //int.,normal,interrupt or polling rUBRDIV0 = (int)(MCLK/(16.0*baud)+0.5)-1; a = rURXH0;else//1

void UartSend(int ch, char data){if(!ch){//0if(data=='\n'){while(!(rUTRSTAT0&0x2));Delay(1);//WrUTXH0('\r');}while(!(rUTRSTAT0&0x2));//THRDelay(1);rUTXH0 = data; }else{//1}

int UartReceive(int ch){if(!ch) {//0 while(!(rUTRSTAT0&0x1));//return rURXH0; } else {//1while(!(rUTRSTAT1&0x1));//returnrURXH1; }}

unsigned char ch = 'a';UartSend(0,ch); ChUartReceive(0);

PART VIII S3C2410 GPIO

GPIOThe S3C2410A has 117 multi-functional input/output port pins. The ports are: Port A (GPA): 23-output port Port B (GPB): 11-input/output port Port C (GPC): 16-input/output port Port D (GPD): 16-input/output port Port E (GPE): 16-input/output port Port F (GPF): 8-input/output port Port G (GPG): 16-input/output port Port H (GPH): 11-input/output port

GPIO _A/B/C/D/E/F/G/HGPIO_A/B/C/D/E/F/G/H

GPIO_A/B/C/D/E/F/G/H

GPIO_A/B/C/D/E/F/G/H

2410S3C2410NANDFLASHSDRAM

1.CPU2.3.4.

um_s3c2410x_rev11_012003.pdfS3C2410

1.FrGPFCON=0x55aarGPFUP=0xffff2.FGPF4~GPF7rGPFDATA=0x0

1;asses.sAREA Init,CODE READONLYENTRY_start B MainEND

2#define rGPFCON (*(valotile unsigned int *)(0x56000050)void Main(){rGPFCON=0x55aarGPFUP=0xffffrGPFDATA=0x0

}

35

/RTC/ 1RTC2007-08-01-12:00:00 2 3RTCPC52007-08-01-12:30:0030eLLEDFLED

PART NINE S3C2410 Interrupt Controller

CPU

CPUCPUCPUCPU

CPU

CPUCPUCPU//CPUCPU

CPU DMA

DMA (DMA)DMADMACPU

CPU CPU

CPUCPU

S3C2410

321INTMASK1

1

I/OF(GPFCONGPFDATGPFPU) S3C2410 (PnCON)/(PnDAT)/0 GPFEINT0~EINT7

2

I/OG(GPGCONGPGDATGPGPU) GPFEINT8EINT23

3(EXTINTn) 24EXTINTnN0~2EXTINT0EINT0~7EXTINT1EINT8~15EXTINT2EINT16~23 3100000101X10X11X

4(EXTINTn) 24EXTINTnN0~2EXTINT0EINT0~7EXTINT1EINT8~15EXTINT2EINT16~23 3100000101X10X11X

PART NINE S3C2410 LCD Controller

LCD

LCDLCDLCDLCD

LCD

LCDLCD8051LCD

LCD

LCDLCDLCDMCUARMS3C44B0 /2410

S3C44B0/2410LCDLCDS3C44B0 /2410LCDLCDLCD4 16 LCD256LCDLCDLCD

S3C2410 LCD CONTROLLER- OVERVIEWThe LCD controller in the S3C2410A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver.The LCD controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale)mode on a monochrome LCD FOR STN LCD.It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palettized TFT color LCD panel, and 16-bit per pixel and 24-bit per pixel for non-palettized true-color display.

STN LCD displaysSupports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display typeSupports the monochrome, 4 gray levels, and 16 gray levelsSupports 256 colors and 4096 colors for color STN LCD panelSupports multiple screen sizeTypical actual screen size: 640480, 320240, 160160, and othersMaximum virtual screen size is 4Mbytes.Maximum virtual screen size in 256 color mode: 40961024, 20482048, 10244096, and others

TFT LCD displays:Supports 1, 2, 4 or 8-bpp (bit per pixel) palettized color displays for TFTSupports 16-bpp non-palettized true-color displays for color TFTSupports 24-bpp non-palettized true-color displays for color TFTSupports maximum 16M color TFT at 24-bit per pixel modeSupports multiple screen sizeTypical actual screen size: 640480, 320240, 160160, and othersMaximum virtual screen size is 4Mbytes.Maximum virtual screen size in 64K color mode: 20481024 and others

S3C2410 LCD

TFT LCD CONTROLLER OPERATIONThe TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers.The VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display.

(CONT.)The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations:HOZVAL = (Horizontal display size) -1LINEVAL = (Vertical display size) -1

(CONT.)The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0.VCLK(Hz)=HCLK/[(CLKVAL+1)x2]

(CONT.)The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD,LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows:Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } {(HSPW+1) + (HBPD +1)+ (HFPD+1) + (HOZVAL + 1) } { 2 ( CLKVAL+1 ) / ( HCLK ) } ]

MEMORY DATA FORMAT (TFT)

(CONT.)

LCD POWER ENABLE (STN/TFT)The S3C2410A provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled,the output value of LCD_PWREN pin is controlled by ENVID. In other words, If LCD_PWREN pin is connected to the power on/off control pin of the LCD panel, the power of LCD panel is controlled by the setting of ENVID automatically.The S3C2410A also supports INVPWREN bit to invert polarity of the PWREN signal.This function is available only when LCD panel has its own power on/off control port and when port is connected toLCD_PWREN pin.

S3C2410 LCD

2410 LCD

LCDLCDCPUGPIOLCD320X240X1LCDLCD

46PCPC screen redLCD screen greenLCD screen blueLCD show pic rect(30,30)200100

PART TEN S3C2410 NORFLASH

FLASHS3C2410ROMROMbootloaderflash memoryNOR flashNAND flashNOR flashIntel 1988 EPROM EEPROM 1989NAND flash

,,RAM.RAM

FLASHNOR flashxIP , executc hiPlaceflash RAM NOR flashNOR flashNANDflashNAND flash

NOR &NAND FLASHNOR flash SRAM NAND flashIO IONAND flash512NAND flash

NOR &NAND FLASH/ flashflashNAND flashNOR flash0 NOR flash64 -128KB55ms NAND flash8-32KB4ms NOR flashNAND flashNAND flashNOR flash

NOR &NAND FLASH NAND flash NOR flashNAND flashNOR flash 1 -16MB NAND flash 8-128MB NOR flashNAND flashNAND flashNOR flashNAND flash10 1 NAND flashNOR flash8 NAND

NOR FLASH

NORFLASHvoid U32 GetFlashID(void){volatile unsigned short * _p=FLASH_BASE; volatile unsigned int manu_id,device_id;_p[0x555]=0x00AA;_p[0x2AA]=0X0055;_p[0x555]=0x0090;manu_id=_p[0x000];device_id=_p[0x01];}

Nor FlashNor Flashsectorflash0.25s8s

NORFLASH static int SectorErase(unsigned int sector){unsigned int address;volatile unsigned short * _p=FLASH_BASE;address = sector

NORFLASH SST39VF160U32 WriteSector(unsigned int address,unsigned short data){volatile unsigned short * _p = FLASH_BASE;_p[0x555]=0x00AA;_p[0x2AA]=0x0055;_p[0x555]=0x00A0;_p[address]=data;

}

PART TEN S3C2410 NANDFLASH

NANDFLASHNAND FlashSamsungTOSHIBAFujistuNAND Flash K9F5608U0B264Mb6553652851216512ECC NAND Flash32K9F5608U0B2048

NANFFLASH

PART NINE S3C2410

S3C2410XIO/I/O/S3C2410XS3C2410XS3C2410XS3C2410X/S3C2410X

123ARM9

-1. 2. 3. 4. 5. 6. 7.

-1I/O3.3V2.5VS3C44B0 1.8VS3C24101.25VPXA2555V12V2 3LDO

` 1LDO DC-DCMaximLinear Sipex TI Microchip25VUA7805TL750L05LTC3425REG1117-5 33.3VLT10837.5A LT1084 5A LT1085 3A LT10861.5AREG1117-3.3

12RTC3USB CPUS3C2410XRTCUSB

1S3C2410XPLL12MHz12MHzS3C2410XPLL202.8MHz2PLL

JTAG1JTAG(Joint Test Action Group) 2JTAGARMDSPFPGA3JTAG4TMSTCKTDITDO 4JTAGJTAGJTAG JTAGISPIn-System ProgrammableFLASH5JTAG JTAG 1420

JTAG-14

JTAG-20

JTAG20JTAG

SDRAMSDRAMFlashSDRAMFlash/SDRAMCPU0x0SDRAMSDRAMSDRAMSDRAMSDRAMS3C2410XSDRAMSDRAM

SDRAMSDRAM1SDRAM8/163.3VHYUNDAIWinbondWinbond57V561620W98251657V56162044M3.3V54TSOPLVTTLAuto-RefreshSelf-Refresh16

SDRAM57V561620

SDRAM 57V561620

SDRAMSDRAM

FLASHFLASHFlashIn-SystemFlash

FLASHFLASHFlash8163.3VINTELATMELAMDHYUNDAIINTELTE28F128J3ATE28F128J3A16M3.3V56TSOP48FBGA16TE28F128J3A3.3VFlash

FLASHTE28F128J3A

FLASHFLASH

S3C2410XS3C2410X + SDRAM + FLASHSDRAMFLASHFLASHJTAGFLASHFLASHS3C2410X

PCEIARS-232-CMODEMMODEMRS-232-C925D9D

RXDTXDGNDRS-232-CS3C2410XTTLTTL12V3.3V00V0.4VRS-232-C1-5V-15V0+5V+15VSipexSP3232E

SP3232E

RS232TTL

IICIICIICICSDASCLLCDIICS3C2410XIICIICKS24C08IICKS24C081KEEPROM

IICIIC

S3C2410X60MHz

S3C2410X + + + + JTAGSDRAMFLASH

12MHznRESET3.3V

JTAGJTAGJTAGTMSTCKTDITDOS3C2410BTMSTCKTDITDOTRST

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