第四章 S3C44B0X 硬件结构及功能

S3C44B0X

4 1.S3C44B02.3.4.CUP Wrapper 5.DMA6.I/O7.PWM

8 9 10.11 LCD 12.IIS13.

4.5 DMA S3C44B0X4DMAZDMAGeneral DMASSB(Samsung System Bus)BDMABridge DMASSBSPB(Samsung Peripheral Bus)DMA-----------

4.5 DMA-----------DMABDMA

4.5 DMA-----------DMAZDMA

4.5 DMA-----------ZDMABDMA ZDMAI/OI/O BDMASPBI/OUART, IISSIO ZDMAon-the-flyon-the-flyZDMADMADMA

4.5 DMA-----------ZDMABDMA ZDMAI/OI/O BDMASPBI/OUART, IISSIOZDMAS3C44B0X4FIFO4DMABDMADMAZDMA

4.5 DMA-----------DMA REQ/ACK (Handshake Mode) (Single Step Mode) (Whole Service Mode) Demand Mode

4.5 DMA-----------DMAUnit11Block4, 416 On-the-fly 11

4.5 DMADMA-----------ZDMA

4.5 DMADMA-----------ZDMA 00 :01:10: 11:

4.5 DMADMA-----------ZDMA (nXDREQ)00: 01:

4.5 DMADMA-----------ZDMA 00:01,10,11CMDnXDREQ01:10:nXDREQ11:CMD=01ZDMADMA/

4.5 DMADMA-----------ZDMA/ZDISRCn/ ZDCSRCn

4.5 DMADMA-----------ZDMA/ZDISRCn/ ZDCSRCnZDMAn

4.5 DMADMA-----------ZDMA/ ZDIDESn/ZDCDESn

4.5 DMADMA-----------ZDMA/ ZDIDESn/ZDCDESnBIT OPT[31:30] DMA OPT=10 bit 31:Nxdreq Bit 30 : DSTDMA 1:DMA B0,B1,B2,B3,B4,B5,B6,B7,.B3,B2,B1,B0,B4,B5,B6,B7,

4.5 DMADMA-----------ZDMA/ ZDIDESn/ZDCDESn00:01:10:11:

4.5 DMADMA-----------ZDMA/ ZDIDESn/ZDCDESnZDMAn

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTn

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTnDMA 00: nXDREQ[0] 01: nXDREQ[1 10: 11: ]

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTnDREQ00: 01:10: 11:

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTn00: 01:10: 11:On_the_fly

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTnOn_the_fly 00,01: 10: 11:

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTn 00: 01: 10:11:

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTnDMA 00: 1:

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTnDMA H/W /0: 1:

4.5 DMADMA-----------ZDMA/ZDICNTn/ ZDCCNTnZDMAn /ICNT1ICNT2ICNT4

4.5 DMADMA-----------BDMA

4.5 DMADMA-----------BDMADMA DMA00:

4.5 DMADMA-----------BDMADMA(nXDREQ)(UARTn,SIO,IIS,Timer)00: other:

4.5 DMADMA-----------BDMA01,10,1101/10:DMA

4.5 DMADMA-----------BDMA/BDISRCn/ BDCSRCn

4.5 DMADMA-----------BDMA/BDISRCn/ BDCSRCn00: 01:10: 11:

4.5 DMADMA-----------BDMA/BDISRCn/ BDCSRCn00:01: 10: 11:

4.5 DMADMA-----------BDMA/BDISRCn/ BDCSRCnBDMAn

4.5 DMADMA-----------BDMA/ BDIDESn/BDCDESn

4.5 DMADMA-----------BDMA/ BDIDESn/BDCDESn00:01: M2IO ()10:IO2M() 11: IO2IO()

4.5 DMADMA-----------BDMA/ BDIDESn/BDCDESn00: 01:10: 11:

4.5 DMADMA-----------BDMA/ BDIDESn/BDCDESnBDMAn/

4.5 DMADMA-----------BDMA/BDICNTn/BDCCNTn

4.5 DMADMA-----------BDMA/BDICNTn/BDCCNTnDMA 00:01: IIS10:UART0 11: SIO

4.5 DMADMA-----------BDMA/BDICNTn/BDCCNTn00:

4.5 DMADMA-----------BDMA/BDICNTn/BDCCNTn01:

4.5 DMADMA-----------BDMA/BDICNTn/BDCCNTn00:BDMAnon_the_fly


8 9 10.11 LCD 12.IIS13.

4.6 I/O S3C44B0X 71/ 7 2 9 / EF2 8 / D G1 16 / C1 10 A1 11 B

4.6 I/O-------PCONA-G

/PCONA[90]10x0ld200000=1 1=20x3ffPCONB[100]10x01d200080=1 1=0x7ffPCONC[310]20x0ld2001000= 01=10=2 11=30xaaaaaaaaPCOND[150]20x01d2001c00= 01=10=2 11=30x000PCONE[1716]20x01d2002800=ENDIAN 01=10=CODECLK 11=0x00[150]000= 01=10=2 11=3

4.6 I/O-------PCONA-G

/

PCONF[2110]30X01d20034000= 001=010=2 011=3100=4 =0x0000[90]200= 01=10=2 11=3FCONG[150]20x01D2004000= 01=10=2 11=30x00

4.6 I/O-------PDATA-G PDATnPDATn

4.6 I/O-------PUPC-G PDATnPDATn PC-PGPUPn01

4.6 I/O-------EXTINT PDATnPDATn PC-PGPUPn01 PG 3 EXINT

4.6 I/O-------PFPF 3 PCONFPDATFPUPF

PCONFPF8[2119]000= 001= 010=nCTSL011=SIOCLK 100=IISCLK Others=PF7[1816]000= 001= 010=RxD1011=SIORxD 100=IISDI Others=PF6[1513]000= 001= 010=TxD1011=SIORDY 100=IISDO Others=PF5[1210]000= 001= 010=nRTS1011=SIOTxD 100=IISDO Others=PF4[98]00= 01= 10=nXBREQ 11=nXDREQ0PF3[76]00= 01=10=nXBACK 11=nXDACK0PF2[54]00= 01=10=nWAIT 11=PF1[32]00= 01=10=IICSDA 11=PF0[10]00= 01=10=IICSCL 11=

PDATFPF[80][80]PDATF

PUPF PF[80][80]01


8 9 10.11 LCD 12.IIS13.

4.7 PWM S3C44B0X616DMA 01234PWM50 S3C44B0X16(128)..

4.7 PWM 616 DMA 38 2514 PWM -------

4.7 PWMPWM ------- 018238458

4.7 PWMPWM -------

4-Prescaler=1Prescaler=255/STCNTBn=655351/2MCLK=66MHz0.030s(33.0MHz)7.75s(58.6kHz)0.501/4MCLK=66MHz0.060s(33.0MHz)15.5s(58.6kHz)1.021/8MCLK=66MHz0.121s(33.0MHz)31.0s(29.3kHz)2.031/16MCLK=66MHz0.242s(33.0MHz)62.1s(14.6kHz)4.071/32MCLK=66MHz0.485s(33.0MHz)125s(7.32kHz)8.13

4.7 PWMPWM -------16TCNTn0CPU

0TCNTBn

4.7 PWMPWM ------- TCNTBnTCNTOn TCNTBn

4.7 PWMPWM ------- (1) TCNTBnTCMPBn;(2) (3)

4.7 PWMPWM-------0 TCFG038MCLK/{+1}/{} 02552481632

TCFG0220[3124][2316][158][70]

4.7 PWMPWM-------0

TCFG0220[3124][2316][158][70]

4.7 PWMPWM-------0Timer2Time3 0x00

TCFG0220[3124][2316][158][70]

4.7 PWMPWM-------0[70]Timer0Time1 0x00

TCFG0220[3124][2316][158][70]

4.7 PWMPWM-------1TCFG16-MUX DMA

TCFG1DMAMUX5XUX4MUX3MUX2MUX1MUX0

[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------1


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------15MUX 000

0000=1/2 0001=1/4 0010=1/8 0011=1/16 01xx=EXTCLK


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------14MUX 000

0000=1/2 0001=1/4 0010=1/8 0011=1/16 01xx=TCLK


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------1S3MUX 0000000=1/2 0001=1/4 0010=1/8 0011=1/16 01xx=1/32


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------1S2MUX 0000000=1/2 0001=1/4 0010=1/8 0011=1/16 01xx=1/32


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------1S1MUX 0000000=1/2 0001=1/4 0010=1/8 0011=1/16 01xx=1/32


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------1S0MUX 0000000=1/2 0001=1/4 0010=1/8 0011=1/16 01xx=1/32


[2724][2320][1916][15:12][11:8][7:4][3:0]

4.7 PWMPWM-------TCON

TCONTimer5/Timer5Timer5/Timer4/Timer4/Timer4Timer4/

[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON5/0= 1= 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON50= 1=TCNTB5 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON5/0= 1= 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON4/0= 1= 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON4/0= 1=TOUT4 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON40= 1=TCNTB4TCMPB4 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------TCON4/0= 1= 0


[26][25][24][23][22][21][20]

4.7 PWMPWM-------nTCNTBn,TCMPBnTCMPBn16Timer0~Timer4;TCNTBn16Timer0~Timer5;TCNTOn 16Timer0Timer5.0n/n

4.7 PWM-------S3C44B0X,16 128

4.7 PWM-------

4.7 PWM-------t_watchdog = 1/( MCLK/ (Prescaler value + 1)/ Division_factor )

4.7 PWM-------1(2) (3)


8 9 10.11 LCD 12.IIS13.

4.8 (RTC)

RTC (Real Time Clock),,RTCARMSTRB/LDRB8BCDCPU,RTC32.768

4.8 RTC-------

2000 RTOS

4.8 RTC-------

4.8 RTC--------------/----------------------------

4.8 -------RTCCON

RTCONCLKRSTCNTSELCLKSELRTCEN

3210

4.8 -------RTCCONRTC 0=1=


3210

4.8 -------RTCCONBCD 0=BCDMerge BCD counters1= Separate BCD counters


3210

4.8 -------RTCCONBCD 0=XTAL1/21=XTAL clock only for test


3210

4.8 -------RTCCONRTC 0=1=


3210

4.8 -------RTCALM RTCALM , RTCALM ALMINT PMWKUP ALMINT

RTCALMRTC0x00Reserved[7]ALMEN[6]Alarm0=1=YEAREN[5]alarm 0=1=MONREN[4]alarm 0=1=DAYEN[3]alarm 0=1=HOUREN[2]alarm 0=1=MINEN[1]alarm 0=1=SECEN[0]alarm 0=1=

4.8

ALMSEC~ALMYEARRTC BCDSEC~BCDYEAR RTC ROUNDTICNT /

4.8

ALMSEC~ALMYEARRTC

ALMSEC 0x00Reserved[7]SECDATA[4:6]BCD(0~5)[0:3]0~9

4.8

ALMSEC~ALMYEARRTC

ALMMIN 0x00Reserved[7]MINDATA[4:6]BCD~[0:3]~

4.8

ALMSEC~ALMYEARRTC

ALMHOUR 0x00Reserved[6:7]HOURDATA[0:3]BCD~[4:5]0~9

4.8

ALMSEC~ALMYEARRTC

ALMDAY 0x01 Reserved[ 76]DAYDATA[ 5:4 ]BCD03[ 30]09

4.8

ALMSEC~ALMYEARRTC

ALMMON 0x01 Reserved[ 76]MONDATA[ 4 ]BCD01[ 3:0 ]09

4.8

ALMSEC~ALMYEARRTC

ALMYEAR 0x00 YEARDATA[ 7:0]BCD0099SRSTEN[ 3 ]RoundSECCR[ 2 0]Round011=30 100=40 101=50

4.8

BCDSEC~BCDYEAR

BCDSEC BCD Reserved[ 7 ]SECDATA[ 6 4]BCD05[ 3:0 ]09

4.8

BCDSEC~BCDYEAR

BCDMIN BCD Reserved[ 7 ]NIMDATA[ 64 ]BCD05[ 30]09

4.8

BCDSEC~BCDYEAR

BCDHOUR BSD Reserved[ 7 6]HOURDATA[ 5 4]BCD02[ 3 0]09

4.8

BCDSEC~BCDYEAR

BCDDAY BCD Reserved[ 7 6]DAYDATA[ 5:4 ]BCD03[ 3:0 ]09

4.8

BCDSEC~BCDYEAR

BCDDATE BCD Reserved[ 7 3]DATTEDATA[ 2:0 ]BCD17

4.8

BCDSEC~BCDYEAR

BCDMON BCD Reserved[ 7:5 ]MONDATA[ 4 ]BCD01[30]09

4.8

BCDSEC~BCDYEAR

BCDYEAR BCD YEARDATA[ 70]BCD0099

4.8

TICNT /

TICNT 0x00 TICK INT ENABLE[ 7 ]0= 1=TICK TIME COUNT[ 60](1127),.


8 9 10.11 LCD 12.IIS13.

4.9 S3C44B0X 30 FIQ IRQ

4.9 ------- ARM7TDMI 2 FIQ IRQ

4.9 -------PSR F I PSR ARM7TDMI PSR F 1 FIQ PSR I 1 IRQ PSR F I 0 INTMASK 0

4.9 ------- 30 26 4 (EINT4/5/6/7) 1 ,,ISR() EXTINPND[3:0] 4 ISREXTINPND[3:0] 1 2 UART

0[ 25 ]1[ 12 ]1[ 24 ]2[ 11 ]2[ 23 ]3[ 10 ]3[ 22 ]4[ 9 ]4/5/6/7[ 21 ]5[ 8 ]RTC[ 20 ]UART0[ 7 ]ZDMA0[ 19 ]UART1[ 6 ]ZDMA1[ 18 ]IIC-[ 5 ]BDMA0[ 17 ]SIO-[ 4 ] BDMA1[ 16 ]UART0 [ 3 ][ 15 ]UART1[ 2 ]UART0/1[ 14 ]RTC[ 1 ]0[ 13 ]ADC[ 0 ]

EINT00mGAsGA0x00000020EINT11mGAsGB0x00000024EINT22mGAsGC0x00000028EINT33mGAsGD0x0000002cEINT4/5/6/74/5/6/7mGAsGKA0x00000030TICKRTCmGAsGKB0x00000034INT_ZDMA0ZDMA0mGBsGA0x00000040INT_ZDMA1ZDMA1mGBsGB0x00000044INT_BDMA0BDMA0mGBsGC0x00000048INT_BDMA1BDMA1mGBsGD0x0000004cINT_WDTmGBsGKA0x00000050INT_UERR0/1UART0/1mGBsGKB0x00000054INT_TIMER00mGCsGA0x00000060

4.9 ------- 514642

EINT0,1,2,3EINT4/5/6/7TICKZDMA0,ZDMA1BDMA0,BDMA1WDTUSRR0/1TIMER0,1,2,3TIMER4,5RxD0,1IIC,SIOTXD0,1SGA,B,C,DSGKA,BSGA,B,C,DSGKA,BSGA,B,C,DSGKA,BSGA,B,C,DSGKA,BmGA,B,C,DmGKA,BRTCADCmGKAmGKBmGAmGBmGCmGDARM IRQ

4.9 -------

INTCONReserved V I F3210

4.9 ------- 0


4.9 -------/IRQ 10 1


4.9 -------/FRQ 10 1


4.9 ------- (1) INTPND(3) INTMSK(2) INTMOD(4) IRQ (5) IRQ/FIQ

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第四章 S3C44B0X 硬件结构及功能