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第三章 硬件描述语言 VHDL. 3.1 概述 3.2 VHDL 语言设计单元的基本结构 3.3 VHDL 语言的语言要素 3.4 VHDL 语言的描述语句 3.5 VHDL 语言的库、程序包及配置 3.6 有限状态机设计技术. 3.1 硬件描述语言与 VHDL. HDL: Hardware Description Language VHDL── VHSIC Hardware Description Language ┖─Very High Speed Integrated Circuit - PowerPoint PPT Presentation
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VHDL3.1 3.2 VHDL 3.3 VHDL3.4 VHDL3.5 VHDL3.6
3.1 VHDLHDL: Hardware Description LanguageVHDL VHSIC Hardware Description Language Very High Speed Integrated CircuitIEEEIEEE std 1076-1987, 1076-1993, 2 VHDL-AMS ( AMS -- Analog and Mixed Signal )
VHDL: C CSystemC, SpecC RTL: AHPL, DDL, CDL LDL: GFHL, ndl, : Splice: Spice: CIF, LEF, DEFVHDLVERILOGEDIFVHDL-AMS
3.2 VHDL 3.2.1 1+ Entity; Architecture 2 1 1 EntityArchitectures
3.1 1. entity)entity Half_Adder is port ( X: in bit ; Y: in Bit ; Sum : out bit ; Carry : Out bit) ; end Half_adder;
3. A2Architecture A2 of Half_Adder is component XOR2 port ( I1, I2: in BIT; Out1: out BIT); end component; component AND2 port ( I1, I2: BIT; Out1: out BIT); end component;begin A: XOR2 port map (X, Y, Sum); B: AND2 port map (X, Y, Carry);end A2;
1. VHDL Entity Architecture Configuration LibraryPackage 3.2.2 VHDL
2. VHDL
3. 3.2VHDL D3 D2 D1 D0 Y S1 S0
4. VHDL VHDL VHDL ENTITYEND ARCHITECTUREEND
3.2.3 entity is [] [] end 1.
2. VHDL
Port ({} {} )generic (=
IN OUTINOUTBUFFER
(generic)
entity mux is port(in1,in2,sel: in bit ; output : out bit ); generic (delay : time:=5 ns); end mux ;
3.2.4 VHDL VHDL
3.2.4 VHDL
3.2.4 VHDL
1. ARCHITECTURE OF IS [] BEGIN [] END [ARCHITECTURE] [] 3.2.4 VHDL
2. SIGNAL TYPE CONSTANT COMPONENT FUNCTION PROCEDURE 3.2.4 VHDL
3. 3.2.4 VHDL
3. BLOCK PROCESS SIGNAL 3.2.4 VHDL
3. PROCEDUREFUNCTION COMPONENT 3.2.4 VHDL
3.3 VHDL3.3.1 VHDL3.3.2 VHDL3.3.3
type is
type byte is range 127 to 127;type num is integer range 0 to 9;type resistance is range 1 to 10e8 units ohm; kohm=1000 ohm; end units3.3.1 VHDL
210E6 , 16#D2# 357.6, 8#43.2#e+5 a sd89 B110111 , O712 , X8BD 1 kohm , 5 ns
type is (......;
type boolean is (false,true); type two_level_logic is (0,1);
type is record ........ end record;type pctbus is record adder : std_logic_vector(31 downto 0); data : std_logic_vector (0 to 31); end record;
type is array of type word is array (15 downto 1) of bit
type is array rangeof type bit_vector is array (natural range) of bit; type string is array (positive range) of character;
subtype is subtype lower_letter is character range a to z; subtype register is bit_vector (0 to 7); subtype ascii is character;
STANDARDVHDL() 2. VHDL
1BOOLEAN FALSETRUE IF A>BA>BTRUEFALSE TYPE BOOLEAN IS FALSETRUE 2. VHDL
2BIT 01 TYPE BIT IS 01 2. VHDL
3BIT_VECTOR TYPE BIT VECTOR IS ARRAY (NATURAL RANGE < >) OF BIT 1011X00EA SIGNAL b: BIT VECTOR0 TO 7 bb(0)~b(7)b(0)b(7) 2. VHDL
4CHARACTER TYPE CHARACTER ISASCII ASCIIXy63 ASCII 2. VHDL
5STRING TYPE STRING IS ARRAY(POSITIVE RANGE < >) OF CHARACTER A BOY.10101011 2. VHDL
6INTEGER TYPE INTEGER IS RANGE -2147483647 TO +2147483647 32-(231-1)~+(231-1) -2147483647 ~ +2147483647 1510E316#D5#2#11011010#8#653# 2. VHDL
7POSITIVE SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGERHIGH 0 321~(231-1) 1~2147483647 INTEGERHIGH, 231-1 2. VHDL
8NATURAL SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGERHIGH 0 2. VHDL
9REAL TYPE REAL IS RANGE -1.0E38 TO +1.0E38 -1.0E+38 ~ +1.0E+38 -2.5-1.0E8 2. VHDL
10TIME TYPE TIME IS RANGE 2147483647 TO 2147483647 55 ms20 ns 2. VHDL
10TIME units fs --10-15S ps=1000fs --ns=1000ps --us=1000ns --ms=1000us --sec=1000ms--min=60sec --hr=60min -- END units 2. VHDL
11SEVERITY_LEVEL TYPE severity_level ISnotewarningerrorfailure NOTEWARNING ERRORFAILURE 4 2. VHDL
3. IEEE IEEESTD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR IEEESTD_LOGIC_1164 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL
1STD_LOGIC IEEE11649BIT STD_LOGIC9 U--X-- 0--0 1--1 Z-- W-- L--0 H--1 --- TYPE STD LOGIC ISUX01Z WLH- 3. IEEE
2STD_LOGIC_VECTOR STD_LOGIC STD_LOGIC TYPE STD LOGIC VECTOR IS ARRAYNATURAL RANGE< >OF STD LOGIC 3. IEEE
4. IEEESTD_LOGIC_ARITHIEEE UNSIGNED SIGNED IEEESTD_LOGIC_ARITH LIBRARY IEEE USE IEEE.STD_LOGIC_ARITH.ALL TYPE UNSIGNED IS ARRAYNATURAL RANGE< >OF STD LOGIC TYPE SIGNED IS ARRAYNATURAL RANGE< >OF STD LOGIC
3.3.2 VHDL VHDL VHDL
1. ()
1. BITBOOLEANSTD_LOGICBIT_VECTORSTD_LOGIC_VECTOR
ANDORXOR NOT Y1
2.
3. BOOLEANTRUEFALSE
4. +- (+) (-)
+ -
5. VHDL93VHDL87
: SLLSLLA2A1A00 SRL SRL0A3A2A1 5.
: SLASLAA2A1A0A0 SRASRAA3A3A2A1 5.
: ROLROLA2A1A0A3 ROR RORA0A3A2A1 5.
6.
3.3.3 VHDL VHDL
VHDL
3.3.3 VHDL
EVENTTRUEFALSE 1. CLK CLKEVENTCLK CLKEVENT AND CLK=1CLK CLKEVENT AND CLK=0CLK
IEEESTD_LOGIC_1164 1. RISING_EDGE(CLK) CLKEVENT AND CLK=1 FALLING_EDGE(CLK) CLKEVENT AND CLK=0
() LEFT()RIGHT()HIGH()LOW() 2. num190-- H1 = 9-- H2 = 0-- H3 = 9-- H4 = 0 TYPE num1 IS INTEGER RANGE 9 DOWNTO 0 VARIABLE H1, H2, H3, H4: INTEGER H1: = num1LEFT H2: = num1RIGTH H3: = num1HIGH H4: = num1LOW
3. -- WTH = 16 TYPE num2 IS ARRAY0 TO 15 OF BIT VARIABLE WTH: INTEGER WTH: = num2LENGTH
4. RANGEREVERSE_RANGE data_bus SIGNAL data_bus: STD_LOGIC_VECTOR15 DOWNTO 0 data_busdata_busRANGE=15 DOWNTO 0
4. VARIABLE byte: BIT_VECTOR7 DOWNTO 0 bity byteLEFT=7byteRIGHT=0 byteHIGH=7byteLOW=0 byteLENGTH=8 byteRANGE=7 DOWNTO 0 byteREVERSE_RANGE=0 TO 7
3.3.3 VHDL constant =
constant vcc:real:=5.0; constant delay:time:=100 ns; constant fbus:bit_vector:=0101;
variable =variable x,y :integer ; variable count:integer range 0 to 255:=10 ; tmp3:=tmp1 after 5 ns
signal =: signal sys_clk:bit=0; signal ground:bit:=0;
=, ( ) =
4.5.2 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY adder8 IS PORT ( ci: IN STD_LOGIC a, b: IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) s: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) co: OUT STD_LOGIC ) END adder8 abcisco
3.4 VHDL() ()
[]process [] begin [] end process;
. = < =
variable a,b;std_logic_vector(1 to 4);a(1to 2) :=10;a( 1 to 4):=0101;
signal a,b,c,d: std_logic;signal s : std_logic_vector(1 to 4);s c,2=>b,1=>d)
. ifcaseloopnextexit
1. if
if then elsif then . elsif then else end if ;
.
.
CASE (2) CASE CASE IS WHEN => WHEN => WHEN OTHERS => END CASE =>THEN
CASE 5 1 TO 3) 4 | 646
CASE CASEWHEN WHEN CASEOTHERS ,OTHERS; =>THEN CASE
LOOP3 VHDL 3LOOP LOOP FOR_LOOP WHILE_LOOP LOOP
FOR_LOOP 3 VHDL FOR_LOOP [:] FOR IN TO LOOP END LOOP [] [:] FOR IN DOWNTO LOOP END LOOP []
13 VHDL FOR_LOOP = |-|+1
FOR_LOOP 3 VHDL X8X1Y=1Y=0 FOR_LOOPX n 07
WHILE_LOOP 3 VHDL WHILE_LOOP [:] WHILE LOOP END LOOP [] ,
LOOPNEXTEXIT 3 VHDL LOOP [ : ] LOOP END LOOP [] LOOP L2: LOOP A := A+1 EXIT L2 WHEN A>10 END LOOP L2-- A 10
NEXTLOOP 3 VHDL 4NEXT NEXT [ ] [ WHEN ]
NEXT 3 VHDL 4NEXT 1 NEXT 2 NEXT 3 NEXT WHEN
3 VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY NEXT_WHEN2 IS PORT ( d: IN STD_LOGIC_VECTOR ( 0 TO 31) y: OUT STD_LOGIC_VECTOR ( 0 TO 3 ) ) END NEXT_WHEN2 ARCHITECTURE example7 OF NEXT_WHEN2 IS BEGIN PROCESS ( d ) VARIABLE i,k,j: INTEGER VARIABLE tmp: STD_LOGIC d[0..31]y[0..3]1y[i]=1y[i]=0
EXITNEXTLOOP3 VHDL 5EXIT EXIT [ ] [ WHEN ]
EXIT 3 VHDL 5EXIT 1 EXIT ,END LOOP 2 EXIT 3 EXIT WHEN
WAIT 3 VHDL 3. WAIT [ON ] [UNTIL ] [FOR ] WAIT
WAIT 3 VHDL 1 WAIT 2 WAIT ON SIGNAL ab STD LOGIC PROCESS WAIT ON ab END PROCESS-- ab 3.
NULLNOP 3 VHDL 4. NULL CASE sel IS WHEN 00 => y y y NULL END CASE --
3.4.2 VHDL VHDL VHDL
3.4.2 VHDL VHDL VHDL
PROCESS VHDL 1.
VHDL 1 [:] PROCESS [()] [IS][] BEGIN END PROCESS []
VHDL 2
VHDL 2
VHDL 2 PROCESSWAIT IFCASELOOPNULL NEXTEXIT
, VHDL 2.
BLOCK VHDL 3.
VHDL 1 BLOCK BEGIN END BLOCK
VHDL 2
ABSUMSUBCOBO VHDL LIBRARY IEEE USE IEEE.STD LOGIC 1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY add_sub IS PORTA, B: IN STD LOGIC_VECTOR7 DOWNTO 0 SUM, SUB: OUT STD LOGIC_VECTOR7 DOWNTO 0 CO, BO: OUT STD LOGIC END add_sub
VHDL 4. COMPONENT IS GENERIC PORT END COMPONENT PORT MAP
GENERICPORT VHDL 4. PORT MAP
VHDL YD0 D1D2 D3S1S0AB
VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux4 IS PORT ( D0, D1, D2, D3: IN STD_LOGIC S0, S1: IN STD_LOGIC Y: OUT STD_LOGIC ) END mux4 ARCHITECTURE example13 OF mux4 IS COMPONENT mux2 PORT ( a, b, s: IN STD_LOGIC y: OUT STD_LOGIC ) END COMPONENT SIGNAL A, B: STD_LOGIC BEGIN U1: mux2 PORT MAP ( D0, D1, S0, A ) U2: mux2 PORT MAP ( a => D2, b => D3, s => S0, y => B ) U3: mux2 PORT MAP ( A, B, S1, y => Y ) END exmple13-- ---- -- --
VHDL 4. PORT MAP ( )COMPONENTPORT U1: mux2 PORT MAP (D0, D1, S0, A ) D0D1S0Aabsy =>PORT MAP ( ) U2: mux2 PORT MAP (a=>D2,b=>D3,s=>S0,y=>B) PORT MAP( ) U3: mux2 PORT MAP (A,B,S1,y=>Y)
: xycincoutsumxycincoutsumEntity full _adder is port (x ,y, cin :in bit; sum ,cout : out bit);End full _adder;u1u2c1s1c2
GENERATE VHDL 5.
VHDL 5. 1 [:] FOR IN GENERATE BEGIN END GENERATE []
VHDL 5. 2 [:] IF GENERATE BEGIN END GENERATE []
FORIF VHDL 5.
VHDL 1D LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY shift_reg_8 IS PORT ( Din, CLK: IN STD_LOGIC Dout: OUT STD_LOGIC ) Q: BUFFER STD_LOGIC_VECTOR ( 7 DOWNTO 0 )) END shift_reg_8 ARCHITECTURE example14 OF shift_reg_8 IS COMPONENT ff_d PORT ( d, cp: IN STD_LOGIC q: IN STD_LOGIC ) END COMPONENT SIGNAL d: STD_LOGIC_VECTOR ( 0 TO 8 ) --
ASSERTVHDL VHDL 6. ASSERT [REPORT ] [SEVERITY ]
NOTEWARNINGERRORFAILURE VHDL 6. RSRS1 ASSERT S =1 AND R =1 REPORT S =1and R = 1 SEVERITY ERROR
3.4.3 VHDL VHDL VHDL PROCEDURE FUNCTION
VHDL 1. 1
VHDL 1 ,INOUTINOUT PROCEDURE PROCEDURE IS [] BEGIN END PROCEDURE
VHDL 2 => =>
VHDL 2
VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY add IS PORT ( A, B, C: IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ) CLK, SET: IN STD_LOGIC S: OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 )) END add ARCHITECTURE example15 OF add IS PROCEDURE add_1 ( VARIABLE data1,data2,data3: IN STD_LOGIC_VECTOR VARIABLE dataout: OUT STD_LOGIC_VECTOR IS BEGIN dataout:= data1 + data2 + data3 END add_1 --
VHDL 2. 1 FUNCTION RETURN
VHDL 2 FUNCTION RETURN IS [] BEGIN RETURN [] END FUNCTION []
VHDL 3 => =>
VHDL FUNCTION LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY min IS PORT ( A, B: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) Y: OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 )) END min
VHDL 3. 1 RETURN 2 RETURN
3.5
IEEESTD, ASIC,WORK, IEEE STD_LOGIC_1164 STD_LOGIC_arith STD_LOGIC_unsigned STD_LOGIC_signed
STD standard : textio : /
ASIC ASIC
Work
library use .. use .. all library ieee ; use ieee.std_logic_1164.all
VHDL
PACKAGE IS END PACKAGE BODY IS END
PACKAGE logic ISTYPE three_level_logic IS (0,1,z);CONSTANT unkown_value : three_level_logic :=0;FUNCTION invert ( input : three_level_logic ) RETURN three_level_logic ;END logic;PACKAGE BODY logic ISFUNCTION invert (input : three_level_logic )RETURN three_level_logic ISBEGIN CASE input IS WHEN 0=> RETURN1; WHEN 1=> RETURN 0 ; WHENz=> RETURN zEND CASE ;END invert ;END logic ;
LIBRARY IEEE; USE IEEE STD-LOGIC-1164.ALL; PACKAGE UPAC IS CONSTANT K:=INTEGER:=4; SUBTYPE CPU-BUS IS STD-LOGIC-VECTOR(K-1 DOWNTO 0); END UPAC;
USE logic. Three _ level_ logic USE logic. invert USE logic.all ;logic+
:
::,:
: xycincoutsumxycincoutsumEntity full _adder is port (x ,y, cin :in bit; sum ,cout : out bit);End full _adder;u1u2c1s1c2
Architecture describ1 of full_adder is component half_adder generic (tpd:time:=2 ns); port(a,b: in bit; s,c: out bit); end component; component or_gate port(o1,o2: in bit; o3: out bit); end component; signal c1,s1,c2:bit; for u1: half_adder use entity half_adder(a1); for u2: half_adder use entity half_adder(a2); begin u1: half_adder generic map (4 ns) port map (x,y,s1,c1); u2: half_adder generic map (4 ns) port map (s1,cin,sum,c2); u3: or_gate port map (c1,c2,cout) ;End describ1;u1,u2,u3
Configuration config1 of full_adder is for describ2 for u1: half_adder use entity half_adder(a1); end for; for u2: half_adder use entity half_adder(a2); end for; end forend config1: configuration of is for []; end for; end ;
Architecture describ3 of full_adder issignal c1,s1,c2:bit;begin u1: entity half_adder(a1) generic map (4 ns) port map (x,y,s1,c1); u2: entity half_adder(a2) generic map (4 ns) port map (s1,cin,sum,c2); u3: entity or_gate port map (c1,c2,cout) ;End describ3;
::entity [.][()] [generic map()] port map();
VHDL
VHDL
Block
block [] begin [] end block
[]process12. [] begin [] end process;
procedure 12.....is [] begin [] end
function 12 return is [] begin [] Return []; End []
inin,out,inoutininout,inout
3.6 TYPETYPETYPE IS OF ;TYPE IS ;
TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ;TYPE week IS (sunmontuewedthufrisat) ;
TYPE m_state IS ( st0st1st2st3st4st5 ) ; SIGNAL present_statenext_state : m_state ;
TYPE BOOLEAN IS FALSETRUE TYPE my_logic IS ( '1' 'Z' 'U' '0' ) ; SIGNAL s1 : my_logic ; s1
SUBTYPE
SUBTYPE IS RANGE ;
SUBTYPE digits IS INTEGER RANGE 0 to 9 ;
VHDL
1. 2. ARCHITECTURE ...IS TYPE FSM_ST IS (s0s1s2s3); SIGNAL current_state, next_state; FSM_ST; ...
3. next_statenext_state
MooreMoore MealyMealy
ClockNo Clock
3.6.2 Moore ADC0809ADC0809+FPGA
ADC0809
ADC0809
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --08098CLK : IN STD_LOGIC; --EOC : IN STD_LOGIC; --ALE : OUT STD_LOGIC; --8START : OUT STD_LOGIC; --OE : OUT STD_LOGIC; --3ADDA : OUT STD_LOGIC; --LOCK0 : OUT STD_LOGIC; --Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8END ADCINT;ARCHITECTURE behav OF ADCINT ISTYPE states IS (st0, st1, st2, st3,st4) ; -- SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; --
ADC0809
RTLSynplify
1.0s
2.0s
3.0s
4.0s
5.0s
6.0s
7.0s
8.0s
MEALY2 LIBRARY IEEE; --MEALY FSMUSE IEEE.STD_LOGIC_1164.ALL;ENTITY MEALY2 IS PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));END MEALY2;ARCHITECTURE behav OF MEALY2 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL STX : states ; SIGNAL Q1 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN COMREG : PROCESS(CLK,RESET) -- BEGIN IF RESET ='1' THEN STX
END IF; END PROCESS COMREG ;COM1: PROCESS(STX,DATAIN,CLK) -- VARIABLE Q2 : STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN CASE STX IS WHEN st0 => IF DATAIN = '1' THEN Q2 := "10000" ; ELSE Q2 := "01010" ; END IF ; WHEN st1 => IF DATAIN = '0' THEN Q2 := "10111" ; ELSE Q2:="10100" ; END IF ; WHEN st2 => IF DATAIN = '1' THEN Q2 := "10101" ; ELSE Q2:="10011" ; END IF ; WHEN st3=> IF DATAIN = '0' THEN Q2 := "11011" ; ELSE Q2:="01001" ; END IF ; WHEN st4=> IF DATAIN = '1' THEN Q2 := "11101" ; ELSE Q2:="01101" ; END IF ; WHEN OTHERS => Q2:="00000" ; END CASE ;
3.6.4 START = current_state4 ALE = current_state3 OE = current_state2 LOCK = current_state1
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY AD574A IS PORT ( D : IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK ,STATUS : IN STD_LOGIC; OUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) );END AD574A;ARCHITECTURE behav OF AD574A ISSIGNAL current_state, next_state: STD_LOGIC_VECTOR(4 DOWNTO 0 ); CONSTANT st0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100" ; CONSTANT st1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001" ; CONSTANT st2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000" ; CONSTANT st3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100" ; CONSTANT st4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110" ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LK : STD_LOGIC; BEGIN COM1: PROCESS(current_state,STATUS) --
BEGIN CASE current_state IS WHEN st0 => next_state next_state IF (STATUS='1') THEN next_state
...SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(2 DOWNTO 0 );CONSTANT ST0 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ;CONSTANT ST1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001" ;CONSTANT ST2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010" ;CONSTANT ST3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011" ;CONSTANT ST4 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100" ;
STATE0
000
100000
STATE1
001
010000
STATE2
010
001000
STATE3
011
000100
STATE4
100
000010
STATE5
101
000001
One-hot encoding
3.6.5
st0
000
st1
001
st2
010
st3
011
st4
100
st_ilg1
101
st_ilg2
110
st_ilg3
111
One hot Gray Binary
4 : state0, state1, state2, state3 :(2 bits : 00 01 10 11 (Binary)(4 bits : 1000 0100 0010 0001 (One Hot)(2 bits : 00 01 11 10 (Grey Code
FPGACycloneSpantan-3ECPLDMAX3000AXC9500XLCPLD
Sample State Machinelibrary ieee;use ieee.std_logic_1164.all;package your_own_type istype t_state is (idle,state0,state01,state011, state0110,state01101, state011011, dummy0, dummy1, dummy2, dummy3, dummy4, dummy5, dummy6, dummy7, dummy8, dummy9, dummy10);end your_own_type;library ieee;use ieee.std_logic_1164.all;use work.your_own_type.all;Entity stmh isport (clk, serial_in, reset : in std_logic; match : out std_logic);end stmh;architecture body_stmh of stmh is
when state011 => if (serial_in = '0') then present_state
Quartus IISynplify
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