IKI10230Pengantar Organisasi Komputer

Bab 7: Control UnitSumber:1. Hamacher. Computer Organization, ed-5.

1

28 Mei 2003

Bobby Nazief (nazief@cs.ui.ac.id)Qonita Shahab (niet@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki1023 0/

1. Hamacher. Computer Organization, ed-5.2. Materi kuliah CS152/1997, UCB.

2

Pengendalian Eksekusi Instruksi:

Hardwired Control

Prosesor: Control & Datapath

Processor(active)

Computer

Control(“brain”)

Memory(passive)

(where

Devices

Input

3

(“brain”)

Datapath(“brawn”)

(where programs, data live whenrunning)

Output

Review: Organisasi Prosesor (Single-bus)

MDR

MAR

PC

R0

IR

InstructionDecoder

Address lines

Data lines

Control lines

Memory bus

Control Unit

4

Y

Z TEMP

R(n-1)

ALUCarry-in

AddSub

XOR

ALU control lines

DatapathUnit

Interaksi Control ↔↔↔↔ Datapath

ControlInstruction

Datapath

IR

Con

ditio

ns

ControlSignalsPCout

MAR in ADD

Ri in

5

STEP CONTROL SIGNALS

1. PCout , MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in

2. Zout , PCin, WMFC

3. MDRout , IRin

4. R3out , MAR in, Read

5. R1out , Yin, WMFC

6. MDRout , Add, Z in

7. Zout , R1in, End

Datapath

Organisasi Unit Pengendali

Control StepCounter

Clock

StatusFlags

CLK

• • •

••

•

6

Decoder/Encoder

IR

Flags

ConditionCodes

Control Signals

••

•

••

•

• • •

Pemisahan Decoder & Encoder

Control StepCounter

Clock

Status

Step Decoder

LDI

CLK

• • •

T1 T2 • • • Tn

Reset

7

EncoderIR

StatusFlags

ConditionCodes

InstructionDecoder

LDI

• • •

Control Signals

••

•

••

•

••

••

••

LD

INSn

Run End

Contoh Struktur Encoder untuk sinyal Z in

° Fungsi Logika:Zin = T1 + T6 •••• ADD + T5 •••• BR + …

° Zin akan terjadi pada:• T : untuk setiap instruksi

ADD BR

T5T6

8

• T1: untuk setiap instruksi(instruksi berikut: PC+1)

• T5: untuk instruksi ADD

• T6: untuk instruksi BR

T1• • • •

Zin

Interaksi Memori ↔↔↔↔ [Control,Datapath]

Data

5

Rw Ra Rb

Rd

DataAddress

Instruction

InstructionAddress

IdealInstruction

Memory

5Rs

5Rt

32A

Nex

t Add

ress

ControlControl Signals Conditions

9

DataOut

Clk

Rw Ra Rb

Registers

ALU

Clk

Data In

AddressIdealData

Memory

Clk

PC

32

323232

B

Nex

t Add

ress

Datapath

10

Pengendalian Eksekusi Instruksi:

Microprogrammed Control

Microprogramming

° Control is the hard part of processor design°Datapath is fairly regular and well-organized

°Memory is highly regular

°Control is irregular and global

Microprogramming:

-- A Particular Strategy for Implementing the Contro l Unit of aprocessor by "programming" at the level of register transfer operations

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operations

Microarchitecture:

-- Logical structure and functional capabilities of the hardware asseen by the microprogrammer

Historical Note:

IBM 360 Series first to distinguish between archite cture & organizationSame instruction set across wide range of implement ations, each with

different cost/performance

MicroinstructionsSTEP CONTROL SIGNALS

1. PCout , MAR in, Read, Clear Y, Carry-in to ALU, Add, Z in

2. Zout , PCin, WMFC

3. MDRout , IRin

4. R3out , MAR in, Read

5. R1out , Yin, WMFC

6. MDRout , Add, Z in

7. Zout , R1in, End

in12

0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 00 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 01 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 00 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 00 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1

IRin

PC

in

PC

out

MA

Rin

MD

Rou

t

Yin

R1 i

n

R1 o

ut

R3 o

ut

Zin

Zou

t

Cle

ar Y

Car

ry-i

n

Add

Rea

d

WM

FC

End

1

2

3

4

5

6

7

Organisasi Microprogrammed Control Unit

IRStartingAddress

Generator

Clock µPC

13

0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 00 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 01 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 00 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 00 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1

IRin

PC

in

PC

out

MA

Rin

MD

Rou

t

Yin

R1 i

n

R1 o

ut

R3 o

ut

1

2

3

4

5

6

7

Clock µPC

ControlStore Control

Word

Organisasi µProgrammed Control Unit: Branching

IRStartingAddress

Generator

Clock µPC

Status Flags

Condition Codes

14

Clock µPC

ControlStore Control

Word

Addr. Microinstruction

0 PCout , MAR in, Read, Clear Y, Carry-in to ALU, Add, Z in

1 Zout , PCin, WMFC

2 MDRout , IRin

3 Branch to starting addr. of appropriate µroutine…………………………………………………………………………….

25 PCout , Yin, if N=0 then branch to µinstruction 0

26 Offset-field-of-IR out , Add, Z in

27 Zout , R1in, End

Encoding of Microinstruction

0000: No transfer

0001: PCout

0010: MDRout

0011: Zout

0100: R0out

000: No transfer

001: PC in

010: IR in

011: Z in

100: R0 in

0000: ADD

0001: SUB

.

.

.

000: No transfer

001: MAR in

010: MDR in

011: TEMP in

100: Yin

F4F2F1 F3

(4 bits)(3 bits)(4 bits) (3 bits)

15

0100: R0out

0101: R1out

100: R0 in

101: R1 in

.

1111: XOR

100: Yin

° Most signals are not needed simultaneously

° Many are mutually exclusive:• ALU: 1 function at a time

• Data source is unique

° Organization:• Vertical Organization (Highly Encoded µInstruction)

• Horizontal Organization (otherwise)

Microprogram Sequencing: Branching Implementation

° 1 Machine Instruction ���� 1 Set of µInstructions• large total number of µInstruction

• large Control Store

° Many Addressing Modes ���� many instruction combinations

• results in many duplications of common parts

If the common parts are to be shared �� many

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° If the common parts are to be shared ���� many branches

• results in longer execution time

����Need efficient branching techniqe ���� Bit-ORing

Microprogram Sequencing (1/2): Add src ,Rdst

MAR ���� [PC]; Read; Z ���� [PC]+1

PC ���� [Z]; WMFC

IR ���� [MDR]

Start

000

001

002

003

17

Branch[InstDec,OR]

MAR ���� [PC]; Read;Z ���� [PC]+1

Z ���� [Rsrc] - 4 MAR ���� [PC]; Read;Z ���� [PC]+1

MAR ���� [Rsrc];Read

PC ���� [Z]; WMFC MAR, Rsrc ���� [Z];Read

Z ���� [Rsrc] Branch[171]; WMFC

111141161 121

112142162 122

Indexed Autodecrement Autoincrement Register indirect

Microprogram Sequencing (2/2): Add src ,Rdst

Branch[170,OR];WMFC

Branch[170,OR];WMFC

Branch[170,OR];WMFC

Branch[171];WMFC

112143166 123Indexed Autodecrement Autoincrement Register indirect

MAR ���� [MDR]; Read; WMFC

170

18

End

MAR ���� [MDR]; Read; WMFC

Y ���� [MDR]

171

Z ���� [Y] + [Rdst]

172

Rdst ���� [Z]

173

Branching in Microinstruction: Add (Rsrc )+,Rdst

Rdst0 1 0OP code Rsrc

11 10 8 7 4 3 0

Addr. Microinstruction000 PCout , MAR in, Read, Clear Y, Set carry-in, Add, Z in

001 Zout , PCin, WMFC

002 MDRout , IRin

003 µBranch { µPC ←←←← 101; µPC ←←←← [IR ]; µPC ←←←← [IR ].[IR ].[IR ]}

IR10,9 = 01 (autoincrement)

Mode

19

003 µBranch { µPC ←←←← 101; µPC5,4 ←←←← [IR10,9]; µPC3 ←←←← [IR10].[IR9].[IR8]}

121 Rsrc out , MAR in, Read, Clear Y, Set carry-in, Add, Z in

122 Zout , Rsrc in

123 µBranch { µPC ←←←← 170; µPC0 ←←←← [IR8]}, WMFC

170 MDRout , MAR in, Read, WMFC

171 MDRout , Yin

172 Rdst out , Add, Z in

173 Zout , Rdst in, End

ADD

IR8 = 0 (direct)

Bit ORing

Microinstruction Sequencing: Organization

Status Flags Condition Codes

IR

Decoding Circuits

20

µAR

ControlStore

µIRNext Address

µInstruction Decoder• • •

Control Signals

Encoding of Microinstruction w/ Next Address

000: No transfer

001: PCout

010: MDRout

011: Zout

100: Rsrc out

000: No transfer

001: PC in

010: IR in

011: Z in

100: Rsrc in

000: No transfer

001: MAR in

010: MDR in

011: TEMP in

100: Yin

F3F1F0 F2

(3 bits)(3 bits)(8 bits) (3 bits)

Address of nextmicroinstruction

21

101: Rdst out 101: Rdst in

0000: ADD

0001: SUB

.

.

1111: XOR

F4 F9

(1 bit)

. . .

(4 bits)

F8

(1 bit)

0: NextAdrs

1: InstDec

0: No action

1: ORmode

F10

(1 bit)

0: No action

1: ORindsrc

Content of µStore

F0 F1 F2 F3 F4 F5 F6

F7

F8

F9

F10

0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 00 0 2 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 00 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 01 2 2 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 01 7 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

000001002003121122

22

1 7 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 11 7 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 01 7 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 01 7 3 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

122170171172173

23

/Etc

“Macroinstruction” Interpretation

MainMemory

execution

ADDSUBAND

DATA

.

.

.

User program plus Data

this can change!

one of these ismapped into oneof these

24

executionunit

controlmemory

CPU AND microsequence

e.g., FetchCalc Operand AddrFetch Operand(s)CalculateSave Answer(s)

Control: Hardware vs. Microprogrammed

° Control may be designed using one of several initia l representations. The choice of sequence control, and how logic is re presented, can then be determined independently; the control can then b e implemented with one of several methods using a structured logic tec hnique.

Initial Representation Finite State Diagram Microprog ram

25

Sequencing Control Explicit Next State Microprogram counterFunction + Dispatch ROMs

Logic Representation Logic Equations Truth Tables

Implementation Technique PLA ROM“ hardwired control” “ microprogrammed control”