1998׃1 Morgan Kaufmann Publishers

jumpפקודת ה-

4 bits 26 bits 2 bits

00

כתובת קפיצה במילים :

כתובת קפיצה בבתים :

0101

101 … 101111011

101 … 101111011

101 … 101111011

00 101 … 1011110110101 הקפיצה הסופית :

ביטים אחרונים4תוספת :

…J 101 הפקודה נמצאת בכתובת .…0101111 101111011

1998׃2 Morgan Kaufmann Publishers

Multicycle Approach

:Multicycle הרעיון מאחורי שיטת ה-

חסיכון בזמן: כל פקודה תקח את מספר היחידות השעון הנחוצות לה.

חיסכון ברכיבים: שימוש באותו רכיב בשלבים שונים של הפקודה.

1998׃3 Morgan Kaufmann Publishers

Jump

Shiftleft 2

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Datamemory

Readdata

Writedata

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction [15– 11]

Instruction [20– 16]

Instruction [25– 21]

Add

ALUresult

Zero

Instruction [5– 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

Branch

JumpRegDst

ALUSrc

Instruction [31– 26]

4

Mux

Instruction [25– 0] Jump address [31– 0]

PC+4 [31– 28]

Signextend

16 32Instruction [15– 0]

1

Mux

1

0

Mux

0

1

Mux

0

1

ALUcontrol

Control

Add ALUresult

Mux

0

1 0

ALU

Shiftleft 2

26 28

Address

1998׃4 Morgan Kaufmann Publishers

Performance of Single-Cycle Machines

• Memory Unit 2 ns• ALU and Adders 2 ns• Register file (Read or Write) 1 ns

Class Fetch Decode ALU Memory Write Back Total

R-format 2 1 2 0 1 6

LW 2 1 2 2 1 8

SW 2 1 2 2 7ns

Branch 2 1 2 5ns

Jump 2 2ns

1998׃5 Morgan Kaufmann Publishers

של השעון היה באורך משתנה cycleמה היה קורה עם

נשווה לגבי תוכנית עם התערובת הבאה של פקודות:•

•24% LW 12% SW 44% R

•44% BRANCH 2% JUMP

•Iמספר פקודות בתוכנית -

•T אורך מחזור שעון -

•CPI = 1 - מספר מחזורים לפקודה

Execution=I*T*CPI= 8*24%+7*12%+6*44+5*18%+2*2%=6.3 ns

1998׃6 Morgan Kaufmann Publishers

התוצאה

EXE Single cycle T single clock * I T single clock 8

EXE Variable T variable clock * I T variable clock 6.3

. היחס יהיה יותר גרוע כאשר נממש פקודות מסובכות כמו 1.27יחס של floating pointפעולות עם

הפתרון: אינו שעון בגודל משתנה - מסובך מבחינת הבניה.

.cycles הפתרון: פקודה לוקחת מספר משתנה של

1998׃7 Morgan Kaufmann Publishers

Multicycleשיטת הבניה של ארכיטקטורת ה-

:cycleחלק את הפקודה לשלבים. כל שלב

- אזן את כמות העבודה הנדרשת בכל שלב.

- הקטן את כמות העבודה הנדרשת בכל שלב - כל שלב יבצע רק פעולה אחת פונקצינאלית.

בסיום כל מחזור שעון:

- שמור את הערכים עבור השלבים הבאים.

- אוסף לביצוע משימה זו רגיסטרים פנימיים נוספים.

1998׃8 Morgan Kaufmann Publishers

multicycleמבנה המחשב בארכיטקטורת ה-

Shiftleft 2

PC

Memory

MemData

Writedata

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Mux

0

1

Mux

0

1

4

Instruction[15– 0]

Signextend

3216

Instruction[25– 21]

Instruction[20– 16]

Instruction[15– 0]

Instructionregister

1 Mux

0

3

2

Mux

ALUresult

ALUZero

Memorydata

register

Instruction[15– 11]

A

B

ALUOut

0

1

Address

1998׃9 Morgan Kaufmann Publishers

סיכום שלבי הפקודות השונות

Step nameAction for R-type

instructionsAction for memory-reference

instructionsAction for branches

Action for jumps

Instruction fetch IR = Memory[PC]PC = PC + 4

Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]

ALUOut = PC + (sign-extend (IR[15-0]) << 2)

Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion

Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or

Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR

1998׃10 Morgan Kaufmann Publishers

Shiftleft 2

PCMux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Instruction[15– 11]

Mux

0

1

Mux

0

1

4

Instruction[15– 0]

Signextend

3216

Instruction[25– 21]

Instruction[20– 16]

Instruction[15– 0]

Instructionregister

ALUcontrol

ALUresult

ALUZero

Memorydata

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWrite

Control

Outputs

Op[5– 0]

Instruction[31-26]

Instruction [5– 0]

Mux

0

2

Jumpaddress [31-0]Instruction [25– 0] 26 28

Shiftleft 2

PC [31-28]

1

1 Mux

0

3

2

Mux

0

1ALUOut

Memory

MemData

Writedata

Address

Final State Machine

PCWritePCSource = 10

ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond

PCSource = 01

ALUSrcA =1ALUSrcB = 00ALUOp= 10

RegDst = 1RegWrite

MemtoReg = 0

MemWriteIorD = 1

MemReadIorD = 1

ALUSrcA = 1ALUSrcB = 10ALUOp = 00

RegDst = 0RegWrite

MemtoReg =1

ALUSrcA = 0ALUSrcB = 11ALUOp = 00

MemReadALUSrcA = 0

IorD = 0IRWrite

ALUSrcB = 01ALUOp = 00

PCWritePCSource = 00

Instruction fetchInstruction decode/

register fetch

Jumpcompletion

BranchcompletionExecution

Memory addresscomputation

Memoryaccess

Memoryaccess R-type completion

Write-back step

(Op = 'LW') or (Op = 'SW') (Op = R-type)

(Op

= 'B

EQ')

(Op

= 'J

')

(Op = 'SW

')

(Op

= 'L

W')

4

01

9862

753

Start

1998׃12 Morgan Kaufmann Publishers

• Implementation:

Finite State Machine for Control

PCWrite

PCWriteCond

IorD

MemtoReg

PCSource

ALUOp

ALUSrcB

ALUSrcA

RegWrite

RegDst

NS3NS2NS1NS0

Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

State register

IRWrite

MemRead

MemWrite

Instruction registeropcode field

Outputs

Control logic

Inputs

1998׃13 Morgan Kaufmann Publishers

Microprogramming

PCWritePCWriteCondIorD

MemtoRegPCSourceALUOpALUSrcBALUSrcARegWrite

AddrCtl

Outputs

Microcode memory

IRWrite

MemReadMemWrite

RegDst

Control unit

Input

Microprogram counter

Address select logic

Op[

5–

0]

Adder

1

Datapath

Instruction registeropcode field

BWrite

1998׃14 Morgan Kaufmann Publishers

Microinstruction

LabelALU

control SRC1 SRC2Register control Memory

PCWrite control Sequencing

Fetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch

Microinstruction formatField name Value Signals active Comment

Add ALUOp = 00 Cause the ALU to add.ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for

branches.Func code ALUOp = 10 Use the instruction's function code to determine ALU control.

SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.A ALUSrcA = 1 Register A is the first ALU input.B ALUSrcB = 00 Register B is the second ALU input.

SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input.Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input.Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input.Read Read two registers using the rs and rt fields of the IR as the register

numbers and putting the data into registers A and B.Write ALU RegWrite, Write a register using the rd field of the IR as the register number and

Register RegDst = 1, the contents of the ALUOut as the data.control MemtoReg = 0

Write MDR RegWrite, Write a register using the rt field of the IR as the register number andRegDst = 0, the contents of the MDR as the data.MemtoReg = 1

Read PC MemRead, Read memory using the PC as address; write result into IR (and lorD = 0 the MDR).

Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR.lorD = 1

Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as thelorD = 1 data.

ALU PCSource = 00 Write the output of the ALU into the PC.PCWrite

PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contentsPCWriteCond of the register ALUOut.

jump address PCSource = 10, Write the PC with the jump address from the instruction.PCWrite

Seq AddrCtl = 11 Choose the next microinstruction sequentially.Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.

Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.

1998׃16 Morgan Kaufmann Publishers

Interrupt and exception

Type of event From Where ? MIPS terminology

Interrupt External I/O device request

Invoke Operation system Internal Exception

From user program

Arithmetic Overflow Internal Exception

Using an undefined

Instruction Internal Exception

Either Exception or interrupt Hardware malfunctions

1998׃17 Morgan Kaufmann Publishers

Exception type Exception vector address (in hex)

Undefined instruction c0 00 00 00

Arithmetic Overflow c0 00 00 20

Cause register or Vectored interrupts

MIPS – Cause register

1998׃18 Morgan Kaufmann Publishers

Interrupt

Shiftleft 2

Memory

MemData

Writedata

Mux

0

1

Instruction[15– 11]

Mux

0

1

4

Instruction[15– 0]

Signextend

3216

Instruction[25– 21]

Instruction[20– 16]

Instruction[15– 0]

Instructionregister

ALUcontrol

ALUresult

ALUZero

Memorydata

register

A

B

IorD

MemRead

MemWrite

MemtoReg

PCWriteCond

PCWrite

IRWrite

Control

Outputs

Op[5– 0]

Instruction[31-26]

Instruction [5– 0]

Mux

0

2

Jumpaddress [31-0]Instruction [25– 0] 26 28

Shiftleft 2

PC [31-28]

1

Address

EPC

CO 00 00 00 3

Cause

ALUOp

ALUSrcB

ALUSrcA

RegDst

PCSource

RegWrite

EPCWriteIntCauseCauseWrite

1

0

1 Mux

0

3

2

Mux

0

1

Mux

0

1

PC

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

ALUOut