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A Frequency Synthesizer Using Two Different Delay Feedbacks

班級：積體所碩一 學生：林欣緯

指導教授：林志明 教授

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

23-26 May 2005 page(s): 2799 - 2802 Vol. 3

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Outline

Introduction Architecture Circuit Implementation Simulation Results Conclusion

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Introduction

The large dead zone induced by the PFD, it causes the phase error accumulation at the VCO output.

The jitter evoked by the inevitable 1/f and white noise of the circuits, it forces VCO to contribute phase noise toward the output.

The clock feedthrough and charge injection motivated by CP switches, it results in the abrupt vibrations on the VCO control line and their corresponding clock jitter even when the loop is locked.

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Two PFDs withseparate dead zones

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Conventional PLL architecture

second-order low-pass filter

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The proposed PLL architecturewith double PFDs scheme

tsIpIp

eIpIpIp ts

121

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The operations of the proposed PLL architecture

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The schematics of the delay cell

PMOS input differential pair

cross-coupled feedbacks

current source

diode-connected transistors

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The schematics of the ring oscillator

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The schematic of three-state PFD with delay buffers

discard the spurs

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Charge pump circuit & Switch

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The schematic of the TSPC divider

TSPCTrue Single Phase Clock1. simple of structure2. small dead zone

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Simulation results when Δt = 90ps

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Simulation results when Δt = 30ps

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Simulation results for the ring oscillator

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Transient responses of the PLLs

settling time < 22μs

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The chip layout

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Performace summary of the proposed PLL

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Conclusion A fully differential delay cell for the VCO is intr

oduced to achieve wide locking range and low-jitter performance.

Two PFDs are combined to provide a less dead zone with a new phase-detecting approach and a less settling time.

A tunable delay element is used to suppress the ripple on the VCO control line, and hence a more accurate output clock can be resulted.