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A Low Spur Fractional-N Frequency Synthesizer

Architecture

指導教授 : 林志明 教授學生 : 黃世一

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

23-26 May 2005 Page(s):2807 - 2810 Vol. 3

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Outline

Abstract Introduction Fractional spurs Blocking of the fractional spurs Simulation results Conclusions References

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Abstract New architecture of a fractional-N PLL

frequency synthesizer

Loop filter with a discrete time comb filter

Loop filter architecture can be efficiently implemented using switched capacitor techniques

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Introduction 1 Fractional-N PLL, Better phase noise perfo

rmance, faster lock and better spur levels

Advantages: larger loop bandwidth, better VCO phase noise suppression, faster lock time and higher PFD update frequencies

Fractional spurs and cycle slipping

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Introduction 2 Delta-sigma control in the feedback divider

Fractional spurs by the delta-sigma modulator to high frequencies.

Delta-sigma modulator can generate spurs

Pseudorandom sequences

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Introduction 3

Another way to suppress fractional spurs is to reduce the bandwidth of the PLL

Degradation of the noise performance, lock time and jitter

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Introduction 3 Extension of the conventional fractional-

N technique

A discrete-time loop filter with notches at spur frequencies

A low power frequency synthesizer design with low spur levels

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Fractional spurs

Fractional-N frequency synthesizers generate spurs at the output of VCO

M

KN

M

NKMNKN f

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ωs = 2πfs fs - frequency of a spur Vi - amplitude of the i-th harmonic ϕi - phase of the i-th harmonic

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ω0 = 2πf0

f0 - frequency of the free running oscillator VA - amplitude of oscillation Φ(t) - phase of the oscillator

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ωc = 2πfc = 2π(f0 + KVCOV0)

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Each harmonic at the control line of a VCO will generate an infinite number of spurs at multiple frequencies around the carrier frequency of the VCO

The magnitude of a spur depends on the Bessel functions and depends on the KVCO

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Blocking of the fractional spurs

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Simulation results

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VCO output spectrum of the conventional PLL (zoomed)

VCO output spectrum of the PLL with DTF (zoomed).

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Conclusion

Fractional-N frequency synthesizers with low fractional spurs

Discrete-time comb filter, switched capacitor techniques

Simulation results

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References Kratyuk, V.; Hanumolu, P.K.; Un-Ku Moon; Mayaram, K.;Ci

rcuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):2807 - 2810 Vol. 3 Digital Object Identifier 10.1109/ISCAS.2005.1465210

Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon and Kartikeya Mayaram

School of Electrical Engineering and Computer Science Oregon State University, Corvallis, Oregon 97331

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Thank You For Your Attention !