1

Lab7Design and

Implementation

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Design Example : Parity checker

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Computer to Spartan-6

USB Port

Spartan-6PC

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DIP SWITCHES & LEDs

DIP SWITCH

LED

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Power to Board

變壓

整流器AC 110V DC 5V

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Create a New Project

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Enter a Name and Location for the Project

1

2

3

檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名

8

Select Device Family, Package, Device and Speed Grade

1

2

9

Finish

1010

Create a New File

1.Right Click

2

1111

Create a New Module

1

2. Type “logic”

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Define I/O Port

1.Type x,y,z,f 2.Select I/O

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Finish

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Type

1.Type

2.Remember to save the file

Check Synthesize

2.Double Click

1.Double Click

16

Add Verilog Test Fixture

1.Right Click

23

4

5

檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名

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Finish

1 2

Test bench

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1

2.Remember to save the file

Generate Expected Simulation Result

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1

2. Double Click

20

Click Zoom Full

1.Run all2.Click

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Result f=x^y ^z

Enter the PlanAhead

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1

2.Double Click

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Pins Assign

User I/O FPGA Pin Signal

LED1 E13 f Sw1 D14 x Sw2 E12 y Sw3 F12 z

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Assign pins [1]

1

2

3.key in

4

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Assign pins [2]

3

1

2. key in

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Assign pins [3]

3

1

2. key in

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Assign pins [4]

3

1

2. key in

4. Save

It’s Generate by PlanAhead

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1.Double Click2.

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Run “Implement Design”

1

2. Double Click

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Select FPGA Start-Up Clock to JTAG Clock

1. Right Click

2

43

5

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Generate Bitstream File

Double Click

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Run “Configure Device”

Double Click

此時請務必將版子接上

Create a New Project on ISE iMPACT

33

1

2

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Select Boundary.. and Automatically…

2

1

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Select “logic.bit file”

1.Double click2

Press “ok”

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37

Right-click to select operation

21.Right Click

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Program Succeeded

Check the Result on spartan-6

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Check the Result on spartan-6

DIP SWITCH

LED

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Question and Answer

歷史人物中，誰跑最快 ?