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Role of Standards in TLM driven D&V Methodology

Umesh Sisodia, CircuitSutra(usisodia@circuitsutra.com)

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Objective

CircuitSutra: SoC Modeling ServicesEmbedded software services using Virtual Platforms

By the end of session you should:

Know about various standards in SoC modeling domain

Role of standards in TLM D&V

How does CircuitSutra’s expertise in SoC modeling standards fits with the Cadence tools to implement the TLM D&V

Q&A session after the presentation

Prize draw in the end. You can win a copy of the book ‘TLM driven design and verification methodology’

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Modeling StandardsModeling Language: SystemC

Full power of C / C++Structure (module, hierarchy, ports)Concurrency, Simulation timePrecision: Fixed point and bit accurate data types

Transaction level modeling (TLM)OSCI TLM2.0OSCI TLM1.0

Extending TLM2.0Bus specific protocols (AMBA, PLB, .. )Non memory map protocols (UART, USB, Ethernet, .. )

STARC TLM Guidelines

SystemC Synthesizable subset

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Benefits of StandardsEasy to integrate IP models from different sources

Models are independent of ESL / EDA tool environmentAny verilog code is supposed to work with EDA tool from any vendorSimilarly SystemC models should work with any ESL tool

(Necessary condition for SystemC to become a language of choice for design entry, and hence for raising the abstraction of chip design)

Feasible to mix tools and expertise from different vendors in the TLM D&V Flow

Virtual platform environment: ARM Fast Model, OVP, ..HLS: Cadence C-to-SVerification: Calypto, Cadence, SystemC Modeling Services (CircuitSutra)

Different parts of a model can be sourced from different vendorThe Untimed / Loosely timed model from one vendor can be combined with bus specific transactor from another vendor

Allows the Code re-use across different applications / architectures

Easy to get engineering professionals

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Components of TLM D&V flowCadence is advocating Standards based TLM D&V

methodology

Virtual Platform of a SoCTLM2.0 wrapper created over fast processor modelPeripheral models created using SystemC & TLM2.0Computation is separate from communication as per STARC TL Guidelines

Synthesizable models for HLSFunctionality implemented using Synthesizable SystemC subsetComputation is separate from communication as per STARC TL GuidelinesTLM Interfaces: TLM1.0 + GP (Borrowed from TLM2.0) = Cadence TLM+GPBus specific Transactors (TLM+GP interface on one end, bus specific signal level interface on other end)

VerificationVerification of TLM Models (TLM2.0, HLS Ready TLM, HLS Ready Signal)Verification of RTL BlocksAccelara UVM can be effectively used to verifiy across abstraction levelsHW / SW Coverification through Incisive Software Extensions (ISX)

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Virtual Platform of SoCAllows the embeded software development without FPGA board

Chip design and eSW can proceed in parallel. Reduces TTM for SoC

Advanced tools are being available for better eSW development and debugging

VP Methodology

A typical virtual platform project

TLM2.0 Sockets tlm_usb Socket New SystemC models added Existing components of ARMIntegratorCP platform

Ethernet driver of host PC

USB driver of host PC

tlm_ethernet Socket tlm_uart Socket

DecodeBus (m_bus)

ARM CPU

DMA

PIC

IRQ

FIQ

TLM Memory UART

Uart backend

Driving the console

Other Slave peripherals of ARM IntegratorCP Platform

USB Backend

USB Controller

Ethernet Backend

EthernetController

ARMIntegratorCP Board

Virtual Platform EnvironmentARM Fast Models, OVP, QEMU, ..

Any other vendor ..

Models for Virtual Platforms

Traffic Generator

EthernetController

TLM 2.0

Model

Backend

TLM-EthernetExtends TLM2.0

Virtual Network

EthernetController

EthernetController

Backend

Ethernet Driver(Host PC)

Accessing host interfaces in VP

EthernetController

TLM 2.0

TLM-EthernetExtends TLM2.0

Backend

Ethernet Driver(Host PC)

TLM 2.0

TLM-USBExtends TLM2.0

USB HostController

Backend

USB Driver(Host PC)

VP

Guest OS

Device Driver

ApplicationGuest OSAndroid /Symbian Device

Driver

Application

Host OSHost OSWindows 7 /Linux

• Enables the virtual platform to interface with real world devices

• Provides real time verification environment

• Any hardware interface of host PC can be supported• Ethernet• WLAN• USB• Printer• Camera• Audio(Speaker, Mic)• ..

Model Architecture

Wrapper

Wrapper

Core (Functional model)

Communication

Cycle Accurate ModelNon blocking interface (AT)

TLM2.0 extended for Bus specific protocol

TLM2.0 Compliant ModelBlocking Interface (LT / UT)

Non blocking interface (AT)

TLM2.0 Socket

Adaptor (PV – CA)

CA TLM Socket Pin level interface

Adaptor (PV – BS)

Bus Signal InterfaceCan connect to the RTL

Pin interface is specific to a bus

Pin level interface

Adaptor (PV – BS)

AXI

Pin level interface

Adaptor (PV – BS)

PLB

Pin level interface

Adaptor (PV – BS)

OCP

STARC TL Guidelines: Computation is separate from communication

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High Level Synthesis

HLS ToolC-to-Silicon Compiler

RTL (Verilog)

TLM modelSystemC, C, C++

SystemC: Language of Design entry

Designers focus on implementing the functionality

HLS Tool: Generate optimized RTL

RTL

Power

RTL

Area

RTL

Performance

Optimized For: Constraints

Constraints

RTL

90 nm

RTL

45 nm

RTL

22 nm

Optimized For: Process Node

RTL

FPGAAltera

RTL

FPGAXilinx

RTL

ASIC

Optimized For: Underlying FabricOptimized For: Bus Architecture

RTL

AXI

RTL

PLB

RTL

OCP

TLM-GP Interfaces

Transactors

Benefits

• Only one version of design• Less amount of code• Fewer bugs

Function is seperated from implementationRaises the abstraction of Chip DesignSystemC may replace Verilog

CircuitSutra have good expertise in Synthesizable SystemC subset

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Models for VP & HLS

Virtual Platform HLS

• Simulation Speed

• Can use all the constructs of SystemC

• TLM2.0 for bus interfaces

• TLM interfaces for non memory mapped connections

• Synthesizability

• Only Synthesizable subset of SystemC should be used

• TLM1.0, TLM+GP (Cadence)

• Pin level interfaces for non memory mapped connections

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Models for VP & HLS

Virtual Platform HLS

Core (SystemC)

Communication(TLM2.0)

Core (Synthesizable SystemC)

CommunicationTLM+GP

HLS Ready TLM

TRANSACTOR

HLS Ready Signal

TLM-UART Sout

Sin

Modem

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Verification from TLM to RTL

New verification methodology required for new design

methodologyEffortlessly reuse verification IP from TLM to RTL closureThe proven RTL verification concepts (UVM, MDV etc.. ) can be usedThe UVC can be extended to verify

SystemC based TLM designs Complete System (HW & SW)

Incisive Software extensions (ISX) enables the verification environment to connect to software using Generic Software adaptor (GSA)

Reduce the verification effortsThe functionality of the computation block should be verified at the highest abstraction level

Fewer bugsFaster simulationEasier to identify, understand and fix the bugs

The interfaces, protocol correctness can be verified at HLS ready levelDetailed timing can be verified at RTL level

HW/SW Co-Verification

Hardware Software

SoC (VP)

BUS UVC

Peripheral UVC

Peripheral UVC

Auto

matic S

yste

m sce

nario

genera

tor

UV

M In

frastru

cture

Software UVC

ISX

Incisive Software Extensions (ISX)

• Extends system verification environment to include software

• MDV can be applied to verify the low level hardware dependent software

CircuitSutra can integrate the VP with ISX

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Standardization required ..

TLM modeling standard for non memory mapped communication protocol

USBEthernetWLANZigbee..

Standard definition of abstraction levels for different use casesPV, AV, VVOCP-IP: TL4, TL3, TL2, TL1STARC TL Guidelines:

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System Realization Alliance

Advocating Standards based TLM D&V methodology

Standards based SoC modeling services

Can help mutual customers to quickly get started with TLM D&V

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CircuitSutra OfferingsCreate virtual platform of System on Chip (SoC)

Integrate the Virtual platform with Cadence ISX

Synthesizable models for High Level Synthesis (HLS)Create models as per SystemC Synthesizable subsetSynthesize using C-to-Silicon compiler

SystemC models for RTL verification or HW / SW coverification

Bus specific Adaptors / TransactorsOCP-IPAMBA Kit

Embedded software services using virtual platforms

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