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Neuromorphic Engineering IIInstructors

Tobi DelbruckGiacomo Indiveri

Shih-Chii LiuAss ist ants

Raphael Berner

Saber Moradi

avlsi.ini.uzh.ch/classwiki

Approx. Course schedule (see web)1. Design flow, SPICE, DC simulation

2. Transistor EKV model, Transient simulations

3. Process technology, layout (LEDIT)

4. Design rules, Design rule checking

5. Hierarchical schematics, LVS

6. Peripheral circuits (pads), work on project

7. Project introduction, discuss project

8. Device mismatch. Elaborate project.

9. Work on project.

10. Design review of layouts.

11. Bias generators, work on project

12. Final project presentations

Grading policy

There are 6 lab exercises and the project. Youmust do at least 5 of the labs.

Project starts around Apr 13. You will have 7 weeks to work on the project.

You must complete your part of the project aspart of the whole team.

Your grade will depend on How well you have learned the technology

Your work on the project

Oral exam: 20-30 minutes.

8 wafer

6000/wafer

$1200/wafer

Die cost $0.20

Testing $0.20

Package $0.10

Plastic lens $0.50

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Analog Chip CAD design tools

S-EditSchematic editor T-SpiceCircuit simulator

L-EditLayout editor

DRCDesign rule checker

ExtractNetlist extractor

LVSLayout vs. Schematic

Design Verification

Mask layout

SPICE

Stands forSimulation Program for Integrated Circuit Emulation

Developed in 1960s at UC Berkeley, continuallyevolved since then

Main industry workhorse (HSPICE, SPECTRE)

A SPICE simulation of aninverter

time

voltage

Vin Vout

Start with file describing circuit and simulationcommands

.options reltol=1e-5 abstol=1e-15 $ set some options

.include ml5_12ami.md $include transistor models

vdd Vdd gnd 5 $ your 5 volt power supply

vin in gnd pwl( 0 0 5u 5 10u 0) $your input signal

.include inverter.sp $include your circuit

.tran/powerup 1u 10u $transient analysis, 1us max step for 10us

.print tran in out $ say what to print

SPICE simulation

Commands Elements

A SPICE netlist

MP_1 out i n Vdd Vdd pmos L=10u W=10u

MN_1 out i n Gnd Gnd nmos L=10u W=10u

in out

Vdd

Gnd

MP_1

MN_1

D G S B model W/L

MOS fet

SPICE output* T-Spi ce 3. 14 Si mul ati on Thu Mar 29 11:24: 41 20010i nvert er. sp (CAZM)

* Command l i ne: tspice -o inverter.out 0inverter.sp

* Host: z Operati ng System: SunOS 5. 6

* Devi ce and node count s:

* MOSFETs - 2 MOSFET geometri es - 2

* Total nodes - 5

TRANSIENT ANALYSIS

Ti me v( i n) v( out)

0. 0000e+00 0. 0000e+00 0. 0000e+00

3. 9710e-10 1. 5431e-06 1. 5351e-06

3. 3925e-09 8. 7563e-04 - 5. 6406e-01

4. 2761e-09 1. 6560e-03 - 6. 8245e-01

5. 2559e-09 2. 8390e-03 - 6. 3864e-01

Use matlab script readtspice to read this file and plot

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Other SPICEelements and commands

Capacitor Cx n1 n2

Resistor Rx n1 n2

Current source I x n1 n2

Bipolar transistor Qx E B C

DC operating point

. op

DC sweep

. dc V1 0 5 . 01

AC analysis

. ac 1 5 oct

Look on the Tanner cheat sheet for more

How does SPICE work?

Not very well! Dont ever believe itcompletely models REALITY .

Problems

Very compute intensive

Doesnt model transistor mismatch

Doesnt model Early effects well

Doesnt model distributed c haracteristics like

resistance and capacitance

Makes you lazy about thinking

Review on MOS transistors

sV

gV

dV

bV

sV

gV

dV

bV

nFET pFET

Regimes of operation for a FET(dependent on Vgs)

Subthreshold (Weak inversion) regime

Current flows through diffusion

Cutoff

Above threshold (Strong inversion) regime

Current flows through drift

nFet curve: I vs Vgs

VT (Threshold voltage)

Threshold voltage is the voltage where the measured I is

half of the I computed from the exponential equation.

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Equation for subthreshold nFET

TsTg UVUV

f eeII//

0

= TdTg UVUV

r eeII

//

0

=

rf

UVUVUV

II

eeeII TdTsTg

=

= )( ///

0

currentreverseI

currentforwardI

r

f

=

=

rI

sV

gV

dV

fI

Regimes of subthreshold operation(dependence on Vds)

Triode/Linear Region

Saturation Region

)1(/)(/)(

0TsdTsg UVVUVV eeII

=

Tsg UVV

f eIII/)(

0

==

nFET curve: I vs Vds

Saturationregion

Ohmicregion

mVqkT 1004

nFet curve: I vs Vgs

VT (Threshold voltage)

Threshold voltage is the voltage where the measured I ishalf of the I computed from the exponential equation.

Above threshold nFET equations

( ) ( )[ ]

rf

dTgsTg

II

VVVVVVI

=

=2

0

2

0 )()(2

L

WCox =

rI

sV

gV

dV

fI

Regimes of above threshold operation(dependence on Vds)

Triode/Linear Region

Saturation Region

))(( sdTgox VVVVL

WCI =

))(( sdTg VVVVI =

[ ]2)(2

Tg VVI =

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Above threshold nFET curve: I vs Vds Enz-Krummenacher-Vittoz (EKV) model

( )( )

( )( )( )( )

0

0

/ 22 2

/ 22

2 log 1

log 1

G T S T

G T D T

V V V U ox

T

V V V U

CWI U e

L

e

= + +

Model is continuous from subthreshold to abovethreshold.

Valid in both ohmic and saturation regions

Log () function smoothly interpolates between expand squaring function

A single pFET has forward andreverse currents

Ifand Ir are independent

Each depends only on voltage on its terminal and gate(This analysis only valid for subthreshold)

g

s d

If

Ir

rf

UVVUVV

UVUVUV

II

eeI

eeeIITdgTsg

TdTsTg

==

=++

)(

)(/)(/)(

0

///

0

Photoreceptor circuit

Resistive element

( )( ) ( )( )

( ) ( )( )

( )2/sinh2 0

2/2/

0

2/2/

0

///

021

VeeI

eeeeI

eeeI

eeeII

VV

p

VVVV

p

VVVVV

p

UVUVUV

p

bp

bp

bp

TTTbp

=

=

=

=

+

1V

bV

2V )(

2/)(

21

21

VVV

VVV

=

+=

Resistive element

( ) bn VVVnb eeII

+= 2/0

1V

bV

2V bV

1V

mV

bI

( )

( ) ( )2/sinh2

2/sinh2

2/1

0

0

0

VeeI

II

VeeII

VV

k

n

bp

VV

p

pnpn

p

bp

=

=

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