2 December 2003 – ITRS Public Conference Hsin Chu, Taiwan Design ITWG ITRS-2003 December 2, 2003 Taiwan Japan: Ichiro Yamamoto, Tamotsu Hiwatashi Taiwan:

2 December 2003 – ITRS Public Conference — Hsin Chu, Taiwan

Design ITWGITRS-2003

December 2, 2003 Taiwan

Japan: Ichiro Yamamoto, Tamotsu HiwatashiTaiwan: Chung-Ping ChenUSA: Andrew Kahng(Europe: Ralf Brederlow)


Design ITWG Contributions to ITRS• System Drivers Chapter

– Defines IC products that drive manufacturing and design technologies– ORTCs + System Drivers = framework for technology requirements– SoC-centric organization, with three “fabrics”

• Processor

• Mixed-Signal

• Memory

• Design Chapter– Cross-cutting challenges: (1) productivity, (2) power, (3) design

for manufacturing, (4) interference, (5) error-tolerance– Design cost and productivity models– Technology areas: (1) design process, (2) system-level design, (3)

logical/physical/circuit design, (4) design verification, (5) design test

• ORTC support– Frequency, Power, Density models


Big Picture• Message: Cost of Design threatens continuation of

the semiconductor roadmap– Design cost model– Challenges are now Crises : software, verification, analog, cost...

• Strengthen bridge from semiconductors to applications, software, architectures– Hertz and bits are not the same as efficiency and utility– System Drivers chapter, with productivity and power foci

• Strengthen bridges among ITRS technologies– “Shared red bricks” can be solved (or, worked-around) more

cost-effectively variability, leakage, low-k, …

– “Manufacturing Integration” cross-cutting challenge– “Living ITRS” framework to promote consistency validation


SYSTEM DRIVERS CHAPTER


System Drivers Chapter Outline 20012001 2003

• ScopeScope

– High-volume custom High-volume custom (MPU, memory), AMS, (MPU, memory), AMS, SOCSOC

– Market DriversMarket Drivers

• MPUMPU• Mixed-SignalMixed-Signal• SoCSoC

– Multi-TechnologyMulti-Technology– High-PerformanceHigh-Performance– Low-Cost, Low-PowerLow-Cost, Low-Power– Trends (Power and Trends (Power and

Design Productivity, Design Productivity, based on LP-PDA model)based on LP-PDA model)

• Market Drivers• SoC scope and taxonomy

– Multi-Technology, High-Performance, Cost-Driven

• SoC trends– LP-PDA and Power– Cost and SiP integration

• Component Fabrics– MPU– Mixed-Signal– Memory


System Drivers Chapter Changes• Rewriting and reorganization SOC-centric structure

– Key challenges: productivity, power, heterogeneous integration, test

• SOC LP PDA model– Table of Performance and die size, Device and memory composition– Battery technology– Mixed-signal content

• SOC LP Device Table reconciliation• Embedded memory section

Planned for 2004-2005:• SOC impact of cost drivers

– SIP Multi-Technology integration alternatives– Low metal/mask count

• Embedded DSP, MCU• Off-chip signaling bandwidth


SoC Taxonomy

N e tw o rk P roce sso rs H igh -en d G am ing D e v ices

H igh -P e rfo rm an ce(H P )

W ire le ss D e v ices P D A

L o w -P o w er(LP )

S oC

Component Fabrics: Processor, Memory, Mixed-Signal


Req’d Performance for Multi-Media ProcessingGOPS

0.01 0.1 1 10VideoVideo

AudioAudioVoiceVoice

CommunicationCommunicationRecognitionRecognition

GraphicsGraphics

FAXModem

2D Graphics

3D Graphics

MPEGDolby-AC3

JPEG

MPEG1Extraction

MPEG2 ExtractionMP/ML MP/HLCompression

VoIP Modem

Word Recognition

Sentence Translation

GOPS: Giga Operations Per Second

100

Voice Auto Translation

10Mpps 100Mpps

MPEG4

Face RecognitionVoice Print Recognition

SW Defined Radio

Moving Picture Recognition


ITRS SoC Low-Power PDA Model Study

• Reference Design: personal digital assistant (PDA)

• Composed of CPU, DSP, peripheral I/O, and memory


Example SoC for PDA0.18um / 400MHz / 470mW (typical)

CPU

I-cache32KB

D-cache32KB

I2C

FICP

USB

MMC

UART AC97

I2S

OST

GPIO

SSP

PWM RTC

DMA controller

LCDCnt.

MEMCnt.

PWR CPG

SDRAM64MB

Flash32MB

LCDPeripheral Area 4 – 48MHz

Data Transfer Area

100MHz

Processor Area

Max 400MHz

MM Application MP3 JPEG Simple Moving Picture

6.5MTrs.

Available Time 6-10Hr

SpecificationUSB

MMC

KEY

Sound


PDA Model Characteristics

Process Technology (nm) 130 90 65 45 32 22Operation Voltage (V) 1.2 1 0.8 0.6 0.5 0.4Clock Frequency (MHz) 150 300 450 600 900 1200Application Real Time Video Codec Real Time Interpretation (MAX performance required) (MPEG4/CIF)Application Web Browser TV Telephone (1:1) TV Telephone (>3:1)(Others) Electric Mailer Voice Recognition (Input) Voice Recognition (Operation)

Scheduler Authentication (Crypto Engine)Processing Performance (GOPS) 0.3 2 14 77 461 2458Parallelism Factor 1 4 4 4 4 4Communication Speed (Kbps) 64 384 2304 13824 82944 497664Power Consumption (MOPS/mW) 3 20 140 770 4160 24580Peak Power Consumption (mW)(Requirement)

Battery Wh/Kg 120 200 400

2 2 2Standby power consumption (mW) (Requirement)

2 2 2

100 100 100

Still Image Processing

100 100 100


LSTP Power Dissipation

0.0

0.4

0.8

1.2

1.6

2001 2004 2007 2010 2013 2016

Year

Pow

er (W

)

- Dynamic Power LSTP (W)

- Static Power LSTP (W)

- Power for LSTP Bottom-Up (W)


LOP Power Dissipation

0.00

0.50

1.00

1.50

2.00

2.50

2001 2004 2007 2010 2013 2016

Year

Po

we

r (W

)

- Dynamic Power LOP (W)

- Static Power LOP (W)

- Power for LOP Bottom-Up (W)


0%

20%

40%

60%

80%

100%

2001 2004 2007 2010 2013 2016Year

Pe

rce

nta

ge

of

Are

a (

%)

Logic Area Contribution (%) LOP

Logic Area Contribution (%) LSTP

Total Memory Area (%) LOP

Total Memory Area (%) LSTP

Die Size = 1cm2

Power-Constrained Chip Composition

Memory

Logic


Technology Needs (e.g., Design)

• Multi-everything optimization – Mix of HP, LOP, LSTP devices in same core– Design tools must simultaneously optimize use of Vdd, Vt,

Tox knobs as well as device sizing

• Body bias control, Lgate bias, …• Dynamic voltage, frequency scaling• Clock gating• Sleep modes• Operating system and application control• Other technology area needs: PIDS, A&P, Test…


Analog / Mixed-Signal Update

• Adapted to analog & RF technologies for wireless communications working group within PIDS – System Drivers Chapter text aligned with the new PIDS subchapter

• Drivers and Figures of Merit– ADC: stays as predicted

– LNA: stronger performance improvement than expected in 2001

– VCO: FoM is adjusted to technology (some changes in text)• Numbers remain relatively similar

• Benefits from certain technology measures as expected, but VCO improvement versus technology remains weak part of RF circuits

– PA: stays as predicted• Less CMOS-centric; some enhancements occur when looking at SiP


Embedded Memory

• SRAM, Flash, DRAM technology parameters– Cell size, additional masks, area efficiency– Access time, power active/standby, refresh, lifetime, SEU

• Figure of Merit for memory:– 1/ (cell size * area efficiency * mask-count factor *

effective power (static or dynamic) * access time (R or RW))

• Define Drivers and their needs– Granularity and hierarchy– Volatile/non-volatile storage– Code (size) vs. data (size voice, image, …)– Bandwidth vs. storage trade-off– Error correction codes, testability, yield


DESIGN CHAPTER


Design Chapter Changes

• Canonical design flow context, design system architecture and design process

• Design cost model refinement• Standalone analog CAD, circuits, SOI content• Soft-error (including logic)• Rewriting and reorganization• Interactions with other ITWGs

– Ground rules (poly half-pitch, contacted M1 pitch, …) impact on layout density

– Benefits of, and lower bounds for, technology improvements (dielectric permittivity, CD variability, …)

– Off-chip signaling roadmap– High-performance (MPU) system power requirements


Design Process• Merged Design Process and Methodology Precepts• Challenges organized around 5 Key Trends

– Tight Coupling – Design for Manufacture – Increasing Level of Abstraction– Increasing Level of Automation– Early Verification

• New Figure to show evolution and trends– Based on STRJ-WG1 Canonical Flow– Different methodologies or applications would have variant flows– Show implied evolution of design system architecture

• New Table to summarize challenges and strategies


Canonical Design Flow (STRJ-WG1)

• Provides context for detailed technology discussions• Also serves as grounding for design cost analysis• Required Design Technology innovations

– RTL synthesis• = synthesis technology that creates RT-level models from

architecture models

– HW/SW co-synthesis• = synthesis technology that creates architecture models from

behavior models• I.e., outputs architecture models for HW and source codes for SW


HW Specification SW Specification

Behavior Models & Constraints

RTL Synthesis

RTL Models & Constraints

Logical & Physical Design

Mask Data

Software Development

Modeling Verification

Micro Architecture Design(Block Partition)

System Requirement Analysis

System Requirement Specification

System Architecture Design

System Function Design Full/Semi-Automated

Handcraft

Files, Documents

Full/Semi-Automated

Handcraft

Files, Documents

Hardware Development Hardware Development

Design FlowRTL Synthesis


Design FlowHW/SW Co-Synthesis

System Requirement Analysis

System Requirement Specification

System Behavior Model ,Design Constraint

HW/SW Co-Synthesis

Behavior Models & Constraints

Logic design & Physical Design

SW Source Code

RTL Synthesis

RTL Models & Constraints

Modeling Verification

System Function DesignFull/Semi-Automated

Handcraft

Files, Documents

Full/Semi-Automated

Handcraft

Files, Documents

Hardware Development Hardware Development

Software Development

Mask Data


Revised ITRS Design Cost Model• Description of model

– Rewritten to further clarify model, data, and conclusions– Introduced footnotes to explain geographical issues

– Remains as Appendix in 2003 Design Chapter • Model itself

– Introduced cost model tree to capture key components– Included software design in tree– Accomodates canonical design flows

• Data– Performed substantial sanity checks successful overall– Future versions will emphasize software, large-block reuse – Calibration across regions (salary, productivity data) due to market differences

should be resolved in future versions


Cost Model Tree

Product cost

Development R&D

Manufacturing

Marketing, sales

General, administrative

Maintenance, service

Financial

Labor

Infrastructure

Chip/circuit/physical design

Chip integration

Verification, test

SW development

EDA licenses

EDA integration & support

Test chips

Depreciation/amortization

design/development costsother costs

Key:


Productivity Evolution

+5,000%TOTAL

Level above RTL, including both HW and SW design. It consists of a behavioral (where the system function has not been partitioned) and an architectural level (where HW and SW are identified and handed off to design teams).

SW dev’ment

Verification

200K+60%2005Electronic system level (ESL) methodology

RTL verification tool (“cockpit”) which takes an ES-level description and partitions it into verifiable blocks, then executes verification tools on the block while tracking and reporting code coverage.

SW dev’ment

Verification

125K+37.5%2003Intelligent testbench

Tightly integrated tool set that goes from RTL synthesis to GDS II through IC place and route.

Chip/circuit/PD

Integration

EDA support

91K+63.6%2001IC implementation suite

Blocks from 75,000 – 1M gates.Chip/circuit/PD

Integration

Verification

56K+38.9%1999Reuse – large blocks

Blocks from 2,500 to 74,999 gates.Circuit/PD

Verification

40K+340%1997Reuse – small blocks

Engineer than can pursue all required tasks to complete a design block, from RTL to GDSII.

Chip/circuit/PD

Verification

9.09K+63.6%1995Tall-thin engineer

Automated block placement and routing.PD

Integration

5.55K +38.9%1993In-house place& route

4K1990None

Description of improvementCost component affected

Productivity

(gates/

designer-yr)

Productivity delta

YearDT Improvement

+5,000%TOTAL

Level above RTL, including both HW and SW design. It consists of a behavioral (where the system function has not been partitioned) and an architectural level (where HW and SW are identified and handed off to design teams).

SW dev’ment

Verification

200K+60%2005Electronic system level (ESL) methodology

RTL verification tool (“cockpit”) which takes an ES-level description and partitions it into verifiable blocks, then executes verification tools on the block while tracking and reporting code coverage.

SW dev’ment

Verification

125K+37.5%2003Intelligent testbench

Tightly integrated tool set that goes from RTL synthesis to GDS II through IC place and route.

Chip/circuit/PD

Integration

EDA support

91K+63.6%2001IC implementation suite

Blocks from 75,000 – 1M gates.Chip/circuit/PD

Integration

Verification

56K+38.9%1999Reuse – large blocks

Blocks from 2,500 to 74,999 gates.Circuit/PD

Verification

40K+340%1997Reuse – small blocks

Engineer than can pursue all required tasks to complete a design block, from RTL to GDSII.

Chip/circuit/PD

Verification

9.09K+63.6%1995Tall-thin engineer

Automated block placement and routing.PD

Integration

5.55K +38.9%1993In-house place& route

4K1990None

Description of improvementCost component affected

Productivity

(gates/

designer-yr)

Productivity delta

YearDT Improvement


CAD for Analog / Mixed-Signal / RFTo close the productivity gap, must focus on:• Description languages (analog and digital, electrical and non-electrical)• System performance evaluation and design-space exploration• Circuit synthesis and sizing• Schematic validation• Design for manufacturing• Analog/RF layout synthesis• Interconnect and substrate extraction, modeling, simulation• Power• Analog IP and reuse• Top-down and bottom-up methodologies


Expected Breakthroughs in AMS CAD

2002/03 2004/05 2006/07

Specification, validation Mixed-signal description languages

Multi-language support; full system simulation

Complete specification-driven design flow

Architectural design Algorithm-oriented design

Language-based performance evaluation

Synthesizable AMS description

Mixed A/D and RF physical design

Procedural layout generation

Design centering, performance estimation

Constraint-driven synthesis; behavior to layout

Parasitic extraction, modeling, simulation

EMI simulation 2D / 3D modeling; order reduction (lines and fields)

Fault-tolerant circuit architectures; robustness

Test preparation AMS fault simulation

BIST for AMS circuits

Generally accepted fault models for all design levels ATPG


SUMMARY


Summary• System Drivers Chapter

– New material• Embedded memory

– Improvements to existing material• “SOC-centric” chapter reorganization• SOC Low-Power PDA driver model• MPU, Mixed-Signal discussions

• Design Chapter– New material

• Analog section• Canonical design flow context

– Improvements to existing material• Design cost model• Design process and design system architecture


THANK YOU !


2003 ITRS Low-Power PDA Model• (R. Saleh, K. Uchiyama, I. Yamamoto)• Goals

– Validate existing models and modify results based on any new data

– Modify ITRS System Drivers text accordingly


2003 ITRS Low-Power PDA Model• (R. Saleh, K. Uchiyama, I. Yamamoto)• Goals

– Validate existing models and modify results based on any new data– Modify ITRS System Drivers text accordingly

• Outcomes– Keep power-related projections– Remove productivity-related projections– Table 1: Reduction of GOPS values, inclusion of battery technology

advances decided to stay with original version– Gate leakage, mixed-signal content, eSRAM-eDRAM transition point

also left unchanged

• Many refinements, but conclusions do not change


Major Cost Components

____________________________Labor Unit Cost X Design ComplexityDesign Labor Cost =

Designer Productivity

__________________________EDA Unit Cost X Design ComplexityEDA Infrastructure Cost =

Designer Productivity


Summary• System Drivers Chapter

– New material• Embedded memory

– Improvements to existing material• “SOC-centric” chapter reorganization• SOC Low-Power PDA driver model• MPU, Mixed-Signal discussions

• Design Chapter– New material

• Analog section• Canonical design flow context

– Improvements to existing material• Design cost model• Design process and design system architecture


2003 ITRS Low-Power PDA Model• Goals

– Validate existing models and modify results based on any new data– Modify ITRS System Drivers text accordingly

• Outcomes– Keep power-related projections– Remove productivity-related projections– Reduction of GOPS values, inclusion of battery technology

advances decided to stay with original version– Gate leakage, mixed-signal content, eSRAM-eDRAM transition point

also left unchanged

• Many refinements, but conclusions do not change