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Mastering the DMA and IOMMUAPIs

Embedded Linux Conference 2014San Jose

Laurent Pinchart

[email protected]

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!" #$ !"

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(he topic )e )ill focus on is ho) to

mana&e s*stem memor* used for!".

(his presentation )ill not discussthe !" en&ine "P+, nor )ill itaddress ho) to control !"

operations from a de-ice point of-ie).

DMA vs. DMA

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7/102Simple Case

CPUCore

Device

Memory

MemoryController

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9/102Write Buer

CPUCore

Device

Memory

MemoryController

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10/102Write Buer

CPUCore

Device

Memory

MemoryController

1 /

2

%1' CP )rites to memor*%2' CP flushes its )rite buffers%/' e-ice reads from memor*

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11/102!" Cache

CPUCore

Device

Memory

MemoryController

!"Cache

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12/102!" Cache

CPUCore

Device

Memory

MemoryController

!"Cache

%1' CP )rites to memor*%2' CP cleans L1 cache%/' e-ice reads from memor*

1

2

/

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13/102!# Cache

CPUCore

Device

Memory

MemoryController

!"Cache

CPUCore

!"Cache

!# Cache

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14/102!# Cache

CPUCore

Device

Memory

MemoryController

!"Cache

CPUCore

!"Cache

!# Cache

%1' CP )rites to memor*%2' CP cleans L1 cache%/' CP cleans L2 cache%4' e-ice reads from memor*

1

2

/

4

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CPUCore

Device

Memory

MemoryController!"

Cache

CPUCore

!"Cache

!# Cache

Ca

cheCoherent

Interconnect

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%1' CP )rites to memor*%2' e-ice reads from memor*

CPUCore

Device

Memory

MemoryController!"

Cache

CPUCore

!"Cache

!# Cache

Ca

cheCoherent

Interconnect

1

2

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IOMMU

CPUCore

Device

Memory

MemoryController!"

Cache

CPUCore

!"Cache

!# Cache

Ca

cheCoherent

Interconnect

IOMMU

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IOMMU

CPUCore

Device

Memory

MemoryController!"

Cache

CPUCore

!"Cache

!# Cache

Ca

cheCoherent

Interconnect

IOMMU

%1' CP )rites to memor*%2' CP pro&rams the +!!%/' e-ice reads from memor*

1

2

/

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$ven More Comple%

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$ven More Comple%

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!emor*!appin&s

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ull* Coherent

Coherent %or consistent' memor* is memor* for )hich a )rite b* either thede-ice or the processor can immediatel* be read b* the processor or de-ice)ithout ha-in& to )orr* about cachin& effects.

Consistent memor* can be expensi-e on some platforms, and the minimumallocation len&th ma* be as bi& as a pa&e.

Memory Mapping &ypes

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rite Combinin&

rites to the mappin& ma* be buffered to impro-e performance. 3ou need tomae sure to flush the processor5s )rite buffers before tellin& de-ices to readthat memor*. (his memor* t*pe is t*picall* used for %but not restricted to'&raphics memor*.


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eal* rdered

6eads and )rites to the mappin& ma* be )eal* ordered, that is that readsand )rites ma* pass each other. 7ot all architectures support non8cached)eal* ordered mappin&s.


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7on8Coherent

(his memor* mappin& t*pe permits speculati-e reads, mer&in& of accessesand %if interrupted b* an exception' repeatin& of )rites )ithout side effects."ccesses to non8coherent memor* can al)a*s be buffered, and in mostsituations the* are also cached %but the* can be confi&ured to be uncached'.(here is no implicit orderin& of non8coherent memor* accesses. hen notexplicitl* restricted, the onl* limit to ho) out8of8order non8dependent accessescan be is the processor5s abilit* to hold multiple li-e transactions.

hen usin& non8coherent memor* mappin&s *ou are &uaranteein& to theplatform that *ou ha-e all the correct and necessar* s*nc points for thismemor* in the dri-er.


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Cache!ana&ement

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#include

Cache Management API

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#include

#include

Cache Management API

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Cache mana&ement operations are

architecture and de-ice specific.

(o remain portable, de-ice dri-ers

must not use the cache handlin&"P+ directl*.

Conclusion

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!" !appin&"P+

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"llocate memor* suitable for

!" operations !ap !" memor* to de-ices !ap !" memor* to userspace

S*nchroni9e memor* bet)eenCP and de-ice domains

DMA Mapping API

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#include

DMA Mapping API

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linux/dma-mapping.h linux/dma-attrs.h linux/dma-direction.h linux/scatterlist.h#ifdef CONFIG_HAS_!A

asm/dma-mapping.h#else asm-generic/dma-mapping-"ro#en.h#endif

DMA Mapping API

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linux/dma-mapping.h linux/dma-attrs.h linux/dma-direction.h linux/scatterlist.h arch/arm/include/asm/dma-mapping.h

asm-generic/dma-mapping-common.h asm-generic/dma-coherent.h

DMA Mapping API 'A(M)

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!" Coherent!appin&

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/* asm-generic/dma-mapping.h %/

void *dma_alloc_coherent(struct device *dev si!e"t si!e

dma"addr"t *dma"handle gf"t flag$%

(his routine allocates a re&ion of @si9e b*tes of coherent memor*. +t alsoreturns a @dma:handle )hich ma* be cast to an unsi&ned inte&er the same)idth as the bus and used as the de-ice address base of the re&ion.

6eturns; a pointer to the allocated re&ion %in the processor5s -irtual addressspace' or 7LL if the allocation failed.

7ote; coherent memor* can be expensi-e on some platforms, and theminimum allocation len&th ma* be as bi& as a pa&e, so *ou should

consolidate *our re

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voiddma_free_coherent(struct device *dev si!e"t si!e

void *cu"addr dma"addr"t dma"handle$%

ree memor* pre-iousl* allocated b* dma:free:coherent%'. nlie )ith CPmemor* allocators, callin& this function )ith a 7LL cpu:addr is not safe.

Coherent Allocation

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void *dma_alloc_attrs(struct device *dev si!e"t si!e

dma"addr"t *dma"handle gf"t flag struct dma"attrs *attrs$%

voiddma_free_attrs(struct device *dev si!e"t si!e void *cu"addr dma"addr"t dma"handle

struct dma"attrs *attrs$%

(hose t)o functions extend the coherent memor* allocation "P+ b* allo)in&the caller to specif* attributes for the allocated memor*. hen @attrs is 7LLthe beha-iour is identical to the dma:=:coherent%' functions.

Attri*ute+Based Allocation

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!":"((6:6+(E:C!>+7E

!":"((6:6+(E:C!>+7E specifies that )rites to the mappin& ma* be

buffered to impro-e performance.

(his attribute is onl* supported b* the "6! and "6!B4 architectures.

"dditionall*, the "6/2 architecture doesn5t implement the attribute8basedallocation "P+ but supports )rite combine allocation )ith the

dma:alloc:)ritecombine%' and dma:free:)ritecombine%' functions.

Memory Allocation Attri*utes

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!":"((6:E"?:6E6+7

!":"((6:E"?:6E6+7 specifies that reads and )rites to the

mappin& ma* be )eal* ordered, that is that reads and )rites ma* pass eachother.

(his attribute is onl* supported b* the CELL architecture %and isn5t used b*an* dri-er'.


!" "((6 77 C7S+S(E7(

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!":"((6:77:C7S+S(E7(

!":"((6:77:C7S+S(E7( lets the platform to choose to return either

consistent or non8consistent memor* as it sees fit. >* usin& this "P+, *ou are&uaranteein& to the platform that *ou ha-e all the correct and necessar* s*ncpoints for this memor* in the dri-er.

nl* the pen6+SC architecture returns non8consistent memor* in responseto this attribute. (he "6C, !+PS and P"6+SC architectures don5t support this

attribute but offer dedicated dma:alloc:noncoherent%' anddma:free:noncoherent%' functions for the same purpose.


!" "((6 6+(E >"66+E6

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!":"((6:6+(E:>"66+E6

!":"((6:6+(E:>"66+E6 is a %)rite' barrier attribute for !". !" to a

memor* re&ion )ith the !":"((6:6+(E:>"66+E6 attribute forces allpendin& !" )rites to complete, and thus pro-ides a mechanism to strictl*order !" from a de-ice across all inter-enin& buses and brid&es. (hisbarrier is not specific to a particular t*pe of interconnect, it applies to thes*stem as a )hole, and so its implementation must account for theidios*ncrasies of the s*stem all the )a* from the !" de-ice to memor*.

"s an example of a situation )here !":"((6:6+(E:>"66+E6 )ould beuseful, suppose that a de-ice does a !" )rite to indicate that data is read*and a-ailable in memor*. (he !" of the Dcompletion indication could race)ith data !". !appin& the memor* used for completion indications )ith!":"((6:6+(E:>"66+E6 )ould pre-ent the race.

(his attribute is onl* implemented b* the S+ S72 %+"B4' subarchitecture.


!" "((6 6CE C7(+S

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!":"((6:6CE:C7(+S

>* default the !"8mappin& subs*stem is allo)ed to assemble the buffer

allocated b* the dma:alloc:attrs%' function from indi-idual pa&es if it can bemapped conti&uousl* into de-ice !" address space. >* specif*in& thisattribute the allocated buffer is forced to be conti&uous also in ph*sicalmemor*.

(his attribute is onl* supported b* the "6! architecture.


!" "((6 7 ?E67EL !"PP+7

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!":"((6:7:?E67EL:!"PP+7

!":"((6:7:?E67EL:!"PP+7 lets the platform to a-oid creatin& a

ernel -irtual mappin& for the allocated buffer. n some architectures creatin&such mappin& is non8tri-ial tas and consumes -er* limited resources %lieernel -irtual address space or dma consistent address space'. >uffersallocated )ith this attribute can be onl* passed to user space b* callin&dma:mmap:attrs%'. >* usin& this "P+, *ou are &uaranteein& that *ou )on5tdereference the pointer returned b* dma:alloc:attr%'. 3ou can treat it as a

cooie that must be passed to dma:mmap:attrs%' and dma:free:attrs%'. !aesure that both of these also &et this attribute set on each call.

(his attribute is onl* supported b* the "6! architecture.


!" "((6 S?+P CP S37C

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!":"((6:S?+P:CP:S37C

hen a buffer is shared bet)een multiple de-ices one mappin& must be

created separatel* for each de-ice. (his is usuall* performed b* callin& the!" mappin& functions more than once for the &i-en buffer. (he first calltransfers buffer o)nership from CP domain to de-ice domain, )hichs*nchroni9es CP caches for the &i-en re&ion. Fo)e-er, subse

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!" !as

/* asm/dma-mapping.h %/

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/ asm/dma mapping.h /

int dma_set_mas#(struct device *dev u&' mas$

/* linux/dma-mapping.h %/

int dma_set_coherent_mas#(struct device *dev u&' mas$%

int dma_set_mas#_and_coherent(struct device *dev u&' mas$%

DMA Mas,

/* linux/de&ice.h*/

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struct device ) ...

u&' *dma_mas#% u&' coherent_dma_mas#% ...%

/* linux/dma-mapping.h %/

int dma_coerce_mas#_and_coherent(struct device *dev u&' mas$%

DMA Mas,

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serspace!appin&


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g g

/* +mlemented on arm arm&' and o,erc */

int dma_mmap_attrs(struct device *dev struct vm"area"struct *vma void *cu"addr dma"addr"t dma"addr si!e"t si!e struct dma"attrs *attrs$%

/* raers */

int dma_mmap_coherent(...$%int dma_mmap_'ritecom"ine(...$%

Userspace Mapping

int dma_mmap_attrs(struct device *dev

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struct vm"area"struct *vma void *cu"addr dma"addr"t dma"addr si!e"t si!e

struct dma"attrs *attrs$%

!ap coherent or )rite8combine !" memor* pre-iousl* allocated b*dma:alloc:attrs%' into user space. (he !" memor* must not be freed b*the dri-er until the user space mappin& has been released.

Creatin& multiple mappin&s )ith different t*pes %coherent, )rite8combined,)eal* ordered or non8coherent' produces undefined results on somearchitectures. Care must be taen to specif* the same t*pe attributes for allcalls to the dma:alloc:attrs%' and dma:mmap:attrs%' functions for the samememor*.

+f the memor* has been allocated )ith the 7:?E67EL:!"PP+7 attributethe same attribute must be passed to all calls to dma:mmap:attrs%'.

Userspace Mapping

/*

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* +mlemented on arc avr 0lacfin cris m&1 and* metag*/

int dma_mmap_coherent(struct device *dev struct vm"area"struct *vma void *cu"addr dma"addr"t dma"addr si!e"t si!e$%

/* +mlemented on metag */

int dma_mmap_'ritecom"ine(struct device *dev struct vm"area"struct *vma void *cu"addr dma"addr"t dma"addr si!e"t si!e$%

Userspace Mapping

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!"

Streamin&

!appin&

/* linux/dma-direction.h %/

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enum dma"data"direction )

!A_(II)*C+IONA,2 3 !A_+O_*IC*2 4 !A_F)O!_*IC*2 !A_NON*2 %

DMA Direction

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dma"addr"tdma_map_page(struct device *dev struct age *age

si!e"t offset si!e"t si!e enum dma"data"direction dir$%

voiddma_unmap_page(struct device *dev dma"addr"t addr si!e"t si!e enum dma"data"direction dir$%

Device Mapping


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intdma_map_sg_attrs(struct device *dev

struct scatterlist *sg int nents enum dma"data"direction dir struct dma"attrs *attrs$%

voiddma_unmap_sg_attrs(struct device *dev

struct scatterlist *sg int nents enum dma"data"direction dir struct dma"attrs *attrs$%

int dma_map_sg(...$%

voiddma_unmap_sg

(...$%

Device Mapping


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intdma_mapping_error(struct device *dev

dma"addr"t dma"addr$%

+n some circumstances dma:map:=%' )ill fail to createa mappin&. " dri-er can chec for these errors b* testin& the returned !"address )ith dma:mappin&:error%'. " non89ero return -alue means themappin& could not be created and the dri-er should tae appropriate action

%e.&. reduce current !" mappin& usa&e or dela* and tr* a&ain later'.

$rror Chec,ing


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voiddma_snc_single_for_cpu(struct device *dev

dma"addr"t addr si!e"t si!e enum dma"data"direction dir$%

voiddma_snc_single_for_de&ice(struct device *dev dma"addr"t addr si!e"t si!e

enum dma"data"direction dir$%

Synchroni-ation


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voiddma_snc_single_for_%(struct device *dev

dma"addr"t addr si!e"t si!e enum dma"data"direction dir$%

voiddma_snc_single_range_for_%(struct device *dev dma"addr"t addr

unsigned long offset si!e"t si!e enum dma"data"direction dir$%

voiddma_snc_sg_for_%(struct device *dev

struct scatterlist *sg int nelems enum dma"data"direction dir$%

(* 2 cu or device$

Synchroni-ation

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#include

dri&ers/"ase/dma-contiguous.h

CMA

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rom a Driver Point o /ie0

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rom a Driver Point o /ie0

(he Conti&uous !emor* "llocator %C!"' is inte&rated in the!" mappin& implementation. ri-ers )ill automaticall* recei-econti&uous memor* )hen usin& the dma:alloc:coherent%' anddma:alloc:attrs%' "P+.

/* linux/dma-contiguous.h %/

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void dma_contiguous_reser&e(h5s"addr"t addr"limit$%

int dma_declare_contiguous(struct device *dev h5s"addr"t si!e h5s"addr"t 0ase h5s"addr"t limit$%

rom a System Point o /ie0

/* linux/dma-contiguous.h %/

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void dma_contiguous_reser&e(h5s"addr"t addr"limit$%

(his function reser-es memor* from earl* allocator. +t should be called b* archspecific code once the earl* allocator %membloc or bootmem' has beenacti-ated and all other subs*stems ha-e alread* allocatedAreser-ed memor*.

(he si9e of the reser-ed memor* area is specified throu&h the ernelconfi&uration and can be o-erridden on the ernel command line. "n area ofthe &i-en si9e is reser-ed from the earl* allocator for conti&uous allocation.

int dma_declare_contiguous(struct device *dev h5s"addr"t si!e h5s"addr"t 0ase h5s"addr"t limit$%

(his function reser-es memor* for the specified de-ice. +t should be called b*board specific code )hen earl* allocator %membloc or bootmem' has beenacti-ated.

rom a System Point o /ie0

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+!!+nte&ration

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#include

IOMMU API

/* linux/iommu.h %/

t t i d i *

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struct iommu"domain *iommu_domain_alloc(struct 0us"t5e *0us$%

void iommu_domain_free(struct iommu"domain *domain$%int iommu_attach_de&ice(struct iommu"domain *domain struct device *dev$%void iommu_detach_de&ice(struct iommu"domain *domain struct device *dev$%

int iommu_map(struct iommu"domain *domain unsigned long iova h5s"addr"t addr si!e"t si!e int rot$%si!e"t iommu_unmap(struct iommu"domain *domain unsigned long iova si!e"t si!e$%

IOMMU API


t t d i i *

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struct dma"iommu"maing *arm_iommu_create_mapping(struct 0us"t5e *0us

dma"addr"t 0ase si!e"t si!e$%void arm_iommu_release_mapping( struct dma"iommu"maing *maing$%

int arm_iommu_attach_de&ice(struct device *dev struct dma"iommu"maing *maing$%

voidarm_iommu_detach_de&ice

(struct device *dev$%

IOMMU Integration 'A(M)

DSomeone must create the "6! mappin& and attach de-ices.

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(o achie-e transparent +!! inte&ration the calls must bemo-ed from de-ice dri-ers to +!! dri-ers. (his creates ne)challen&es;

e-ices mi&ht need fine8&rained control o-er the +!!%such as mappin& memor* at a fixed de-ice address'. (he*)ould then need to mana&e the +!! in cooperation )ith

the !" mappin& "P+. e-ices mi&ht ha-e se-eral bus master ports connected to

different +!!s, )hile the !" mappin& "P+ operates atthe de-ice le-el.

Po)er mana&ement needs to be taen care of.

IOMMU Integration 'A(M)

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e-ice (ree>indin&s

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GP"(CF -H 0A4I e-ice (ree support forC!" %Conti&uous !emor* "llocator'

http;AAl)n.netA"rticlesAB4K/0A

Device &ree Bindings 1 CMA

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(ips (rics

se the correct "P+, choose )isel* bet)een coherent andt i i

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streamin& mappin&s. on5t tr* to mana&e the cache manuall*, it5s bound to fail. Set *our !" mass. se dma:mappin&:error%'.

Coherent !appin&s

Set the !":"((6:S?+P:CP:S37C )hen callin&dma:map:=%'.

on5t call dma:s*nc:=%'.

&ips 2 &ric,s

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Problems +ssues

3eneric Pro*lems

Coherent mappin&s and streamin& mappin&s exhibit different

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pp & & pp &performances dependin& on the use case, )hich should be confi&urablefrom userspace.

Lac of standard ( bindin&s for +!!s. Coherent and non8coherent mass are confusin& and badl* implemented. Feaders hierarch* is confusin&. (he dma:s*nc:=%' "P+ has no attributes and thus can5t sip CP cache

s*nchroni9ation for coherent mappin&s.

A(M+Speciic Pro*lems

Lac of non8coherent allocation. lushin& a cache ran&e can be less efficient than flushin& the )hole 8

cache. (he !" mas is not taen into account )hen creatin& +!!

mappin&s.

Pro*lems 2 Issues

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6esources

ocumentationA!"8"P+8F(.txtocumentationA!"8"P+ txt

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ocumentationA!" "P+.txt

ocumentationA!"8attributes.txt

http;AAcommunit*.arm.comA&roupsAprocessorsAblo&A2011A0/A22Amemor*8access8orderin&8an8introductionhttp;AAelinux.or&Aima&esAHAH/Aeacon8)ea8to8)eed*.pdf

https;AAl)n.netA"rticlesA4KB/01A

Documentation

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linu%+,ernel4vger.,ernel.orglinu%+arm+,ernel4lists.inradead.org

[email protected]

Contact

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M #

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(hx.

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"d-anced(opics

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!" Coherent!emor* Pool

/* linux/dmapool.h %/

(he !" mappin& "P+ allocates buffers in at least pa&e si9e chuns. +f *ourdri er needs lots of smaller memor re&ions o can se the !" pool "P+ to

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dri-er needs lots of smaller memor* re&ions *ou can use the !" pool "P+ tosubdi-ide pa&es returned b* dma:alloc:coherent%'.

struct dma"ool *dma_pool_create(const char *name struct device *dev si!e"t si!e si!e"t align si!e"t 0oundar5$%

(his function creates a !" allocation pool to allocate buffers of the &i-en@si9e and ali&nment characteristics %@ must be a po)er of t)o and can beset to 9ero'. +f @boundar* is non9ero, obNects returned from dma:pool:alloc%')on5t cross that si9e boundar*. (his is useful for de-ices )hich ha-eaddressin& restrictions on indi-idual !" transfers.

i-en one of these pools, dma:pool:alloc%' ma* be used to allocate memor*.Such memor* )ill all ha-e Dconsistent !" mappin&s, accessible b* thede-ice and its dri-er )ithout usin& cache flushin& primiti-es.

DMA Pool

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7on8Coherent!appin&


void *dma alloc noncoherent(struct device *dev si!e t si!e

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dma_alloc_noncoherent(struct device dev si!e"t si!e dma"addr"t *dma"handle gf"t flag$%

voiddma_free_noncoherent(struct device *dev si!e"t si!e void *cu"addr dma"addr"t dma"handle$%

5on+Coherent Allocation

(he non8coherent memor* allocation is architecture8dependent. (he follo)in&list summari9es the beha-iour of supported architectures.

Allocates 5ormal Cachea*le Memory

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Allocates 5ormal Cachea*le Memory

arc, mips, openrisc, parisc

Allocates Coherent Memory

alpha, a-r/2, blacfin, cBx, cris, fr-, hexa&on, iaB4, mBK, meta&,microbla9e, mn10/00, po)erpc, s/O0, sh, sparc, tile, unicore/2, xKB,

xtensa

7ote that some of those architectures can be full* coherent, in )hich casethe concept of non8coherent memor* doesn5t appl* and memor* mappin&sare al)a*s coherent.

(eturns 5U!!

arm, armB4

5on+Coherent Allocation

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eneric !"Coherent!emor*

"llocator

/* asm-generic/dma-coherent.h %/

/** 6tandard interface

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6tandard interface*/#define 789:":76";7";=978="9?:=8=@A"=?8Bextern intdma_declare_coherent_memor(struct device *dev dma"addr"t 0us"addr dma"addr"t device"addr si!e"t si!e int flags$%

extern voiddma_release_declared_memor(struct device *dev$%

extern void *dma_mar#_declared_memor_occupied(struct device *dev

dma"addr"t device"addr si!e"t si!e$%

Device API


extern intdma declare coherent memor(struct device *dev

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_ _ _ ( dma"addr"t 0us"addr dma"addr"t device"addr si!e"t si!e int flags$%

eclare a coherent memor* area for a de-ice. (he area is specified b* its%CP' bus address, de-ice bus address and si9e. (he follo)in& fla&s can bespecified;

!":!E!63:!"P allocated memor* is directl* )ritable %al)a*s set'. !":!E!63:+ allocated memor* accessed as +A mem %unused'. !":!E!63:+7CLES:CF+L6E7 declared memor* a-ailable to

all child de-ices %unsupported'. !":!E!63:EQCLS+E force allocation to be made exclusi-el*

from the coherent area for this de-ice )ithout an* fallbac method.

nl* a sin&le coherent memor* area can be declared per de-ice.

Device API


extern voiddma_release_declared_memor(struct device *dev$%

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( $%

6elease the coherent memor* pre-iousl* declared for the de-ice. "ll !"coherent memor* allocated for the de-ice must be freed before callin& thisfunction.

Device API

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/** Ahese three functions are onl5 for dma allocator.

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* ;onCt use them in device drivers.*/

Allocator Private API


/** Ahese three functions are onl5 for dma allocator.

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* ;onCt use them in device drivers.

*/int dma_alloc_from_coherent(struct device *dev ssi!e"t si!e dma"addr"t *dma"handle void **ret$%int dma_release_from_coherent(struct device *dev

int order void *vaddr$%int dma_mmap_from_coherent(struct device *dev struct vm"area"struct *vma void *cu"addr si!e"t si!e int *ret$%



int dma_alloc_from_coherent(struct device *dev ssi!e"t si!e

d dd *d h dl

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dma"addr"t *dma"handle

void **ret$%

(r* to allocate memor* from the per8de-ice coherent area.

6eturns 0 if dma:alloc:coherent should continue )ith allocatin& from&eneric memor* areas, or #0 if dma:alloc:coherent should return @ret.

(his function can onl* be called from per8arch dma:alloc:coherent %anddma:alloc:attrs' to support allocation from per8de-ice coherent memor*pools.


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int dma_mmap_from_coherent(struct device *dev struct vm"area"struct *vma

id * dd i t i

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void *cu"addr si!e"t si!e

int *ret$%

(r* to mmap the memor* allocated from per8de-ice coherent memor* poolto userspace.

(his checs )hether the memor* )as allocated from the per8de-ice

coherent memor* pool and if so, maps that memor* to the pro-ided -ma andreturns 1. ther)ise it returns 0 to si&nal that the caller should proceed )ithmappin& memor* from &eneric pools.

(his function can onl* be called from )ithin the architecture5sdma:alloc:coherent %and dma:alloc:attrs' implementation.


Documents

20140429-dma