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30.05.04
הטכניון - מכון טכנולוגי לישראל
המעבדה למערכות ספרתיות מהירותהפקולטה להנדסת חשמל
MidTermMidTerm PresentationPresentation
Enhanced Ethernet CardEnhanced Ethernet CardProject num. 1523Project num. 1523
Students:Students: Alex ShpinerAlex Shpiner
Eyal AzranEyal Azran
Supervisor:Supervisor: Boaz MizrahiBoaz Mizrahi
Project’s goals: Automatic ping reply
Real time Packet analyzer & data collector
Real time Network Testing Unit:
Predefined transmit rate
Accurate measurement of response time
Testing parameters are predefined by user
MAC
CIF
TRN
RCV
ARB
FPGA ArchitectureFPGA Architecture
Shared bus
TRP
RCP
* Configuration units (GNR, MCF) are not shown on this diagram
TRP – Transmit TRP – Transmit Processing UnitProcessing Unit
Echo Request
Parameters
Regular Packets to be transmitted
Echo RequestGenerator
Echo ReplyCreator
TRN Arbiter
CIF
TRN
RCP
TRP
Echo request Echo request parametersparameters
IP MAC
•Inter Packet Gap
•Total number of test cycles
•IP-MAC table:
Transmit Packets Buffer
DATA FIFO
TRANSMITTER
EOP FIFO
BE FIFO
TRN_ARB
TRN
Use
r P
acke
ts
Echo Request Creator
DATA FIFO
TRANSMITTER
EOP FIFO
BE FIFO
TRN_ARB
TRN
Tra
nsm
itP
aram
eter
s
PacketCreator
Echo Reply Creator
DATA FIFO
TRANSMITTER
EOP FIFO
BE FIFO
TRN_ARB
TRNPacketCreator
RCP
TRN Arbiter
RCP – Receive RCP – Receive Processing UnitProcessing Unit
Regular Packets Received
Data Collector
PacketAnalyzer
CIF
RCV
TRP
RCPEcho RAM
RCP – Receive RCP – Receive Processing UnitProcessing Unit
Data
FIFO with Back PointerPacket
Received
FSM
Address Type
TRP
Echo received
ERP ready
Data Collector
Data CollectorData Collector
IP MAC
•Min/Max Delay
•Total packages received
•Sources IP-MAC addresses table:
Approximated Time Table
Time line
Learning the Network ProtocolsArchitecture Design and Algorithms Development
Final Presentation and Project Book Submitting
Writing the code and simulationSynthesis & Debug
March 2004
April 2004
May to June 2004Jule 2004
August 2004
ThanksThanks
