31801941 Laporan Jam Digital

LAPORAN PRAKTIKUM

TEKNIK DIGITAL

PENBUATAN JAM DIGITAL

DENGAN IC 7493

Oleh :

BUDI UTOMO ( IB/10 )

IMANDA RAHMA ARUM ( IB/15)

NURUL FURQON R ( IB/20 )

POLITEKNIK NEGERI MALANG

JURUSAN TEKNIK ELEKTRO

PROGRAM STUDI TEKNIK TELEKOMUNIKASI

A. Tujuan 1. Dapat menerapkan logika dasar dari suatu perangkat digital 2. Dapat merancang suatu system dengan menggunakan IC TTL

(Trasistor – Transistor Logika) 3. Mengetahui cara kerja IC 7493. 4. Mengetahui cara pengaplikasian IC 7493 pada pembuatan jam digital. 5. Mengetahui cara kerja IC 7447. 6. Mengetahui prinsip kerja dari seven segmen common anoda.

B. Teori Dasar

Jam elektronika digital yang terdiri dari pencacah yang merupakan komponen terpenting dari

sistem jam digital. Gambar (1) merupakan diagram blok sederhana suatu sistem jam digital.

Kebanyakan jam menggunakan daya frekuensi jala-jala 60 Hz sebagai masukannya. Frekuensi ini

dibagi menjadi detik, menit dan jam oleh bagian pembagi frekuensi dari jam tersebut. Kemudian

pulsa satu-per-detik, satu-per-menit, dan satu-per-jam dihitung dan disimpan dalam akumulator

pencacah jam tersebut. Selanjutnya isi akumulator pencacah (detik, menit, jam) yang tersimpan

didekode, dan waktu yang tepat ditayangkan pada tayangan waktu keluaran. Jam digital

mempunyai elemen sistem khusus. Masukannya berupa arus bolak-balik 60 Hz. Pengolahan

terjadi pada pembagi frekuensi, akumulator pencacah, dan bagian pendekode.

MASUKAN KELUARAN

60Hz

Set waktu Gambar (1)

Pembagi frekuensi

Counter Dekoder 7-Segmen display

Jam menit detik

KELUARAN

1 pulsa/jam 1 pulsa/menit 1 pulsa/detik

MASUKAN

60 Hz detik menit jam

Penyimpanan terjadi pada akumulator. Bagian kendali barupa kendali set-waktu seperti pada

gambar (2). Telah disebutkan bahwa semua sistem terdiri atas gerbang logika, flip-flop, dan

subsistem. Diagram pada gambar (2) memperlihatkan bagaiman subsistem diorganisasikan

sampai menampilkan waktu dalam jam, menit, detik. Ini merupakan diagram jam digital yang

lebih terinci. Masukan berupa sinyal 60 Hz. 60 Hz dibagi 60 oleh pembagi frekuensi pertama.

Keluaran rangkaian pembagi ini berupa pulsa 1 per detik. Pulsa 1 per detik dimasukkan ke

pencacah naik yang mencacah naik dari 00 sampai 59 dan reset 00. Kemudian pencacah detik

didekode dan ditayangkan pada 7segmen.

Perhatikan rangkaian pembagi frekuensi tengah pada gambar (2). Masukan pada rangkaian ini

berupa pulsa1 per detik. Keluarannya berupa pulsa 1 per menit. Keluaran pulsa 1 per menit

dipindah ke pencacah menit 0 - 59. Pencacah naik ini mengawasi jumlah menit dari 00 sampai 59

dan reset menjadi 00. Keluaran akumulator pencacah menit didekode dan ditayangkan pada dua

7-segmen di sebelah atas tengah gambar (2).

Dekoder DekoderDekoder

Counter hit. 0-59

Counter hit. 0-23

Counter Hit. 0-59

Dibagi dengan 60

Dibagi dengan 60

Dibagi dengan 60

Gambar (2)

Memperhatikan rangkaian pembagi 60 di sebelah kanak gambar (2). Masukan pada pembagi

frekuensi ini adalah pulsa 1 per menit. Keluaran rangkaian ii adalah pulsa 1 per jam. Keluaran pulsa 1

per jam dipindah ke pencacah jam di sebelah kiri. Akumulator pencacah jam ini mengawasi jumlah

jam dari 0 sampai 23. keluaran akumulator jam didekode dan dipindahkan kedua penayang 7-segmen

pada kiri atas gambar (2). Kita telah perhatikan bahwa rangkaian tersebut sudah berupa suatu jam

digital 24-jam. Rangkaian tersebut dapat diubah dengn mudah menjadi jam 12-jam dengan menukar

akumulator pencacah 0 sampai 23 menjadi pencacah 0 sampai 11.

C. Alat dan Bahan 1. Protoboard 3x 2. IC 7493 (4 binary counter) 6x 3. IC 7447 (BCD to 7-Segment Decoder/Driver) 6x 4. IC 7408 (Quard 2-input AND Gate) 1x 5. IC 7432 (Quard 2-input OR Gate) 1x 6. 7-Segment Display Common Anoda 6x 7. Resistor 300Ω 6x 8. Power Supply 9. Clock Generator 10. Kabel Penghubung

D. Rangkaian Logika

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

1 Hz

Decoder Driver

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

Decoder Driver

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

Decoder Driver

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

Decoder Driver

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

Decoder Driver

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

Decoder Driver

Detik Menit

Jam

E. Hubungan IC

F. Kesimpulan

o IC 74 LS 93 merupakan IC 4 bit counter yang dapat digunakan dalam rancangan

pembuatan jam digital.

o Tampilan jam harus direset dua kali dengan gerbang AND & OR agar 7-segment tidak

menampilkan nilai lebih dari 24.

o Rangkaian detik pada jam digital merupakan rangkaian pembagi 60.

o Rangkaian menit pada jam digital merupakan rangkaian pembagi 3600.

o Rangkaian jam pada jam digital merupakan rangkaian pembagi 86400.

Lampiran URUTAN KAKI 7 – SEGMEN DISPLAY

G F

CO

MM

ON

A B

E D

CO

MM

ON

C dot

A

B

G

C

F

E

D

5-1

FAST AND LS TTL DATA

DECADE COUNTER;DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTER

The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed4-bit ripple type counters partitioned into two sections. Each counter has a di-vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) ordivide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-tion on the clock inputs. Each section can be used separately or tied together(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All ofthe counters have a 2-input gated Master Reset (Clear), and the LS90 alsohas a 2-input gated Master Set (Preset 9).

• Low Power Consumption . . . Typically 45 mW• High Count Rates . . . Typically 42 MHz• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,

Binary• Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES LOADING (Note a)

HIGH LOW

CP0 Clock (Active LOW going edge) Input to÷2 Section

0.5 U.L. 1.5 U.L.

CP1 Clock (Active LOW going edge) Input to÷5 Section (LS90), ÷6 Section (LS92)

0.5 U.L. 2.0 U.L.

CP1 Clock (Active LOW going edge) Input to÷8 Section (LS93)

0.5 U.L. 1.0 U.L.

MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L.MS1, MS2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L.Q0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92),

÷8 (LS93) Sections (Note b)10 U.L. 5 (2.5) U.L.

NOTES:a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)b. Temperature Ranges.c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.

SN54/74LS90SN54/74LS92SN54/74LS93

DECADE COUNTER;DIVIDE-BY-TWELVE COUNTER;

4-BIT BINARY COUNTER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1

ORDERING INFORMATION

SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC

141

D SUFFIXSOIC

CASE 751A-02

LOGIC SYMBOL

1 22

VCC = PIN 5GND = PIN 10NC = PINS 4, 13

VCC = PIN 5GND = PIN 10NC = PINS 2, 3, 4, 13

VCC = PIN 5GND = PIN 10NC = PIN 4, 6, 7, 13

LS90 LS92 LS936 7

1 2

14

1

1 2

2 3

MSCP0

CP1MR Q0 Q1 Q2 Q3

12 9 8 11 6 7

14

1

1

CP0

CP1MR Q0 Q1 Q2 Q3

12 9 811

14

1

2 3

CP0

CP1MR Q0 Q1 Q2 Q3

12 9 8 11

5-2


SN54/74LS90 • SN54/74LS92 • SN54/74LS93

LOGIC DIAGRAM

MS1MS2

MR1MR2

CP0

CP1

Q0 Q1 Q2 Q3

MR1

CP0

CP1

Q0 Q1 Q2 Q3MR2

LS90

MR1

CP0

CP1

Q0 Q1 Q2 Q3MR2

SDJ

CP

K

Q

QCD

SDR

CP

S

Q

QCD

SDJ

CP

K

Q

QCD

SDJ

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

J

CP

K

Q

QCD

14

1112

1

2

6

7

9

3

8

14

13

12

11

10

9

1

2

3

4

5

6

87

CP0

NC

Q0

Q3

GND

Q1

Q2

CP1

MR1

MR2

NC

VCC

MS1

MS2

CONNECTION DIAGRAMDIP (TOP VIEW)

NC = NO INTERNAL CONNECTION

NOTE:The Flatpak version has the samepinouts (Connection Diagram) asthe Dual In-Line Package.

14

1

6

7

12 11 9 8

LOGIC DIAGRAM

LS92

14

13

12

11

10

9

1

2

3

4

5

6

87

CP0

NC

Q0

Q1

GND

Q2

Q3

CP1

NC

NC

NC

VCC

MR1

MR2




LOGIC DIAGRAM

LS93

VCC = PIN 5GND = PIN 10

= PIN NUMBERS


= PIN NUMBERS


= PIN NUMBERS

14

1

2

312 9 8 11

14

13

12

11

10

9

1

2

3

4

5

6

87

CP0

NC

Q0

Q3

GND

Q1

Q2

CP1

MR1

MR2

NC

VCC

NC

NC




5-3


SN54/74LS90 • SN54/74LS92 • SN54/74LS93

FUNCTIONAL DESCRIPTION

The LS90, LS92, and LS93 are 4-bit ripple type Decade,Divide-By-Twelve, and Binary Counters respectively. Eachdevice consists of four master/slave flip-flops which areinternally connected to provide a divide-by-two section and adivide-by-five (LS90), divide-by-six (LS92), or divide-by-eight(LS93) section. Each section has a separate clock input whichinitiates state changes of the counter on the HIGH-to-LOWclock transition. State changes of the Q outputs do not occursimultaneously because of internal ripple delays. Therefore,decoded output signals are subject to decoding spikes andshould not be used for clocks or strobes. The Q0 output ofeach device is designed and specified to drive the ratedfan-out plus the CP1 input of the device.

A gated AND asynchronous Master Reset (MR1 • MR2) isprovided on all counters which overrides and clocks andresets (clears) all the flip-flops. A gated AND asynchronousMaster Set (MS1 • MS2) is provided on the LS90 whichoverrides the clocks and the MR inputs and sets the outputs tonine (HLLH).

Since the output from the divide-by-two section is notinternally connected to the succeeding stages, the devicesmay be operated in various counting modes.

LS90

A. BCD Decade (8421) Counter — The CP1 input must be ex-ternally connected to the Q0 output. The CP0 input receivesthe incoming count and a BCD count sequence is pro-duced.

B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3output must be externally connected to the CP0 input. Theinput count is then applied to the CP1 input and a divide-by-ten square wave is obtained at output Q0.

C. Divide-By-Two and Divide-By-Five Counter — No externalinterconnections are required. The first flip-flop is used as abinary element for the divide-by-two function (CP0 as theinput and Q0 as the output). The CP1 input is used to obtainbinary divide-by-five operation at the Q3 output.

LS92

A. Modulo 12, Divide-By-Twelve Counter — The CP1 inputmust be externally connected to the Q0 output. The CP0 in-put receives the incoming count and Q3 produces a sym-metrical divide-by-twelve square wave output.

B. Divide-By-Two and Divide-By-Six Counter —No externalinterconnections are required. The first flip-flop is used as abinary element for the divide-by-two function. The CP1 in-put is used to obtain divide-by-three operation at the Q1and Q2 outputs and divide-by-six operation at the Q3 out-put.

LS93

A. 4-Bit Ripple Counter — The output Q0 must be externallyconnected to input CP1. The input count pulses are appliedto input CP0. Simultaneous divisions of 2, 4, 8, and 16 areperformed at the Q0, Q1, Q2, and Q3 outputs as shown inthe truth table.

B. 3-Bit Ripple Counter— The input count pulses are appliedto input CP1. Simultaneous frequency divisions of 2, 4, and8 are available at the Q1, Q2, and Q3 outputs. Independentuse of the first flip-flop is available if the reset function coin-cides with reset of the 3-bit ripple-through counter.

5-4


SN54/74LS90 • SN54/74LS92 • SN54/74LS93

LS90MODE SELECTION

RESET/SET INPUTS OUTPUTS

MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3

HHXLXLX

HHXXLXL

LXHLXXL

LLH

LLL

LLL

LLH

CountCountCountCount

XLHXLLX

H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care

LS92 AND LS93MODE SELECTION

RESETINPUTS OUTPUTS

MR1 MR2 Q0 Q1 Q2 Q3

HLHL

HHLL

L L L LCountCountCount

H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care

LS90BCD COUNT SEQUENCE

COUNTOUTPUT

Q0 Q1 Q2 Q3

0123456789

LHLHLHLHLH

LLHHLLHHLL

LLLLHHHHLL

LLLLLLLLHH

NOTE: Output Q0 is connected to InputCP1 for BCD count.

LS92TRUTH TABLE

COUNTOUTPUT

Q0 Q1 Q2 Q3

0123456789

1011

LHLHLHLHLHLH

LLHHLLLLHHLL

LLLLHHLLLLHH

LLLLLLHHHHHH

NOTE: Output Q0 is connected to InputCP1.

LS93TRUTH TABLE

COUNTOUTPUT

Q0 Q1 Q2 Q3

0123456789

101112131415

LHLHLHLHLHLHLHLH

LLHHLLHHLLHHLLHH

LLLLHHHHLLLLHHHH

LLLLLLLLHHHHHHHH

NOTE: Output Q0 is connected to InputCP1.

5-5


SN54/74LS90 • SN54/74LS92 • SN54/74LS93

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 5474

4.54.75

5.05.0

5.55.25

V

TA Operating Ambient Temperature Range 5474

–550

2525

12570

°C

IOH Output Current — High 54, 74 –0.4 mA

IOL Output Current — Low 5474

4.08.0

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

S b l P

Limits

U i T C di iSymbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs

VIL Input LOW Voltage54 0.7

VGuaranteed Input LOW Voltage for


Vp g

All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH Output HIGH Voltage74 2.7 3.5 V

CC , OH , IN IHor VIL per Truth Table

VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN = VIL or VIHVOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA

VIN = VIL or VIHper Truth Table

IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V

IIL

Input LOW CurrentMS, MRCP0CP1 (LS90, LS92)CP1 (LS93)

–0.4–2.4–3.2–1.6

mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC Power Supply Current 15 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

5-6


SN54/74LS90 • SN54/74LS92 • SN54/74LS93

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF)

S b l P

Limits

U iS b l P

LS90 LS92 LS93

U iSymbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit

fMAX CP0 Input Clock Frequency 32 32 32 MHz

fMAX CP1 Input Clock Frequency 16 16 16 MHz

tPLHtPHL

Propagation Delay,CP0 Input to Q0 Output

1012

1618

1012

1618

1012

1618 ns

tPLHtPHL

CP0 Input to Q3 Output3234

4850

3234

4850

4646

7070 ns

tPLHtPHL


1621

1014

1621

1014

1621 ns

tPLHtPHL


3235

1014

1621

2123

3235 ns

tPLHtPHL


3235

2123

3235

3434

5151 ns

tPLH MS Input to Q0 and Q3 Outputs 20 30 ns

tPHL MS Input to Q1 and Q2 Outputs 26 40 ns

tPHL MR Input to Any Output 26 40 26 40 26 40 ns

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

S b l P

Limits

U iS b l P

LS90 LS92 LS93

U iSymbol Parameter Min Max Min Max Min Max Unit

tW CP0 Pulse Width 15 15 15 ns

tW CP1 Pulse Width 30 30 30 ns

tW MS Pulse Width 15 ns

tW MR Pulse Width 15 15 15 ns

trec Recovery Time MR to CP 25 25 25 ns

RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognizeand transfer HIGH data to the Q outputs

AC WAVEFORMS

Figure 1

Figure 2 Figure 3

*CP

Q

1.3 V

tPHLtW

1.3 V

1.3 V 1.3 V

1.3 V

tPLH

*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.

MR & MS

CP

Q

MS

Q0 • Q3(LS90)

1.3 V 1.3 V

1.3 V

1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tPHL

tW

tPLH

trec tW

CP

trec

5-1


BCD TO 7-SEGMENTDECODER/DRIVER

The SN54/74LS47 are Low Power Schottky BCD to 7-Segment Decod-er /Drivers consisting of NAND gates, input buffers and seven AND-OR-IN-VERT gates. They offer active LOW, high sink current outputs for drivingindicators directly. Seven NAND gates and one driver are connected in pairsto make BCD data and its complement available to the seven decodingAND-OR-INVERT gates. The remaining NAND gate and three input buffersprovide lamp test, blanking input / ripple-blanking output and ripple-blankinginput.

The circuits accept 4-bit binary-coded-decimal (BCD) and, depending onthe state of the auxiliary inputs, decodes this data to drive a 7-segment displayindicator. The relative positive-logic output levels, as well as conditionsrequired at the auxiliary inputs, are shown in the truth tables. Outputconfigurations of the SN54/74LS47 are designed to withstand the relativelyhigh voltages required for 7-segment indicators.

These outputs will withstand 15 V with a maximum reverse current of250 µA. Indicator segments requiring up to 24 mA of current may be drivendirectly from the SN74LS47 high performance output transistors. Displaypatterns for BCD input counts above nine are unique symbols to authenticateinput conditions.

The SN54/74LS47 incorporates automatic leading and/or trailing-edgezero-blanking control (RBI and RBO). Lamp test (LT) may be performed at anytime which the BI /RBO node is a HIGH level. This device also contains anoverriding blanking input (BI) which can be used to control the lamp intensityby varying the frequency and duty cycle of the BI input signal or to inhibit theoutputs.

• Lamp Intensity Modulation Capability (BI/RBO)• Open Collector Outputs• Lamp Test Provision• Leading/Trailing Zero Suppression• Input Clamp Diodes Limit High-Speed Termination Effects

14 13 12 11 10 9

1 2 3 4 5 6

VCC

7

16 15

8

f g a b c d e

B C LT BI / RBO RBI D A GND

CONNECTION DIAGRAM DIP (TOP VIEW)

PIN NAMES LOADING (Note a)

HIGH LOW

A, B, C, DRBILTBI /RBO

a, to g

BCD InputsRipple-Blanking InputLamp-Test InputBlanking Input orRipple-Blanking OutputOutputs

0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.1.2 U.L.

Open-Collector

0.25 U.L.0.25 U.L.0.25 U.L.0.75 U.L.

2.0 U.L.15 (7.5) U.L.

NOTES:a) 1 Unit Load (U.L.) = 40 µA HIGH, 1.6 mA LOW.b) Output current measured at VOUT = 0.5 V

The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74) Temperature Ranges.

SN54/74LS47

BCD TO 7-SEGMENTDECODER/DRIVER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1

ORDERING INFORMATION

SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC

161

D SUFFIXSOIC

CASE 751B-03

LOGIC SYMBOL


7 1 2 6 3 5

13 12 11 10 9 15 14 4

A B C D LT RBI

a b c d e f gBI/RBO

INPUTS OUTPUTS

TRUTH TABLE

5-2


SN54/74LS47

14 15

LOGIC DIAGRAM

NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS

0 1 2 3 4 5 6 7 8 9 10 11 12 13

INPUT

BLANKING INPUT ORRIPPLE-BLANKINGOUTPUT

RIPPLE-BLANKINGINPUT

LAMP-TESTINPUT

A

B

C

D

a a

b b

c c

d d

e e

f f

g g

OUTPUT

DECIMALOR

FUNCTIONLT RBI D C B A BI/RBO a b c d e f g NOTE

0 H H L L L L H L L L L L L H A

1 H X L L L H H H L L H H H H A

2 H X L L H L H L L H L L H L

3 H X L L H H H L L L L H H L

4 H X L H L L H H L L H H L L

5 H X L H L H H L H L L H L L

6 H X L H H L H H H L L L L L

7 H X L H H H H L L L H H H H

8 H X H L L L H L L L L L L L

9 H X H L L H H L L L H H L L

10 H X H L H L H H H H L L H L

11 H X H L H H H H H L L H H L

12 H X H H L L H H L H H H L L

13 H X H H L H H L H H L H L L

14 H X H H H L H H H H L L L L

15 H X H H H H H H H H H H H H

BI X X X X X X L H H H H H H H B

RBI H L L L L L L H H H H H H H C

LT L X X X X X H L L L L L L L D

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

NOTES:(A) BI/RBO is wire-AND logic serving as blanking Input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held

at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blankingof a decimal 0 is not desired. X = input may be HIGH or LOW.

(B) When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state ofany other input condition.

(C) When ripple-blanking input (RBI) and inputs A, B, C, and D are at LOW level, with the lamp test input at HIGH level, all segment outputsgo to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).

(D) When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp test input,all segment outputs go to a LOW level.

5-3


SN54/74LS47

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 5474

4.54.75

5.05.0

5.55.25

V

TA Operating Ambient Temperature Range 5474

–550

2525

12570

°C

IOH Output Current — High BI /RBO 54, 74 –50 µA

IOL Output Current — Low BI /RBOBI /RBO

5474

1.63.2

mA

VO (off) Off-State Output Voltage a to g 54, 74 15 V

IO (on) On-State Output Current a to gOn-State Output Current a to g

5474

1224

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

S b l P

Limits


VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Theshold Voltagefor All Inputs


VGuaranteed Input LOW Threshold Voltage


Vp g

for All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage BI /RBO 2 4 4 2 VVCC = MIN, IOH = –50 µA,

VOH Output HIGH Voltage, BI /RBO 2.4 4.2 V CC , OH µ ,VIN = VIN or VIL per Truth Table

VOLOutput LOW Voltage 54, 74 0.25 0.4 V IOL = 1.6 mA VCC = MIN, VIN = VIN or

VOLp g

BI /RBO 74 0.35 0.5 V IOL = 3.2 mACC , IN IN

VIL per Truth Table

IO (off)Off-State Output Currenta thru g 250 µA

VCC = MAX, VIN = VIN or VIL per TruthTable, VO (off) = 15 V

VO (on)On-State Output Voltage 54, 74 0.25 0.4 V IO (on) = 12 mA VCC = MAX, VIN = VIH

V T th T blVO (on)p g

a thru g 74 0.35 0.5 V IO (on) = 24 mACC IN IH

or VIL per Truth Table

IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V

IILInput LOW Current BI /RBOAny Input except BI /RBO

–1.2–0.4 mA VCC = MAX, VIN = 0.4 V

IOS BI /RBO Output Short Circuit Current (Note 1) –0.3 –2.0 mA VCC = MAX, VOUT = 0 V

ICC Power Supply Current 7.0 13 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

S b l P

Limits


tPHLtPLH

Propagation Delay, AddressInput to Segment Output

100100

nsns VCC = 5.0 V

tPHLtPLH

Propagation Delay, RBI InputTo Segment Output

100100

nsns

VCC 5.0 VCL = 15 pF

AC WAVEFORMS

VIN

VOUT

1.3 V 1.3 V

1.3 V 1.3 V

tPHL tPLH

Figure 1 Figure 2

1.3 V 1.3 V

1.3 V1.3 V

tPLHtPHL

VIN

VOUT

Documents

31801941 Laporan Jam Digital