45nm PLL Loop Measurement Circuit - Dennis PLL + Loop Measurement Circuit Digital State Machine no analog circuits Minimal overhead/intrusion communicates with feedback divider only

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    An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI

    Dennis Fischette, Richard DeSantis, John H. Lee1

    AMD, Sunnyvale, California, USA1 MIT, Cambridge, Massachusetts, USA

    Custom Integrated Circuits ConferenceSeptember 16, 2009

  • 2

    Outline

    Motivation

    Loop Measurement Circuit

    Algorithm

    Architecture

    Silicon Results

    Conclusion

  • 3

    PLL Closed-Loop Transfer Function

    Frequency domain model

    Input: excess phase modulation of input (reference) clock

    Output: excess phase modulation of feedback clock

    Jitter Modulation Frequency

    100kHz 1MHz 10MHz 100MHz

    No

    rmali

    zed

    Jit

    ter

    Tra

    ns

    fer

    (dB

    )

    Low

    damping

    High

    damping

    0

    +2

    +4

    +6

    -6

    -4

    -2

    PLL

    tftft cfeedback mod 2

    BW

    Peaking

    ttft crefclk mod 2

  • 4

    Motivation

    Strict bandwidth and peaking requirements

    e.g., PCI Express Generation II @ 5 Gb/s

    58 MHz BW / < 1 dB peaking

    816 MHz BW / < 3 dB peaking

    Locktime (function of BW) increasingly important given frequent exit from sleep/power-save states

    Device PVT variation simulations inadequate

    Standard methods

    Spectrum Analyzer, Waveform Generator

    Problems with standard methods

    Slow expensive

    Wafer? Package? Product? inflexible

  • 5

    Outline

    Motivation

    Loop Measurement Circuit

    Algorithm

    Architecture

    Silicon Results

    Conclusion

  • 6

    Simulated Step Response vs. Time

    0

    +2

    +4

    +6

    -6

    -4

    -2

    -8

    Time (s)

    Ph

    ase

    Err

    or

    (ns)

    0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

    Tcrossover

    MaxOvershoot

  • 7

    Basis of Algorithm

    Relationship between time & frequency domain behavior

    Lower BW higher Tcrossover

    Larger input phase step larger peaking

    0.00

    0.05

    0.10

    0.15

    0.20

    0.25

    0.0 0.1 0.2 0.3 0.4 0.5 0.6

    50%

    75%

    1/BW (s)

    Tc

    ros

    so

    ve

    r(

    s)

    Linear Fit

    TrefclkPhase Step

    MaxO

    vers

    ho

    ot

    (ns)

    Peaking (dB)

    0

    1

    2

    3

    4

    5

    0 1 2 3 4 5 6 7 8 9

    50%

    75%

    TrefclkPhase Step

    Linear Fit

  • 8

    Closed-Form Equations for Phase Error

    Damping Factor < 1 (underdamped)

    Damping Factor = 1 (critically damped)

    Damping Factor > 1 (overdamped)

    tet nt

    steperrn 1

    1

    11 2

    2

    2

    ttet nn

    t

    steperrn sinhcosh

    2

    2

    2 11

    1

    ttet nn

    t

    steperrn sincos

    Source: Gardner, Phaselock Techniques, 2005

  • 9

    Closed-Form Equations vs. Simulations

    0.00

    0.05

    0.10

    0.15

    0.20

    0.25

    0.0 0.1 0.2 0.3 0.4 0.5 0.6

    Simulation

    Equation

    1/BW (s)

    Tcro

    sso

    ve

    r(

    s)

    Ma

    xO

    ve

    rsh

    oo

    t (n

    s)

    Peaking (dB)

    0

    1

    2

    3

    4

    5

    0 1 2 3 4 5 6 7 8 9

    Simulation

    Equation

    75% Trefclk Phase Step 75% Trefclk Phase Step

    Equations become less accurate at high due to smoothing loop filter pole for reference spur reduction

  • 10

    PLL + Loop Measurement Circuit

    Digital State Machine no analog circuits

    Minimal overhead/intrusion communicates with feedback divider only

    Instantaneously steps feedback clock phase programmable, directional

    Measures Tcrossover and MaxOvershoot

    UP

    Gain Control Range ControlRefClk

    FbClk

    FbDiv[5:0]FbCnt[5:0]

    Nstep[5:0]

    N[5:0]

    Start

    BwCnt[9:0]

    MaxOvershoot[5:0]

    BwValid

    FeedbackDivider

    LoopMeasurement

    Circuit

    Phase-FrequencyDetector DN

    ChargePump

    Voltage-ControlledOscillator

    Vco

  • 11

    Loop Measurement Circuit

    DD QQ DD QQ

    RefRiseRefRise

    RefFallRefFallVcoVco VcoVco

    RefClkRefClk

    DD QQ DD QQ

    StartRiseStartRise

    VcoVco VcoVco

    StartStart

    FbDiv[5:0]FbDiv[5:0]

    To Feedback

    Divider

    To Feedback

    Divider

    BwValidBwValid

    BwEnBwEn

    RefRiseRefRise

    Edge DetectorEdge Detector

    Edge DetectorEdge Detector

    From

    JTAG

    From

    JTAG

    Control

    Unit

    Control

    Unit

    N[5:0]N[5:0]

    N[5:0]+K[5:0]N[5:0]+K[5:0]

    StepEnStepEn

    DD QQ

    RefClkRefClk

    FbClkFbClkBBPDBBPD

    DD QQ

    VcoVco

    BwValidBwValid

    Tcrossover

    Detector

    Tcrossover

    Detector

    To JTAGTo JTAG

    RefRiseRefRise

    BBPD2BBPD2

    Load_BBPDLoad_BBPD

    CompareCompare

    FbCnt[5:0]FbCnt[5:0]

    RefRiseRefRise

    VcoVco

    DD QQ

    SmplCnt[5:0]SmplCnt[5:0]

    UpdateOSUpdateOS

    RefFallRefFall

    MaxOvershoot[5:0]MaxOvershoot[5:0]

    NewMaxOSNewMaxOSMaxOvershoot

    Detector

    MaxOvershoot

    Detector

    From

    Feedback

    Divider

    From

    Feedback

    Divider

    VcoVco

    FbRiseFbRise

    VcoVco

    ClrClr

    DD QQ DD QQ

    EnEn BBPD1BBPD1DD QQ

    VcoVco

    EnEn

    VcoVco

    EnEn

    CounterCounterBWBW BwCnt[9:0]BwCnt[9:0]QQ

    To JTAGTo JTAG

    DD QQEnEn

    Hold D

    until

    En=1

    Hold D

    until

    En=1

    EnEn EnEn

    Delay D

    until En=1

    Hold D

    until Clr=1

    Delay D

    until En=1

    Hold D

    until Clr=1

  • 12

    Control Unit

    VcoVco

    RefClkRefClk

    RefFallRefFall

    RefRiseRefRise

    StartStart

    StartRiseStartRise

    StepEnStepEn

    FbRiseFbRise

    BwEnBwEn

    DD QQ DD QQ

    RefRiseRefRise

    RefFallRefFallVcoVco VcoVco

    RefClkRefClk

    DD QQ DD QQ

    StartRiseStartRise

    VcoVco VcoVco

    StartStart

    FbDiv[5:0]FbDiv[5:0]

    To Feedback

    Divider

    To Feedback

    Divider

    BwValidBwValid RefRiseRefRise

    Edge DetectorEdge Detector

    Edge DetectorEdge Detector

    From

    JTAG

    From

    JTAG

    N[5:0]N[5:0]

    N[5:0]+K[5:0]N[5:0]+K[5:0]

    StepEnStepEn

    VcoVco

    FbRiseFbRise

    VcoVco

    ClrClr

    DD QQ DD QQ

    Hold D

    until

    En=1

    Hold D

    until

    En=1

    EnEn EnEn

    Delay D

    until En=1

    Hold D

    until Clr=1

    Delay D

    until En=1

    Hold D

    until Clr=1

    To Tcrossover DetectorTo Tcrossover Detector

    BwEnBwEn

  • 13

    Control Unit and Phase Step

    VcoVco

    RefClkRefClk

    BwEnBwEn

    BwCnt[9:0]BwCnt[9:0] 11 22 33 5544 66 77 88 99 1010 1111 1212 131300

    FbDiv[5:0]FbDiv[5:0] 88 881111

    FbClkFbClk

    FbCnt[5:0]FbCnt[5:0] 1100 22 33 44 55 66 77 00 11 22 33 44 55 66 77 88 99 1010 1100 22 33 44 55 66 77 0077

    StepEnStepEn

    DD QQ DD QQ

    RefRiseRefRise

    RefFallRefFallVcoVco VcoVco

    RefClkRefClk

    DD QQ DD QQ

    StartRiseStartRise

    VcoVco VcoVco

    StartStart

    FbDiv[5:0]FbDiv[5:0]

    To Feedback

    Divider

    To Feedback

    Divider

    BwValidBwValid RefRiseRefRise

    Edge DetectorEdge Detector

    Edge DetectorEdge Detector

    From

    JTAG

    From

    JTAG

    N[5:0]N[5:0]

    N[5:0]+K[5:0]N[5:0]+K[5:0]

    StepEnStepEn

    VcoVco

    FbRiseFbRise

    VcoVco

    ClrClr

    DD QQ DD QQ

    Hold D

    until

    En=1

    Hold D

    until

    En=1

    EnEn EnEn

    Delay D

    until En=1

    Hold D

    until Clr=1

    Delay D

    until En=1

    Hold D

    until Clr=1

    To Tcrossover DetectorTo Tcrossover Detector

    BwEnBwEn

  • 14

    Bandwidth/Tcrossover Test

    BwEnBwEn

    DD QQ

    RefClkRefClk

    FbClkFbClkBBPDBBPD

    DD QQ

    VcoVco

    BwValidBwValid

    To JTAGTo JTAG

    RefRiseRefRise

    BBPD2BBPD2

    Load_BBPDLoad_BBPD

    EnEn BBPD1BBPD1DD QQ

    VcoVco

    EnEn

    VcoVco

    EnEn

    CounterCounterBWBW BwCnt[9:0]BwCnt[9:0]QQ

    From Control UnitFrom Control Unit

    RefClkRefClk

    BwCnt[5:0]BwCnt[5:0]

    Load_BBPDLoad_BBPD

    FbClkFbClk

    BBPDBBPD

    BBPD1BBPD1

    BBPD2BBPD2

    BwValidBwValid

    VcoVco

    4646 4747 4848 4949 5050 5151 5252 5353 5454 5555 5656 5757 5858 5959 60604444 4545

  • 15

    Peaking/MaxOvershoot Test

    RefClkRefClk

    FbCnt[5:0]FbCnt[5:0] 11 22 33 44 55 66 77 00 11 22 33 44 55 66 77 00 11 22 33 44 55 66 77 00 11 22 33 44

    33 4422 33 22SmplCnt[5:0]SmplCnt[5:0]

    RefFallRefFall

    RefRiseRefRise

    VcoVco

    UpdateOSUpdateOS

    4400MaxOvershoot[5:0]MaxOvershoot[5:0] 33

    CompareCompare

    FbCnt[5:0]FbCnt[5:0]

    RefRiseRefRise

    VcoVco

    DD QQ

    SmplCnt[5:0]SmplCnt[5:0]

    UpdateOSUpdateOS

    RefFallRefFall

    MaxOvershoot[5:0]MaxOvershoot[5:0]

    NewMaxOSNewMaxOS

    From

    Feedback

    Divider

    From

    Feedback

    DividerTo JTAGTo JTAG

    DD QQEnEn

    BwValidBwValid

  • 16

    Outline

    Motivation

    Loop Measurement Circuit

    Algorithm

    Architecture

    Silicon Results

    Conclusion

  • 17

    Simulations vs. Measurements

    100 MHz refclk, feedback divisor = 50 (2x25)

    CaseRlpf(kW)

    Icp(A)

    Bandwidth (MHz) Peaking