A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration

A 10 Gb/s 0.25 lm SiGe modulator driverfor photonic-integration

Bernhard Goll • Horst Zimmermann

Received: 22 February 2013 / Revised: 27 September 2013 / Accepted: 14 November 2013 / Published online: 23 November 2013

� Springer Science+Business Media New York 2013

Abstract A 10 Gb/s modulator driver in SiGe 0.25 lm

BiCMOS technology with a chip area of only 0.54 mm2 is

presented. The intentions of designing this modulator driver

are to amplify small incoming data signals at 10 Gb/s and to

integrate the driver together with a silicon optical phase

modulator (Mach–Zehnder modulator in push–pull config-

uration) on the same chip. The driver is designed to have a

low power-consumption of 0.68 W but a high gain

(S21 = 37 dB). It consists of a differential pre-amplifier

with common-mode feedback and automatic gain control,

which is supplied by 2.5 V. The differential output stage is

supplied with 3.5 V. The driver is designed to drive a Mach–

Zehnder modulator, which uses in his arms carrier depletion

in a reverse biased pn junction to adjust the refractive index.

The differential output (5Vpp) delivers two times a voltage

between 0 and 2.5 V. Therefore no bias-T is needed at the

output to assure that the diodes of the interferometer arms

are in the reverse biased mode. In addition to the low-power

design, a passive network instead of an additional amplifier

circuit for driving the cascode transistors, which reduce the

collector–emitter voltage of each transistor in the output

stage below breakdown, is presented. According to bit-

error-ratio (BER) measurements with a pseudo-random-bit-

sequence with the length of 231 - 1 the BER is better than

10-12 for input voltage differences down to 50 mVpp. The

rise/fall time (20–80 %) is 45/30 ps respectively.

Keywords Modulator driver � 0.25 lm SiGe

BiCMOS � Low power � High gain � Analog circuit

design � 10 Gb/s

1 Introduction

Optical data transmission at 10 Gb/s (e.g. ethernet standard)

and beyond is a well established technology and multi-

channel transmission systems have been demonstrated [1].

For the design of functional blocks as well as whole trans-

ceiver, a competitive option is their implementation in a

common silicon process based on experience in BiCMOS or

CMOS technologies due to widespread integrated circuit

foundries [2–4]. A fully integrated 4 9 10 Gb/s dense

wavelength division multiplex (DWDM) optoelectronic

transceiver with Mach–Zehnder modulator and a fully inte-

grated 25 Gb/s transceiver with photonic microring resona-

tor modulator in 0.13 lm SOI CMOS is presented in [5] and

[6], respectively. Even at lower data rates at e.g. 10 Gb/s

optimizations on different optical as well as electrical

building blocks are still going on. So different electrical

circuit blocks like e.g. laser drivers for direct modulation [7,

8] or drivers for signal amplification, e.g. a driver for a low-

voltage differential signaling (LVDS) digital standard [9]

which usually are designed in a fast SiGe BiCMOS process

can be combined with silicon photonics elements. Silicon

optical phase modulators based on carrier depletion were

demonstrated in [10–12]. For data transmission at 10 Gb/s

reverse bias voltages of only 5 V are sufficient to achieve an

extinction ratio of [5 dB at a distinct operation point of a

phase modulator. As a consequence an appropriate electric

modulator driver has to deliver a data signal with&5Vpp. If a

modulator is designed as a Mach–Zehnder interferometer in

push–pull configuration, the driver has to deliver a

B. Goll (&) � H. Zimmermann

Institute of Electrodynamics, Microwave and Circuit

Engineering, Vienna University of Technology, Gusshausstrasse

25/354, 1040 Vienna, Austria

e-mail: [email protected]

H. Zimmermann

e-mail: [email protected]

123

Analog Integr Circ Sig Process (2014) 79:15–25

DOI 10.1007/s10470-013-0235-3

differential data stream, where each single-ended part

switches between 0 and 2.5 V. There exist several 10 Gb/s

modulator drivers in SiGe BiCMOS technology in the lit-

erature. In [14] a modulator driver with a feedback network

for a breakdown voltage doubler was introduced to over-

come the limit of collector–emitter breakdown voltage. A

driven cascode circuit with compensation capacitance to

overcome the breakdown limit is presented in [15]. Another

driven cascode is used in a modulator driver in [16] to

achieve a high differential output voltage of 10Vpp but at a

low data rate of 3.4 Gb/s. A high data rate of 23 Gb/s was

achieved in [17], where an optimization regarding parasitic

inductances has been done. A 10 Gb/s differential, distrib-

uted modulator driver in 0.18 lm SiGe-BiCMOS, where

instead of the input transmission line a digital phase-shifting

is implemented was proposed in [18]. The output swing

amounted to 6Vpp, the total power consumption was 2.13 W

and 2.8 mm2 chip area was needed.

In this paper the more detailed description of a modulator

driver in a 0.25 lm SiGe BiCMOS (IHP SG25H3 with ftmax

&120 GHz, BVCE0 = 2.2 V) technology is presented

including its automatic gain control (AGC) and its common-

mode feedback (CMFB) with additional simulation and mea-

surement results, whereas a short and non-detailed description

of only the pre-amplifier and the output stage without the device

sizes and resistor as well as capacitance values, tail-currents,

emitter-areas and passive components can be found in the short

letter [13]. Furthermore the measurement results are treated in

more detail (additional diagrams with BER measurements and

S11/S21 measurements) in this paper. The driver is capable of

driving the modulators proposed in [10] and [11]. For the driver

design the focus has been set to achieve a high gain

(S21 = 37 dB) as well as a low power consumption (0.68 W)

and a low chip area of 0.54 mm2 for driving the long electrode

lines of the modulator (up to 3 mm), which are each terminated

with their characteristic impedance of 50 X. Modulator drivers

for smaller modulators like e.g. some types of microring

modulators (e.g. in [12]) only have to drive an electrode with its

small capacitive loads thus consuming much less power (but it

should be noted that microring resonators have other severe

disadvantages). Additionally in the design no inductances for

enhancing the bandwidth with inductive shunt peaking are

implemented because for 10 Gb/s they usually consume a

considerable chip area. Because each voltage of the inverted

and non-inverted part of the differential output switches

between 0 and 2.5 V, the driver does not need an additional

bias-T to drive the diodes in the modulator in reverse operation.

2 Circuit description

A block diagram of the whole modulator driver is depicted

in Fig. 1. The presented modulator driver implements a pre-

amplifier stage, where the amplification is controlled with an

AGC and where the common-mode level is regulated with a

CMFB circuit. The reference block RB (simulated power

consumption of 19 mW) delivers bias voltages like RE-

FAGC and REFCM and bias currents to the different circuit

blocks. It consists of a standard bandgap reference and an

additional voltage regulator to generate all bias- and refer-

ence voltages. An output stage is implemented to generate a

fully differential output data stream with 5Vpp for an

external 50 X system.

2.1 Pre-amplifier

The pre-amplifier stage is supplied with VCC1 = 2.5 V and

the schematic is depicted in Fig. 2. The data signal to be

amplified is applied to the input pads IN? and IN-, which

are connected to the first differential amplifier consisting of

transistors T1, T2 and resistors R1 and R2. The amplified

differential data signal OT1? and OT1- is buffered and

level-shifted by emitter followers (transistors T3, T4 with

resistors R5, R6 respectively) and applied to transistors T5,

T6 of the second differential amplifier (see Fig. 2). Capac-

itors C1 and C2 avoid peaks in the collector–emitter voltage

of T5 and T6 but have the disadvantage of a slight decrease

in bandwidth. The amplified data signal at nodes OT2? and

OT2- is level shifted again with emitter followers (tran-

sistors T7, T8 and resistors R11 and R12) and builds with

nodes INT2? and INT2- the input nodes for the following

output stage. Additionally nodes INT1? and INT1- are

connected to the output stage to deliver a second differential

data signal to drive the cascode transistors T11, T12 for

voltage doubling to overcome the breakdown voltage limit

of the fastest bipolar transistor (BVCE0 & 2.2 V) available

in the process used. All bipolar transistors used as emitter

followers have a smaller transit frequency (45 GHz), which

is still enough for 10 Gb/s but a higher collector–emitter

breakdown voltage of BVCE0 &4.5 V. The simulated power

consumption of the pre-amplifier excluding the two 50 X

VEE

IN+

CMFB

IN-

AGC

VCC1

INT1+

INT1-INT2-

INT2+

RB

Cur

Mirr

REFCM

REFAGC

BIAS1

VCM

VEE

50Ω 50Ω

VEE VEEchar

acte

ristic

impe

danc

esof

ele

ctro

des

(50

)Ω

OUT+

OUT-

VCC2

VEE

CM

OT

1+O

T1-

Pre-amplifier Output stage

VEE

VEE

VCC1

VCC1

VEE

VCC1

BIASOPA1,2

IDC

Fig. 1 Block diagram of the modulator driver

16 Analog Integr Circ Sig Process (2014) 79:15–25

123

matching resistors at nodes IN?/IN?, the CMFB amplifier,

RB and AGC amounts to 72.5 mW.

2.2 AGC

The AGC is added to the circuit to reduce continuously the

amplification of the first differential amplifier if an input volt-

age difference (nodes IN?/IN-) is larger than 100 mVpp (see

Fig. 3). This is done to reduce voltage peaks in the first stage of

the pre-amplifier if large input voltage differences are applied.

The operational amplifier OPA1 is a buffer to avoid a too large

load at nodes OT1? and OT1-. OPA1 is a fast voltage buffer

with a 3 dB cut-off frequency of f-3dB = 24 GHz but with a

simulated DC voltage gain of only 3 dB (it so happened that for

OPA1 f-3dB is equal to its transit frequency). This low gain is

enough when considering that the AGC starts to work for dif-

ferential input voltages at IN?/IN- of 100 mVpp (corresponds

to&1Vpp at nodes OT1?/OT1-) and that the main focus of the

design was a low influence to nodes OT1?/OT1-. OPA1

consists of the fastest SiGe bipolar transistors available in this

process, where its input differential stage (MN2, T21, T22,

R27–R30, C12, C13) is designed with transistors of minimum

emitter area (AE1 = 0.353 lm2) to have a small load at nodes

OT1? and OT1- for fast operation of the modulator driver.

The differential amplifier stage uses emitter degeneration (R27,

R28) with decoupling at high frequencies by C12, C13 to enhance

the bandwidth. After buffering with two stages (T23, R21, R33

and T24, R32, R34 having in front of them diode connected NPN

transistors for level shifting) the differential output data signal

OP1? and OP1- is applied to transistors T25, T26 and

capacitor C14 as well as resistor R35, which act as a peak

detector. The voltage at node AMP, which is stored in C14,

corresponds to the maximum voltage at OT1? or OT1-. R35

introduces an additional time constant of &120 ns when dis-

charging C14 (R35 = 100 kX, C14 & 1.2 pF). The amplifier

OPA2 compares the potential at AMP with a reference voltage

REFAGC and adds current via transistor MP2 to transistor T27,

which is in diode connection and forms the input side of a

current mirror with TCS1 at its output side. OPA2 is a simple

two-stage standard operational amplifier with CMOS transis-

tors and Miller compensation. The simulated DC gain is 55 and

the 3 dB cut-off frequency is f-3dB = 0.28 MHz. A constant

current IDC (see Fig. 3) of 0.45 mA defines a minimum

amplification for large input voltage differences. With a current

mirror multiplication factor of nine, the collector current in

TCS1 can be found. For small input voltage differences of the

input data signal OPA2 turns MP2 on and the maximum

amount of current is mirrored from T27 (Fig. 3) to transistor

TCS1 in Fig. 2 (See node CurMirr in Figs. 2, 3.), because node

AMP is 0.2 V lower in its potential than the reference voltage

REFAGC. This ensures a stable low potential (low-ohmic) near

to VEE at the output of OPA2 thus VAGC is low and MP2

delivers maximum current. The maximum gain is available for

the first stage in Fig. 2. For small amplitudes this gain is not

high enough to drive the output of OPA2 away from this low

potential and the AGC is turned off.

The simulated step response for the AGC at 10 Gb/s is

depicted in Fig. 4, where at IN? a DC voltage of 1.25 V

was applied while at IN- the data signal overlaid at 1.25 V

DC offset performed a step response from 25 to 500 mVpp.

The settling time for an error lower than 1 % of the final

value is 1.55 ls. The simulated power consumption of the

AGC amounts to 14.5 mW.

2.3 CMFB

A CMFB is implemented to the first differential amplifier

stage of the pre-amplifier stage (see Figs. 1, 2) to ensure a

constant common-mode voltage of &1.8 V at nodes OT1?

and OT1- if different common-mode voltages are applied at

VEE

IN+

CMFB

IN-

AGC

VEE VEEVEE VEE VEE

VCC1 VCC1 VCC1 VCC1 VCC1VCC1

T1 T2

T3

T4

T5 T6 T7

T8

INT1+

INT1-

INT2-

INT2+

CMOT1-

OT1+ OT2+ OT2-R1

TCS1

R2R3 R4

R5 R6

MN1

R7 R8

R9 R10

R11 R12

C1 C2

RB

CurMirr

MP1

RE

FC

M

RE

FAG

C

BIAS1

VCM

VEE

50 50

~10mA 12mA

1mA1mA

2.5mA 2.5mA

AE1 AE1

AE2

AE2

AE2

10 E1 10 E1

AE2

AE2

Fig. 2 Pre-amplifier stage of

the modulator driver. The unit

emitter area of the fast

transistors (T1, T2, T5, T6 with

BVCE0 = 2.2 V) is

AE1 = 0.353 lm2 and

AE2 = 0.493 lm2 for the slow

transistors (T3, T4, T7, T8,

TCS1 with BVCE0 = 4.5 V).

R1,2 = 120 X, R3,4 = 4 kX,

R5,6 = 1 kX, R7,8 = 11 X,

R9,10 = 25.3 X,

R11,12 = 600 X, C1,2 = 250 fF

Analog Integr Circ Sig Process (2014) 79:15–25 17

123

IN? and IN-. The common-mode voltage is measured at

node CM and then adjusted via a feedback loop with transistor

MP1. A detailed circuit of CMFB can be seen in Fig. 5. The

CMFB circuit consists of a simple operational CMOS

amplifier (OPA3) with Miller compensation, where transistor

MP6 limits the maximum output voltage at node VCM. OPA3

VEE VEE

VCC1 VCC1

T26

T25

R35C14

OT1+OT1-

AMP

VEE

C15

R36

VEE

VCC1

VAGC

OPA1

OPA2

T27

MP2

I DC

VCC1 VCC1

VEE

MN2

BIASOPA1VEE VEE

VCC1 VCC1

T21

T22T23

T24

VEE

VCC1

R27

R28C12

C13

R29 R30 R33 R34

OP1+

OP1-

R31 R32

REFAGC

CurMirr

BIASOPA2

AE1

AE1

AE1 AE1

AE1

AE1

AE1

AE1

AE2

1mA 1.1mA 1.1mA

1.2mA

max.1.4mA

Fig. 3 Automatic gain control

(AGC) in the pre-amplifier (fast

bipolar transistors with

AE1 = 0.353 lm2 and

BVCE0 = 2.2 V, and slow

bipolar transistors with

AE2 = 0.493 lm2 and

BVCE0 = 4.5 V) and its

simulated influence to the

voltage gain of the first stage in

the pre-amplifier in Fig. 2.

R27,28 = 250 X,

R29,30 = 400 X,

R31,32 = 650 X,

R33,34 = 900 X,

C12,13 = 120 fF,

R35 = 100 kX, C14 & 1.2 pF

Fig. 4 Simulated step response

of the AGC at 10 Gb/s for

IN? = 1.25 V DC and IN-

= 1.25 V with the overlaid data

signal. The amplitude of the

input data signal performs a step

from 25 to 500 mVpp


123

is designed to have a DC voltage gain of 39 and a 3 dB cut-off

frequency of 18 MHz (considering a capacitive load of 2 pF).

With capacitors C16–C18 OPA3 is used as an integrator circuit.

The response of a step of the input common-mode voltage

from 1.75 to 1.25 V can be seen in Fig. 6. The time constant of

the feedback loop amounts to&130 ns. The simulated power

consumption of the CMFB circuit amounts to 7 mW.

2.4 Output stage

The schematic of the output stage of the modulator driver is

depicted in Fig. 7

The supply voltage of the output stage amounts to

VCC2 = 3.5 V. The differential data signal INT2? and

INT2-, which is incoming from the pre-amplifier stage, is

applied to transistors T9 and T10 for amplification.

Resistors R13 and R14 set the operating point and somewhat

degenerate the small-signal amplification at low frequen-

cies. At high frequencies capacitor C4 enhances the band-

width by decoupling these resistors. Capacitor C3 is added

to reduce peaks in the collector–emitter voltages of tran-

sistors T9–T12 with the drawback of a small decrease of

the bandwidth. T11 and T12 are the driven cascode tran-

sistors, where at the bases the data signals INT1- and

INT1? respectively, which are delivered by the pre-

amplifier stage, are applied. By doing this the voltage at

node AP? is divided to the collector–emitter voltages of

series-connected transistors T9 and T11 and to a small part

to the voltage drop across resistor R13. In a similar way the

voltage at AP- is divided to T10, T12 and R14. The

amplified differential data signals AP? and AP- are level

shifted with emitter followers T13, R17, R19 and T14, R18,

R20 respectively. Capacitors C5 and C6 bypass the emitter

followers and enhance the bandwidth. The generated sig-

nals APD?, APD- are applied to transistors T15 and T16

for amplification, which are the dominating transistors in

the output stage. Cross-coupled capacitors C7, C8 between

the collectors of T16 and T15 resp. and nodes APD? and

APD- resp. are added to somewhat decrease the rise- and

fall time by a few ps of the data signals at nodes AP2?

and AP2- thus lowering the voltage peaks of the

Fig. 5 Schematic of the CMFB amplifier

Fig. 6 Step response of the

common-mode voltage at nodes

OT1?/OT1- (simulated at

node CM) and signal VCM

when a common-mode jump

from 1.75 to 1.25 V is applied

to the input (nodes IN?/IN-) at

10 Gb/s data rate


123

collector–emitter voltage of transistors T17 and T18. These

peaks occur due to different switching times between nodes

AP2? and AP2I? or AP2- and AP2I- respectively. C7

and C8 (200 fF) are chosen to be too small to considerably

increase the bandwidth or to cause instabilities. Instability

considerations of so-called negative miller-capacitances

(NMCs) and their positive influence to the large signal

behavior in reducing the effective input impedance under

certain conditions are treated in [19]. Another problem is

the saturation voltage of bipolar transistors, which can

amount between 0.3 and 0.4 V. So in the design care has to

be taken to use the full collector–emitter voltage range

headroom between the saturation voltage and BVCE0

&2.2 V. Usually it is avoided to drive a transistor into

saturation but as a trade-off between voltage-headroom and

speed a small saturation effect may be tolerable.

To include all these considerations and to furthermore

save power, a passive network without amplification tran-

sistors is used to drive transistors T17 and T18 at their

bases with the help of nodes AP? and AP-. The simulated

waveforms can be seen in Fig. 8. The DC base current for

e.g. transistor T17 is defined here mainly with resistor R21.

If T15 turns on (The operation point is set at node APD-)

node AP2I? is pulled very close to the saturation voltage

of T15 and a large collector current flows, which is also

defined by resistor R25 (note that T15 = T17). Due to the

fact that AP- is currently in the high state and node API-

is pulled to low (via the base–emitter diode of T17) the

voltage difference AP- minus API- and R25 defines the

higher base current and also the collector–emitter voltage

of T17 is close to saturation. In the other case, when

transistor T15 turns off the potential at AP2I? is limited by

the potential at node API- via the base–emitter voltage of

T17. Because only a negligible collector current flows

through T15 and T17 the base current of T17 is low and the

potential at API- is mainly defined by AP-, which is

currently at low state. Transistors T16 and T18 are the

differential counterpart to transistors T15 and T17 and are

working in a similar way. Capacitors C9 and C10 form

capacitive dividers together with the base–emitter capaci-

tances of T17 and T18, respectively, including capacitor

C11 to increase the bandwidth at nodes API- and API?

and to improve the dynamic behavior. Capacitor C11 is also

added to avoid further voltage peaks exceeding the col-

lector–emitter breakdown voltages of T17 and T18. In

Fig. 8 it can be seen that the collector–emitter voltages of

T15 and T17 are \1.7 and 2.1 V, respectively, which is

well below BVCE0 &2.2 V.

Fig. 7 Schematic of the output

stage of the modulator driver

(AE1 = 0.353 lm2 for fast

transistors and

AE2 = 0.493 lm2 for slow

transistors): R13,14 = 30 X,

R15,16 = 68 X, R17,18 = 520 X,

R19,20 = 880 X, R21,22 = 1 kX,

R23,24 = 100 kX, C3 = 20 fF,

C4 = 2pF, C5,6 = 800 fF,

C7,8 = 200 fF, C9,10 = 200 fF

Fig. 8 Simulated transients at the nodes of the modulator driver’s

output stage


123

The final differential data signal at nodes AP2?, AP2-

is level shifted by the emitter followers T19 and T20,

which drive the modulator electrodes’ characteristic

impedance of 50 X. The bipolar transistors (T13, T14, T19,

T20) used as the emitter followers have similar to those in

the pre-amplifier stage a smaller transit frequency, which is

still enough for 10 Gb/s but a higher collector–emitter

breakdown voltage of BVCE0 &4.5 V. A simulation of the

final data signals at the outputs OUT? and OUT- at

10 Gb/s can be seen in Fig. 9. The inverted data signal

(OUT-) as well as the non-inverted data signal (OUT?)

switch between 0 and 2.5 V (differential 5Vpp) so that the

diodes in the modulator arms are always in reverse oper-

ation (no bias-T is needed for the signal part of modulator).

Typically in the modulator arms additional diodes in

reverse operation are implemented with which the optical

operation point of the phase modulator can be adjusted by

tuning the phase shift with an additional external DC

voltage. The simulated power consumption of the output

stage including the load of two 50 X resistors amounts to

602 mW.

3 Measurement results

A test chip of the modulator driver has been fabricated in a

0.25 lm SiGe BiCMOS technology in ‘‘low-speed’’ ver-

sion IHP SG25H3 (ftmax & 120 GHz, BVCE0 = 2.2 V)

(see Fig. 10). The modulator driver chip has a size of

0.54 lm2. For test purposes the test chip has been bonded

to a PCB and supplied with VCC1 = 2.5 V, VCC2 = 3.5 V.

The chip contains four pads for each supply voltage and

several pads for the ground connections. To reduce the

influence of the parasitic inductances of the bond wires,

eight wires are bonded to the PCB for VCC1 as well as for

VCC2 each. For the ground connection as many wires as

possible have been connected to the chip. To connect one

signal pad to the PCB, two wires were bonded in parallel.

At IN- a DC voltage of 1.25 V and at IN? a 10 Gb/s

pseudo-random bit-sequence PRBS 231 - 1 with a DC bias

of 1.25 V has been applied. The measured eye diagram and

for comparison simulated ones are shown in Fig. 11 for

100 mVpp (measured eye diagrams) and 50 mVpp (simu-

lated eye diagrams) differential input voltage respectively.

The jitter in the measured eye diagram in Fig. 11 is mainly

caused by data dependent jitter in the rising and falling

edge, because the circuit, where several capacitors to

compensate the frequency behavior are added, shows a

slightly slower behavior than in the simulation. Another

reason is the fact that the saturation voltage of a bipolar

transistor is &0.35 V. Transistors T15–T18 show small

saturation effects when they are turned on. This has an

additional influence to the rising edge of the data signals.

Nevertheless the eye of the signal at node OUT? shows a

wide opening with a voltage swing of 2.5 V (corresponds

to 5Vpp differential). The influence of the load of the bases

of the large output transistors T19 and T20 on nodes AP2?

and AP2-, respectively, results to a slight ramp in the

roofs of the eyes in Fig. 11.

A rising voltage of e.g. AP2? has as a consequence a

higher emitter current of T19 and hence the base current,

which consists of a static part and a dynamic part caused by

voltage switching, is rising. Another influence of T19 (or

T20) to node AP2? (or AP2-) is the voltage dependent

base–collector capacitance, which tends to increase when

the voltage at AP2? rises.

Bit-error-ratio (BER) measurements with a PRBS

231 - 1 data signal have resulted in a BER \10-12 for

input voltage differences down to 40 mVpp (see Fig. 12).

Fig. 9 Simulated data signal (10 Gb/s) at the output nodes OUT?

and OUT- of the modulator driver, when an input data signal of

100 mVpp with 1.25 V common-mode bias is applied at IN? and a

reference voltage of 1.25 V at IN-

Fig. 10 Layout plot (top) and chip photo (bottom) of the modulator

driver


123

The measured power consumption amounts to 680 mW

in contrast to the simulated 715 mW for the modulator

driver (including 2 9 50 X load at the output nodes

OUT?/OUT- but excluding 2 9 50 X termination at the

input nodes IN?/IN-).

For S-parameter measurements the chip has been wire-

bonded to a PCB but where the signal pads (IN?/IN-,

OUT?/OUT-) have been kept unconnected to place

Z-probes on these pads in a wafer prober. Measurements were

performed with a R&S ZVM vector network analyzer

(10 MHz to 20 GHz) where for calibration (TOSM) a CSR-3

calibration substrate has been used. Due to AC measurements

(magnitude of measured S21 and S11 see Fig. 13) for small

input voltage differences, where the AGC has not turned on,

the modulator driver has a maximum S21 of 37 dB with a 3 dB

cut-off frequency of f-3dB = 7.1 GHz The resonance effect at

*12 GHz is caused by capacitors C7 and C8 in Fig. 7, which

are connected in positive feedback. The single peaks at 1 and

2 GHz are most likely measurement obstacles (parasitic line

effects) caused by an old, not perfect calibration substrate.

Fig. 11 Measured (100 mVpp

data signal at the input) and

simulated (50 mVpp data signal

at the input) eye diagrams at the

output nodes OUT? and OUT-

Fig. 12 Measured BER versus the differential input voltage for two

input common-mode voltages


123

Influences of bond wires are less likely, because when bonding

the chip to the test PCB, care has been taken for short bond

wires and block capacitors as near as possible to the chip. A

rough estimation (inductance, on-chip block capacitors)

would give influences around 10 GHz. The measured rise/fall

times (20–80 %) are 45/30 ps. The longer rise time is another

indication of a small saturation effect in T15–T18.

4 Comparison and conclusion

A test chip of a modulator driver with a chip area of

0.54 mm2 in a 0.25 lm SiGe 120 GHz-BiCMOS process

has been presented. The driver consists of a pre-amplifier

stage with AGC and CMFB, which is supplied with 2.5 V

and an output stage, which is supplied with 3.5 V. At the

Fig. 13 AC characteristic (magnitude of S21 and S22) for small input

voltage differences at 1.25 V input common-mode voltage

Table 1 Comparison related to design parameters power consumption and gain of the modulator driver used

Publ. Technology Data rate

Input swing (eye)

Output swing (eye)

Suppl. volt.

Power

consumption

AC gain

f-3dB

Load Driver chip

area (mm2)

[5] 0.13 lm CMOS SOI 10 Gb/s (meas.)

50 mVpp for 4 dB ER (sim.)

5Vpp nominal (sim.)

(inductive peaking

in every stage)

1.5 V, 5 V

575 mW

N/A 2 9 50 X N/A

[6] 0.13 lm CMOS SOI 25 Gb/s (meas.)

200 mVpp

&2.8Vpp (sim.) 6.9 dB

ER (meas.) (inductive

peaking in the last stage)

1.2 V, -1.5 V

to 1.5 V

207.6 mW

N/A Capacitive load of

photonic ring resonator

(Ø15 lm, &50 fF)

N/A

[14] 0.35 lm SiGe BiCMOS 10 Gb/s

500 mVpp

9Vpp

5 V

1 W

N/A 2 9 50 X 0.56


500 mVpp

8 Vpp

-6.5 V

3.7 W

N/A 2 9 50 X 1.2

[16] 0.25 lm SiGe BiCMOS 3.4 Gb/s

300 mVpp

max. 12Vpp

5.2V, 8 V

1.6 W

N/A 2 9 50 X 0.6

[17] SiGe bipol. 0.3 lm eff. emitter width 23 Gb/s

0.6Vpp to 0.8Vpp

7Vpp

0 V to -5 V,

2.8 V to -5 V

2.5 W

N/A 2 9 50 X 0.7828

[19] 0.25 lm 180 GHz-SiGe BiCMOS 40 Gb/s

0.6Vpp

6Vpp

4 V, 5.5 V

1.35 W

13 dB

33.7 GHz

2 9 50 X 0.72


–

2.5Vpp

5 V

0.75 W

– 50 X 0.7

This work 0.25 lm 120 GHz-SiGe BiCMOS 10 Gb/s (meas.)

50 mVpp (sim.)

100 mVpp (meas.)

5Vpp (meas.)

2.5, 3.5 V

0.68 W

37 dB

7.1 GHz

2 9 50 X 0.54

The most significant results of our work are written in bold

ER extinction ratio of optical output of a transceiver, sim. simulated, meas. or no comment measured


123

outputs a differential data stream with 5Vpp is delivered.

Because the differential output delivers two times a voltage

swing of between 0 and 2.5 V, no bias-T is needed and the

modulator driver can be connected directly to the elec-

trodes of a silicon Mach–Zehnder modulator in push–pull

configuration, because the diodes in the interferometer

arms are always in reverse operation. The focus in the

design has been also set to a low supply voltage and hence

a low power consumption, which amounts to 680 mW in

contrast to simulated 715 mW. To save additional active

transistor stages in the output stage a passive network

without additional bipolar transistors to control the cascode

transistors has been used. Another design goal was a high

AC gain, which results to S21 = 37 dB (f-3dB = 7.1 GHz).

In Table 1 a comparison with the literature related to

the considered design parameters (gain and power con-

sumption) is given. In some publications the AC gain has

not been measured, but a hint may be given by comparison

of the input and output voltage swing for the different eye

diagrams. Considering the measured small-signal stray-

parameter of S21 = 37 dB and the large-signal behavior

that a full-swing eye-diagram (Vpp = 5 V) was achieved

by a low input voltage difference of 100 mVpp, this is a

considerably better result. The power consumption of

0.68 W is lower than in most of the other works, but

depends also on the load, which will be driven. It is

apparent that the driver for the active microring resonator

in [6] with a load capacitance of 50 fF only, consumes less

power and therefore less chip area than the driver for a

Mach–Zehnder modulator in push–pull configuration

(typical length of 2–3 mm of electrodes), where two times

the termination of an electrode line (50 X) and additionally

the capacitances of the diodes in reverse operation have to

be driven. A Mach–Zehnder modulator in push–pull con-

figuration, however has the advantage compared to mic-

roring resonators of a theoretical chirp-free operation, more

than a factor of 100 higher bandwidth and a lower sensi-

tivity to process tolerances and temperature [20]. A slightly

lower power consumption of a Mach–Zehnder modulator

driver has been reported in [5]. Nevertheless they use

inductive peaking with integrated inductors in every

amplifier stage to meet bandwidth requirement and this

tends to increase the chip area. Another factor in CMOS

processes is the lower gain of MOS transistors compared to

bipolar transistors. So a large gate width has to be imple-

mented for an appropriate drain current and higher gain

(in small-structure CMOS processes the velocity saturation

of charge carriers further reduces the gain) which increases

the chip area needed. A trade-off in the low-power design

of the presented modulator driver may be the rise-/fall-time

(20–80 %), which amounts to 45 and 30 ps respectively.

This is slightly worse than in some publications, but

enough for well open eye diagrams (see Fig. 11) to

integrate the driver together with a 10 Gb/s silicon Mach–

Zehnder modulator on a photonic-electronic chip.

Acknowledgments The authors would like to thank L. Zimmer-

mann and B. Tillack at IHP GmbH, Germany for chip production and

H. Porte at Photline Technologies for support. This work was partially

funded in the European project HELIOS (FP7-224312).

References

1. Kuchta, D. M., Kwark, Y. H., et al. (2004). 120-Gb/s VCSEL-based

parallel-optical interconnect and custom 120-Gb/s testing station.

IEEE Jourunal of Lightwave Technology, 22(9), 2200–2212.

2. Rein, H.-M. (1996). Design considerations for very-high-speed

SI-bipolar IC’s operating up to 50 Gb/s. IEEE Journal of Solid-

State Circuits, 31(8), 1076–1090.

3. Liu, A., Liao, A., et al. (2008). In IEEE Asia-Pacific microwave

photonics conference on optical silicon modulator and photonic

integration, pp. 295–297.

4. Vacondio, F., Mirshafiei, M., et al. (2010). A silicon modulator

enabling RF over fiber for 802.11 OFDM signals. IEEE Journal

of Selected Topics in Quantum Electronics, 16(1), 141–148.

5. Narasimha, A., Analui, B., et al. (2007). A fully integrated 49

10-Gb/s DWDM optpelectronic trasceiver implemented in a

standard 0.13 lm CMOS SOI technology. IEEE Journal of Solid-

State Circuits, 42(12), 2736–2744.

6. Buckwalter, J. F., Zheng, X., et al. (2012). A monolithic 25-Gb/s

transceiver with photonic ring modulators and Ge detectors in a

130-nm CMOS SOI process. IEEE Journal of Solid-State Cir-

cuits, 47(6), 1309–1322.

7. Tsai, C. -M., & Huang, L. -R. (2003). 10 Gb/s single-ended laser

driver in 0.35 lm SiGe BiCMOS technology. In IEEE European

conference on solid-state circuit, pp. 289–292.

8. Rein, H.-M., Schmid, R., et al. (1994). A versatile Si-bipolar

driver circuit with high output voltage swing for external and

direct laser modulation in 10 Gb/s optical-fiber links. IEEE

Journal of Solid-State Circuits, 29(9), 1014–1021.

9. Abugharbieh, K., Krishnan, S., et al. (2010). An ultralow-power

10-Gbits/s LVDS output driver, IEEE transactions on circuits and

systems I: Regular papers, Vol. 57, No. 1, pp. 262–269.

10. Thomson D. J., Gardes, F. Y., et al. (2011). Silicon based optical

modulation within the HELIOS project. In Proceedings of SPIE

photonic west, 7943, 794316.

11. Ziebell, M. Rasigade, G., et al. (2011). Large extinction ratio

10 Gbit/s silicon optical modulator based on a reverse biased

PIPIN diode, international conference on information photonics,

pp. 1–2.

12. Dong, P., Liao, S., et al. (2010). High speed silicon microring

modulator based on carrier depletion (pp. 1–3). Communication

(OFC)/NFOEC: Optical Fiber.

13. Goll, B., & Zimmermann, H. (2012). 10Gbit/s SiGe modulator

driver with 37 dB gain and 680 mW power consumption. IET

Electronic Letters, 48(15), 938–940.

14. Li, D.-U., & Tsai, C.-M. (2005). Efficient breakdown voltage

doubler for 10Gbit/s SiGe modulator drivers. IET Electronic

Letters, 41(3), 126–127.

15. Mandegaran, S., & Hajimiri, A. (2007). A breakdown voltage

multiplier for high voltage swing drivers. IEEE Journal of Solid-

State Circuits, 42(2), 302–312.

16. Ostrovskyy, P., Gustat, H., et al. (2010). A 10 Vpp SiGe voltage

driver. In 20th international crimean conference CriMiCo,

pp. 109–110.


123

17. Schmid, R., Meister, T. F., et al. (1999). SiGe driver circuit with

high output amplitude operating up dp 23 Gb/s. IEEE Journal of

Solid-State Circuits, 34(6), 886–891.

18. Zhao, Y., Vera, L., Long, J. R., & Harame, D. L. (2013). A

10 Gb/s 6 Vpp differential modulator driver in 0.18 lm SiGe-

BiCMOS. In IEEE international conference on solid-state cir-

cuits, pp. 132–133.

19. Knochenhauer, C., Scheytt, J. C., & Ellinger, F. (2011). A

compact, low-power 40-GBit/s modulator driver with 6-V dif-

ferential output swing in 0.25-lm SiGe BiCMOS. Journal of

Solid-State Circuits, 46(5), 1137–1146.

20. Reed, G. T., Mashanovich, G., et al. (2010). Silicon optical

modulators. Nature Photonics, 4, 518–526.

21. Sedighi, B., Ostrovskyy, P., & Scheytt, J. C. (2012). Low-power

20-Gb/s SiGe BiCMOS driver with 2.5 V output swing, IEEE

Microwave Symposium Digest (MTT), pp. 1–3.

Bernhard Goll (M’08) received

the M.Sc. degree (with distinc-

tion) in Electrical Engineering

and Telecommunication Engi-

neering in 2003 and the Ph.D.

degree (with distinction) in 2007

from Vienna University of

Technology (VUT), Austria. He

is with the Institute of Electro-

dynamics, Microwave and Cir-

cuit Engineering, VUT, as a

Scientific Research Assistant on

the design of analog integrated

circuits, especially clocked,

regenerative comparators, mod-

ulator drivers and optical receivers.

Horst Zimmermann (M’98–

SM’02) was born in Sulzbach-

Rosenberg, Bavaria, in 1957. He

received the Dr.-Ing. degree

from the Fraunhofer Institute for

Integrated Circuits (IIS-B), Er-

langen, Germany, in 1991. He

was an Alexander-von-Hum-

boldt Research Fellow at Duke

University, Durham, NC, where

he worked on diffusion in Si,

GaAs, and InP until 1992. In

1993, he joined the Chair for

Semiconductor Electronics, Kiel

University, Kiel, Germany,

where he lectured optoelectronics and worked on optoelectronic

integration in silicon. Since 2000, he is professor for Electronic

Circuit Engineering at the Vienna University of Technology, Vienna,

Austria. He is the author of the Springer books ‘Integrated Silicon

Optoelectronics’ (2nd ed., 2000) and ‘Silicon Optoelectronic Inte-

grated Circuits’ (2004), coauthor of ‘Highly Sensitive Optical

Receivers’, of’Optical Communication over Plastic Optical Fibers’

and of ‘Analog Filters in Nanometer CMOS’ as well as author or co-

author of more than 400 publications. His main interests are in the

design and characterization of analog, deep-submicron and nanometer

CMOS circuits as well as optoelectronic integrated CMOS and

BiCMOS circuits and sensors.


123

Documents

A 10 Gb/s 0.25 μm SiGe modulator driver for photonic-integration