A 12-bit, 300 MS CMOS DAC for high-speed system applications

Weining Ni; Xueyang Geng; Yin Shi; Foster Dai;Circuits and Systems, 2006. ISCAS 2006. Proceedings.

2006 IEEE International Symposium on 21-24 May 2006 Page(s):4 pp. Digital Object Identifier 10.1109/ISCAS.2006.1692857

指導教授：林志明 老師 研究生：黃信嵐 學號： 95662008

2006.11.27

OUTLINE

INTRODUCTION DAC ARCHITECTURE DAC IMPLEMENTATION EXPERIMENTAL RESULTS CONCLUSION Q&A

INTRODUCTION a 12-bit, 300MHZ, CMOS DAC . a unit current-cell matrix for 8 MSBs and

a binary-weighted array for 4 LSBs to obtain high linearity at 12bit level.

a double Centro symmetric current matrix is designed by using the Q2 random walk strategy.

DAC ARCHITECTURE

REQUIREMENT BINARY-WEIGHTED THERMOMETER-CODED

DNL 64σ σINL 32σ 32σ

Area (INL=0.5LSB)

1024*Aunit 1024*Aunit

Area (INL=1LSB) 256*Aunit 256*Aunit

Area (DNL=0.5LSB)

4096*Aunit Aunit

DAC ARCHITECTURE Normalized required area versus percent of segmentation

DAC IMPLEMENTATION Simplified DAC architecture with current steering matrix.

B0B3B4B11

DAC IMPLEMENTATION Switching sequence of the Q2 Random Walk switching scheme

DAC IMPLEMENTATION

0. current source 0 in region A,1. current source 0 in region B,2. …16. current source 1 in region A17. current source 1 in region B18. ……254. current source 15 in region o255. current source 15 in region p.

DAC IMPLEMENTATION

DAC IMPLEMENTATION Chip photograph of the D/A converter

EXPERIMENTAL RESULTS

INL

EXPERIMENTAL RESULTS DNL

EXPERIMENTAL RESULTS Measured SFDR

CONCLUSION MEASURED PERFORMANCE OF THE PROTOTYPE DAC

Q&A