A 2.1 lW 80 dB SNR DT DR modulator for medical implantdevices in 65 nm CMOS

Ali Fazli Yeknami • Atila Alvandpour

Received: 15 February 2013 / Revised: 19 May 2013 / Accepted: 27 May 2013 / Published online: 18 June 2013

� Springer Science+Business Media New York 2013

Abstract This paper presents a simple and robust low-

power DR modulator for accurate ADCs in implantable

cardiac rhythm management devices such as pacemakers.

Taking advantage of the very low signal bandwidth of

500 Hz which enables high oversampling ratio, the objective

is to obtain high SNDR and low power consumption, while

limiting the complexity of the modulator to a second-order

architecture. Significant power reduction is achieved by

utilizing a two-stage load-compensated OTA as well as the

low-VT devices in analog circuits and switches, allowing the

modulator to operate at 0.9 V supply. Fabricated in a 65 nm

CMOS technology, the modulator achieves 80 dB peak SNR

and 76 dB peak SNDR over a 500 Hz signal bandwidth.

With a power consumption of 2.1 lW, the modulator obtains

0.4 pJ/step FOM. To the authors’ knowledge, this is the

lowest reported FOM, compared to the previously reported

second-order modulators for such low-speed applications.

The achieved FOM is also comparable to the best reported

results from the higher-order DR modulators.

Keywords Analog-to-digital converter (ADC) �Delta-sigma modulator � Operational transconductance

amplifier (OTA) � Medical implant device

Load-compensated two-stage amplifier

1 Introduction

Medical implant devices, such as pacemakers and cardiac de-

fibrillators, require increasingly advanced signal acquisition

and processing systems. Such devices require extremely low

power consumption. Analog-to-digital converters (ADCs) are

among the most critical components for measurement of

various electrophysiological signals [1, 2]. For low resolution

conversion (7–9 bits), SAR ADC has shown to be an efficient

choice [3]. For higher-precision measurements in medical

implants, the DR modulator is gaining significant interest [4].

This paper describes the design and measurement results of a

simple and low-power DR modulator, aimed for high-preci-

sion conversion of the low frequency cardiac signals. Taking

advantage of the very low signal bandwidth of 500 Hz, the

main objective is to achieve a high SNDR and low power

consumption, while limiting the modulator complexity to a

high-oversampled second-order architecture. This design

strategy for maximum simplicity in the modulator architecture

is particularly motivated for the improved robustness and the

stable circuit operation in such critical environments as well as

the minimum chip area.

Operational transconductance amplifiers (OTAs) are the

most critical block of the DR ADCs and consume most of

the power. To reduce the power, several circuit techniques

have been proposed, such as the inverter-based integrator

[4–6], the double-sampled integrator [7–9], and the single-

stage OTAs [10, 11]. Using the inverter as an amplifier in

[4] suffers from the sensitivity to process variation, due to

the undefined bias current. This issue is resolved by a

switched capacitor (SC) biasing scheme in [5], where the

inverter is biased near threshold voltage (VT) and its offset

is compensated with additional circuits. This circuit over-

head for the modulator operating at supply near VT [5]

imposes excessive power. Double-sampling technique

[7–9], as a low-power solution in SC circuit, can provide

twice the sampling frequency without increase in opamp

bandwidth requirement, but at the cost of more kT/C noise.

Moreover, the designs in [10, 11] employ single-stage

A. Fazli Yeknami (&) � A. Alvandpour

Department of Electrical Engineering, Linkoping University,

Linkoping, Sweden

e-mail: ali@isy.liu.se

123

Analog Integr Circ Sig Process (2013) 77:69–78

DOI 10.1007/s10470-013-0087-x

high-performance amplifier to reduce the analog power. In

this work, we exploit a two-stage load-compensated OTA

because of its advantage in the low bias current and the low

speed application of the medical implants.

Furthermore, the use of low-VT transistors in the analog

blocks of the designed modulator provides larger voltage

headroom in the amplifiers as well as wider overdrive

voltage in the switches implementation at 0.9 V, elimi-

nating the need for bootstrap circuit [12], or charge pump

clock booster [5]. This strategy has lead to a simpler

architecture, which in turn has resulted in a more power-

efficient modulator.

By combining maximal simplicity in the modulator

circuit and architecture, power-efficient analog solution

such as the two-stage load-compensated OTA, low-VT

devices in analog blocks and high-VT devices in digital

circuits, the implemented modulator obtains the lowest

FOM among the second-order DR converters in such low

signal bandwidths. The achieved FOM (0.4 pJ/step) is

comparable to the best reported modulators from the

higher-order architectures.

The rest of the paper is organized as follows: Section 2

explains the modulator architecture and discusses the sys-

tem-level and low-power design considerations. Section 3

describes the modulator implementation. Section 4 pre-

sents the measurement results, followed by the comparison

with other publications in Sect. 5. Conclusions are drawn in

Sect. 6.

2 Modulator architecture

2.1 System-level considerations

There are several degrees of freedom in the DR modulator

design space, such as the modulator order, the OSR, and

the number of quantization bits. With minimum power

consumption as a key design objective we aimed to avoid

any circuit complexity and overhead. Targeting about

12-bit resolution, with the system-level simulations we

found a second-order single-loop topology sufficient for the

required SNR and convenient to minimize the power and

area. The modulator employs inherently linear one-bit

quantizer. The multi-bit quantization is avoided because

the internal DAC usually requires dynamic element

matching [13] or other complementary linearization tech-

niques, which increase the hardware complexity and hence

the power consumption. Since the signal bandwidth is too

low, up to 500 Hz, a relatively high OSR can be used,

which makes the thermal noise (kT/C) contribution to the

signal band low. In this way, also the capacitor size of the

first integrator and consequently the power consumption

can be reduced. Using an OSR equal to 250 in the system-

level simulation when both amplifiers gain is set to 35 dB,

the scaled modulator (Fig. 2) achieves 90 dB SNR pro-

viding more than 10 dB margin for 12-bit accuracy.

Considering the linear model of the designed DR con-

verter shown in Fig. 1, the baseband output signal includ-

ing noise is given by

Y � Xþ N1ð Þ þ 1

HN2 þ

1

gHFNq H;F � 1 ð1Þ

where H and F are the transfer functions of the integrators,

N1 and N2 represent their input-referred noise, respectively,

while Nq denotes the quantization noise. The factor g rep-

resents the equivalent gain of the quantizer [14]. As seen

from Eq. 1, the noise N2 is shaped (low-pass filtered) by

filter H, while Nq is shaped by both filters H and F. Thus,

for the overall noise reduction (and accordingly power

saving) the first filter H appears critical. As a consequence,

the corresponding OTA tends to consume most of the

modulator power. The second integrator F however is less

important, therefore its performance and current con-

sumption can be scaled down to reduce the analog power

consumption.

The z-domain model of the scaled modulator topology is

shown in Fig. 2 with two-pole low-pass filter and 1-bit

quantizer. The noise transfer functions (NTF) and the sig-

nal transfer function (STF) can be expressed by:

NTF(z) ¼ YðzÞE(z)

¼ ð1� z�1Þ2

1þ ðga2 � 2Þz�1 þ ð1þ ga1a2 � ga2Þz�2

STF(z) ¼ YðzÞX(z)

¼ ga1a2 � z�2

1þ ðga2 � 2Þz�1 þ ð1þ ga1a2 � ga2Þz�2� ð2Þ

where a1 = 0.23 and a2 = 0.3 are the signal and feedback

scaling coefficients, determined by the loop stability con-

straint, the maximum linear swing of the integrators, and

the required SNR. Figure 3 indicates that the STF is unity

and the NTF has 40 dB/dec noise suppression in baseband.

2.2 Modulator order and oversampling ratio

In this section we discuss the tradeoffs between the OSR

and the modulator order with respect to power and

YH+X

-+ + F +

N1 N2 Nq

-Quantizer

+ g

Fig. 1 Linear model of the single-loop second-order DR modulator

70 Analog Integr Circ Sig Process (2013) 77:69–78

123

performance. The first-order DR modulator is naturally

rejected because it suffers from the idle tones [15] and also

requires very high OSR (or sampling frequency) to meet

the required SNR, resulting in high power dissipation,

particularly in the digital blocks. In low-power design

environment it is advantageous to use second-order mod-

ulator due to its simplicity [16, 17]. Alternatively, third-

order modulator with approximately half OSR can be used

at the cost of one extra integrator, whereas amplifiers with

half gain-bandwidth (GBW) can be replaced.

Ideally, with constant OSR the increase in the modulator

order would improve the SNR. In other words, for a given

SNR the third-order (or higher-order) modulator makes use

of a lower OSR (or clock frequency) than the second-order

modulator. It should be noted that with modulator order

equal to three or higher, the more stringent scaling of the

signal levels would be required to sustain the stability,

which limits the SNR in practical implementations.

For kT/C-noise dominated DR modulators (i.e., high-

resolution modulators), in particular, the sampling capaci-

tor value CS1 in the first integrator can be expressed as

shown below [14]

CS1 ¼8kT � DR

OSR� V2FS

ð3Þ

where kT is the product of the Boltzmann constant and the

absolute temperature, DR is the dynamic range, and VFS is

used as the amplitude of a full-scale sinusoidal input. For a

given SNR, using a half OSR in the third-order topology

translates into twice the sampling capacitor CS1, according

to Eq. 3. To maintain the integrator gain (a1 = CS1/CI1)

constant in both second- and third-order topology, also the

integrating capacitor CI1 has to be taken twice in value.

Therefore, the effective capacitive load of the first integrator

(Fig. 10), given by Eq. 4, would increase, thus enhances the

amplifier power. In this scenario, achieving lower power

consumption with a third-order implementation seems to be

impractical.

CL;eff ¼ CL þCS1 � CI1

CS1 þ CI1

ð4Þ

Furthermore, in applications that the input signal

bandwidth is very high, it is normally useful to keep the

sampling clock frequency low by using higher-order

modulators but with extremely low OSR. In this way, the

analog performance parameters of the required amplifiers

would become achievable at a lower power. As the signal

bandwidth in this work is too low, a second-order topology

with a relatively high OSR of 250 is employed, which

makes the thermal noise (kT/C) contribution to the signal

band very low. Therefore, the capacitor size of the first

stage and consequently the power consumption are

decreased.

To summarize, it is not generally straightforward to

draw conclusion that either a second-order or a third-order

modulator topology favors lower power dissipation at a

given SNR, as it depends on several important design

factors, such as the signal bandwidth, the circuit topology

[e.g., common-mode feedback (CMFB) circuit in the

OTAs], the loop coefficients used for the stability, etc.

2.3 Low-power design considerations

To reduce the overall power consumption several solutions

are exploited in this work as follows:

Since simplicity both in architecture and circuit building

blocks is beneficial for ultra-low-power design, a single-

loop topology with single-bit quantization is adopted.

Lower-order modulator also simplifies the design of the

succeeding digital decimation filter, thereby reducing the

total converter power [14, 18].

The use of low-VT devices provides sufficient switch

overdrive at the cost of more leakage or harmonic distor-

tions [11, 19], while it eliminates the need for extra circuit

for boosting the voltage, such as bootstrapping switches

[12] and charge pump clock boosters [20]. The use of low-

VT device, on the other hand, enables a simpler amplifier

design, which compensates for the low available headroom

in 0.9 V supply.

Y++

-

++

-1

1

z1

z−

−

−

X1

1

z1

z−

−

−+

g

E(z)

a1

a1 a2

a2

Fig. 2 The scaled topology of the second-order single-loop DRmodulator with loop coefficients a1 = 0.23, a2 = 0.3

Fig. 3 Magnitude of NTF(z) and STF(z) of the scaled modulator

Analog Integr Circ Sig Process (2013) 77:69–78 71

123

In contrast, the digital circuits of the modulator exploit

the advantage of high-VT devices in order to suppress the

leakage in this low speed application (Sect. 3.2, 3.3).

In addition to the choice of the modulator topology, the

selection of the building blocks including OTA, compara-

tor, CMFBs, is also important in power reduction (Sect. 3).

Additionally, efforts have been made to find the optimal

performance parameters (e.g., dc gain and GBW of the

OTAs) in a wide optimization space (Sect. 2.4).

2.4 OTA requirements

The main requirements for the OTA are dc gain, GBW and

output swing. As mentioned before, OTAs are the main

analog circuits of the DR modulators. Particularly, the first

OTA determines the overall modulator performance and

hence consumes the major part of the power. To minimize

the power, optimal analog performance parameters (gain

and GBW) need to be determined. Figure 4 shows the

obtained SNR versus the dc gain and the GBW of the first

OTA. The minimum gain and GBW to obtain more than

90 dB SNR is about 35 dB and 1.2 MHz, respectively.

This minimum requirement is drawn only from the SNR

perspective. Taking into account high power supply

rejection ratio, good distortion performance (SNDR), and

robust operation in the presence of process-voltage-tem-

perature variation, a safe margin has to be placed for the

minimum gain and GBW.

The signal swing is of great importance in low-voltage

modulator design. Due to the limited headroom in low-

voltage operation, cascode topologies such as folded cas-

code [16, 21, 22] and telescopic cascode amplifiers cannot

be used. Therefore, to compensate for the necessary gain, a

two-stage topology is selected.

3 Circuit implementation

The key building blocks in the modulator are explained in

this section. The OTA is the most critical component, and

is discussed first. Other important blocks, such as com-

parator and latch, non-overlapping clock generator, are

explained subsequently.

3.1 Power-efficient OTA: design and analysis

The DT DR converters have been largely studied and

developed in terms of the opamp non-idealities [15, 18,

23], such as finite gain and GBW, noise, etc. In this section,

we reconsider the power efficiency aspect of the most

popular opamp topologies in low-power design.

Several OTA topologies were designed and carefully

analyzed [24] for ultra-low-power delta-sigma modulator.

Among them a load-compensated two-stage amplifier was

selected because of its higher power-efficiency, rail-to-rail

voltage swing, and minimal load for a balanced GBW and

phase margin.

While the two-stage Miller amplifier and the single-

stage current-mirror OTA have been widely used for low-

power modulators [10, 11], we exploit the two-stage load-

compensated OTA due to its advantage in the low bias

current and low speed of the target application. Figure 5

shows the schematic of the differential two-stage amplifier

with load compensation. Because of the low current

(*200 nA) in this OTA, the output resistance of the

amplifier is inherently high and the dominant pole due to

the output load CL is then placed at very low frequency

with a minimal load capacitor value, 2 pF for the first

OTA. Therefore, in this application the load compensation

is preferred to the Miller compensation because it prevents

additional power dissipation for driving the Miller capac-

itor. This is shown by the following analysis.

The non-dominant pole due to the parasitic capacitance

of node x is placed beyond 3 9 GBW. The dc gain and

GBW of the OTA is then expressed as

Fig. 4 SNR versus the first OTA’s dc gain and GBW. The GBW

simulation is accomplished when the gain is set to 50 dB

72 Analog Integr Circ Sig Process (2013) 77:69–78

123

Ad ¼ gm1Rout1 � gm5Rout2 ð5Þ

GBW ¼ gm1 � gm5 � Rout1

2p � CL

: ð6Þ

where gmi is the transconductance of the ith transistor in the

OTA, and Rout1 and Rout2 are the output resistance of the

1st and 2nd stage, respectively. Assuming all branches of

the amplifier, illustrated in Fig. 5, draw similar current and

that all transistors are driven in the moderate inversion

region, the transconductance of M1 and M5 is given by

Eq. 7

gm1 ¼ gm5 ¼ gm ¼2ID1

VGS � VT

ð7Þ

Substituting Eq. 7, the GBW given by Eq. 6 can be

modified to

GBW ¼ g2m � Rout1

2p � CL

¼ g2m

2p � CL � ðkn þ kp

����Þ � ID1

ð8Þ

Combining Eqs. 7 and 8, the total current drawn by the

load-compensated two-stage OTA, denoted by I2S–LC, can

be expressed as

I2S�LC ¼ 4� ID1

¼ GBW � p � VGS � VTð Þ2 � kn þ kp

����

� �

� 2CLð Þ:ð9Þ

Similarly, for the same GBW, overdrive voltage, and

load capacitance CL, the current drawn by a class-A Miller

compensated OTA (Fig. 6) has been derived in [10] as

IMiller ¼ GBW � p � VGS � VTð Þ � 8CM þ 6CLð Þ: ð10Þ

Then the current ratio of the two-stage load-compensated

OTA to the Miller OTA for the same condition is given

by

I2S�LC

IMiller

¼ VGS � VTð Þ � kn þ kp

����

� �

� 2CL

8CM þ 6CL

:

ð11Þ

Typically, this ratio is much smaller than one. It is worth

to mention that even for 2CL|2S–LC & (8CM ? 6CL)Miller in

the worst case to get much better phase margin in a load-

compensated amplifier, yet the term (VGS- VT) 9

(kn ? |kp|) keeps Eq. 11 well below one. Generally

saying, a drawback of this amplifier is that it may require

larger load than a Miller OTA to get enough phase margin

for a given GBW. It must be noted that the actual load of

the OTA in this sigma-delta feedback loop is enforced by

the loading effect of the sampling and feedback capacitors,

rather than the phase margin constraint. Commonly, due to

the thermal noise suppression, the sampling and feedback

capacitors are selected to be large (see Fig. 10), which

considerably loads the amplifier output node in the

integration phase [11, 18].

M3

M0

outp outn

VDD

M5

CMFB

M1inp inn

M7

M2

M4b

VDD

M4

CMFB

M6

VBVBVB

M2b XX

M1b

M3b

M5b

M6b M7b

CL CL

Fig. 5 The two-stage

load-compensated OTA

M0

outp outn

VDD

M3

M1inp inn

M2bM2

M4

M1b

M3b

M4b

CLCL

CMCM

Fig. 6 The two-stage class-A Miller-compensated OTA

Analog Integr Circ Sig Process (2013) 77:69–78 73

123

For the same GBW, overdrive voltage, and load

capacitance CL, the current drawn by a current mirror (CM)

OTA (Fig. 7), derived in [10], can be given by

ICM ¼ GBW � p � VGS � VTð Þ � 2CL þ 2CL=bð Þ: ð12Þ

where b is the CM ratio (see Fig. 7). Then the current ratio

of the load-compensated OTA to the CM amplifier used in

[10, 11] is

I2S�LC

ICM

¼ VGS � VTð Þ � kn þ kp

����

� �

� 2CL

2CL þ 2CL=b:

ð13Þ

The last term is approximately one as b is large, but the

term (VGS- VT) 9 (kn ? |kp|) is sufficiently smaller than

one.

As clearly seen from Eqs. 11 and 13, the two-stage load-

compensated amplifier shows better power-efficiency than

the Miller-compensated two-stage (Fig. 6) and the CM

(Fig. 7) amplifiers. Therefore, we take advantage of the

nano-ampere bias current to minimize the amplifier’s load

capacitance and hence the power with acceptable phase

margin and GBW.

Another important design factor in the modulator is

noise, which directly determines the power. As seen from

Eq. 1, the noise term N1 does not obtain any attenuation by

the loop filters, and directly affects the modulator perfor-

mance. The N1 consists of the amplifier noise (thermal and

flicker) as well as the thermal noise from the sampling and

DAC switches. The latter was mitigated by the proper

sizing of the sampling and feedback capacitors in the

modulator input stage. Moreover, the input devices M1/

M1b of the first OTA, the main noise contributors, are

designed with large dimension and large gm in order to

limit the thermal noise and the flicker noise contribution.

The post-layout simulation for worst-case corner indi-

cates that the first OTA achieves 49 dB dc gain, 58� phase

margin and 2.4 MHz GBW with a 2 pF load. As explained

in Sect. 2.1, the OTA performance requirement of the

second integrator can be relatively relaxed; hence, its

performance is scaled down to 42 dB gain, 1.8 MHz GBW

and 45� phase margin with a 0.6 pF load capacitance in

order to reduce the analog power. The first and second

integrators draw 1.15 and 0.84 lA, respectively.

To maximize the voltage swing, the OTAs output

common-mode voltage is set to half VDD by means of a

very power-efficient switched-capacitor CMFB [11]. Due

to its capacitive loading at node x and a considerable phase

margin reduction, a simple continuous-time CMFB is

employed in the first stage (Fig. 5), composed of four

transistors M2, M2b, M4, M4b. Biased in the linear oper-

ating region, M2 and M2b realize resistors that sense the

CM level at node x and provide control voltage in the gate

of M4 and M4b to balance the positive and negative out-

puts of the first stage.

3.2 Single-bit quantizer and latch

The single-bit quantizer is implemented using a dynamic

regenerative comparator [10] and a SR-latch. The circuit

schematic is shown in Fig. 8. When clock signal clk is low,

the nodes x and y are precharged to VDD. While clk goes

high, the precharged nodes begin to discharge to the ground

by transistors M1a and M1b. The amount of discharge

currents depend on the input signals. The cross-coupled

transistors, M3a and M3b, form a positive feedback loop

and amplify the difference in the inputs to a full-rail output.

Since the comparator is a dynamic circuit, a slow clock

causes the leakage current flows through branches. To limit

this, high-VT and low-power transistors are utilized. The

total power consumption of the comparator and latch is

\10 nW. Any non-ideality of the comparator circuit is

suppressed by the modulator loop filter, and thus the

requirement of the single-bit quantizer is relaxed. Offset

voltage at the comparator input is minimized by a careful

layout of the input devices.

M0

outp outn

VDD

M3

M1inp inn

M2bM2

M4

M1b

M3b

M4b

CLCL

1:1:

Fig. 7 The single-stage current-mirror OTA

M1a M1b

M2a M2b

inp inn

VDD

outn

outp

clk clkM3a M3b

xy

Fig. 8 Dynamic comparator and SR latch using high-VT low-power

devices

74 Analog Integr Circ Sig Process (2013) 77:69–78

123

3.3 Clock generation circuitry

The clock generation is provided on-chip [10]. The external

clock input (250 kHz sine wave) is buffered and then two

non-overlapping clocks with their delays, as indicated by

U1d and U2d in Fig. 9, are generated using logic gates. The

U1, U2, U1d, and U2d clock signals have to drive 6, 4, 12 and

12 switches in total, respectively, which include the sam-

pling, DAC, integrating switches as well as the switches in

the SC CMFBs. Therefore, the estimated capacitive load of

the clock signals is 60, 40, 120, and 120 fF, respectively. The

circuit components are carefully sized and optimized for

nano-Watt range power consumption. High-VT low-power

devices with non-minimum length (L = 1.5 lm) have been

used to minimize the leakage consumption. The total mea-

sured digital power including non-overlapping clock gen-

erator is 0.3 lW.

3.4 Overall modulator circuit

Figure 10 shows the schematic diagram of the implemented

second-order DR modulator with active integrators. The first

sampling capacitor value CS1 is determined by the thermal

noise level of the modulator and with extra noise margin is

selected as 2 pF, which is sufficient for 90 dB SNR with

0.6 V reference level and OSR of 250. Other capacitors are

chosen to meet the loop coefficients as indicated in Fig. 2.

The capacitor values are specified in Fig. 10. As mentioned,

switches are designed as transmission gate using low-VT

device, which provides wider overdrive voltage and smaller

signal-dependent on-resistance. The digital parts of the

modulator, including the clock generation circuit, latch,

clock buffers, and the switch local drivers, utilize small size

and high-VT devices to minimize the dynamic power and the

leakage. The DAC reference level is set to 0.6 V, which is

clk

1d

1

2d

2

inv inv

inv buffer

inv

0.3/1.5

0.135/1.5

2.2/1.5

1.0/1.5

Fig. 9 Clock generation

circuitry using high-VT

low-power devices

+

-

-

+

2

2

1

1cmi

1d

CI1

CS1

CI1

OTA1

CS1

VREFP VREFN

Lp Ln

1d

Lp

Ln

+

-

-

+

CS1

CS2

CI1

CI2 1 pF

2 pF

8.8 pF

0.3 pF

1

inp

inn

2d

VREFN VREFP

Lp Ln

2d

+

-

-

+

2

2

1

1cmi

1d

CI2

CS2

CI2

OTA2

CS2

VREFP VREFN

Lp Ln

1d

2d

VREFN VREFP

Lp Ln

2d

Fig. 10 Schematic diagram of the implemented modulator with two active integrators. The sampling and integrating capacitor values are

included

Analog Integr Circ Sig Process (2013) 77:69–78 75

123

defined by VREFP = 0.75 V and VREFN = 0.15 V, and the

modulator is designed for an OSR of 250.

4 Measurement results

The prototype chip was fabricated in a 65 nm CMOS

technology using MIM capacitors. The chip micrograph is

shown in Fig. 11. It occupies a core area of 0.033 mm2.

For the chip test, a high-accuracy signal generator is used to

generate the input signals. The output data is captured by an

oscilloscope and then processed with Matlab. Figure 12 shows

the measured power spectrum for -4.0 dBFS, 99 Hz sinusoidal

input. Figure 13 depicts the measured SNR and SNDR versus

the differential input amplitude. Clocked at 250 kHz, the peak

SNR and SNDR are 80 and 76 dB, respectively, from a 0.9 V

supply over 500 Hz signal bandwidth.

The power breakdown by sources, obtained from the

chip test, is shown in the diagram of Fig. 14. The analog

power, including the integrators and reference voltages,

constitutes 85 % of the total power, whereas almost 50 %

of the power is dissipated in the first integrator. It should be

noted that the reference buffers necessary for the reference

generation are not included in the power calculation, and so

M Core

Oth

er C

ircu

its

1st integrator

2nd integrator

rot

are

neG

kcol

C

Qu

antizer

Capacitors

Capacitors

Fig. 11 Chip micrograph and the layout details. Capacitors are

realized by MIM (Metal Insulator Metal) structure

Fig. 12 Measured spectrum with a -4.0 dBFS and 99 Hz input.

32768 FFT-point are used

Fig. 13 Measured SNR and SNDR versus differential signal ampli-

tude. Below -40 dBFS the values are extrapolated

Integrator I49.5%

clock generation14.3%

Integrator II36%

Comparator+ latch0.2%

Fig. 14 Measured modulator power distribution

Table 1 Measured performance results

Technology 1P7M 65 nm CMOS

Supply voltage 0.9 V

Clock frequency 250 kHz

Signal BW 500 Hz

Peak SNR 80 dB (13-bit)

Peak SNDR 76 dB (12.3-bit)

Dynamic range 75 dB

Power 0.3 lW digital

1.8 lW analog

Active area 0.033 mm2

FOM 0.407 pJ/step

76 Analog Integr Circ Sig Process (2013) 77:69–78

123

is for the modulators listed in the comparison Table 2. The

measured performance is summarized in Table 1.

5 Performance comparison

The measured performance of the implemented modulator

is compared to the other delta-sigma modulators in

Table 2, where the FOM is defined as the following:

FOM ¼ Power=ð2ENOB � 2� BWÞ: ð14Þ

The implemented DT DR modulator achieves the lowest

FOM, compared to the previously reported second-order [16,

17] and low bandwidth modulators [4, 16, 21, 25]. The

achieved FOM is also comparable to the best reported results

from the higher-order delta-sigma ADCs [4, 5, 8, 9, 11, 21,

25]. Moreover, the designed modulator occupies the lowest

chip area among the modulators, which is an important

design factor for implantable devices. While DR converters

listed in Table 2 have been implemented in old technologies

(0.35-, 0.18-, or 0.13-lm process), this design exploits the

advantage of ultra-deep-submicron 65 nm CMOS, that

demonstrates the possibility of implementing high-

performance DR ADC in deep submicron technologies.

6 Conclusion

The implementation and measurement results of a low-

voltage and low-power DR modulator for medical implant

devices are presented in this paper. Low-power design

strategy is discussed in detail. Implemented in 65 nm

CMOS, the modulator clocked at 250 kHz achieves 80 dB

peak SNR, 76 dB peak SNDR in a 500 Hz signal band-

width and occupies 0.033 mm2 core area, while it con-

sumes 2.1 lW from a 0.9 V supply voltage. The achieved

power consumption and performance is a direct result of

the simple SC single-loop second-order architecture,

composed of the power-efficient two-stage load-compen-

sated OTAs, and an effective power-optimization scheme

employed in both analog and digital circuits. Compared to

the previously reported modulators, this work obtains one

of the best FOMs (0.4 pJ/step) amongst sub-1-V modula-

tors in terms of most commonly used figure of merit.

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Chae and Han [4] 1.5 0.35 120 3 65 75 0.73 0.35 2.093

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Wismar et al. [26] 0.2 90 nm 20 k 1 60.3 68.9 7.5 0.136 0.082

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Ali Fazli Yeknami received the

B.Sc. degree in electrical engi-

neering and telecommunications

from Sharif University of

Technology (SUT), Iran, in

1999, and the M.Sc. degree in

System-on-Chip from Linko-

ping University (LiU), Sweden,

in 2008. From 1999 to 2000, he

was with the electronic research

center at SUT developing

ADSP218x microcontroller-

based hardware and firmware

design for wireless telephony.

From 2000 to 2006, he was a

senior researcher in R&D department of electronic industries devel-

oping DC–DC converters, C5000 DSP processors, and voice coder for

telecommunication products. He is currently working toward the

Ph.D. degree in the division of electronic devices, the department of

Electrical Engineering at LiU. His research focus is on ultra-low-

power analog-to-digital converters for biomedical implants.

Atila Alvandpour received the

M.S. and Ph.D. degrees from

Linkoping University, Sweden,

in 1995 and 1999, respectively.

From 1999 to 2003, he was a

senior research scientist with

Circuit Research Lab, Intel

Corporation. In 2003, he joined

the department of Electrical

Engineering, Linkoping Uni-

versity, as a Professor of VLSI

design. Since 2004, he is the

head of Electronic Devices

division. His research interests

include various issues in design

of integrated circuits and systems in advanced nano-scale technolo-

gies, with special focus on efficient analog frontends, data converters,

clock generators/synthesizers, and digital circuits for high-speed

communication links as well as low-power sensors and medical

devices. He has published more than 100 papers in international

journals and conferences, and holds 24 U.S. patents. Prof. Alvandpour

is a senior member of IEEE, and has served as member of many

technical program committees of IEEE and other international con-

ferences, including the IEEE Solid-State Circuits Conference, ISSCC,

and European Solid-State Circuits Conference, ESSCIRC. He has also

severed as guest editor for IEEE Journal of Solid-State Circuits.

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