A New SVPWM Modulated Input Switched Multilevel Converter for Grid-Connected PV Energy Generation Systems

920 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 2, NO. 4, DECEMBER 2014

A New SVPWM Modulated Input SwitchedMultilevel Converter for Grid-Connected

PV Energy Generation SystemsXiong Li, Student Member, IEEE, Serkan Dusmez, Student Member, IEEE,

Udupi Rajagopal Prasanna, Member, IEEE, Bilal Akin, Senior Member, IEEE,and Kaushik Rajashekara, Fellow, IEEE

Abstract— This paper proposes a new space vector pulsewidthmodulation (SVPWM) strategy for a hybrid input switchedmultilevel converter for photovoltaic energy generation systems.The converter topology is a cascaded connection of input switchedand H-bridge converters, which can provide 2N + 1 voltagelevels for each phase. The proposed SVPWM strategy treats themultilevel converter as a two-level converter by introducing anoffset vector. With a generated switching pattern, it is possible toobtain minimum number of switching-state transitions and switchthe H-bridge close to line frequency; thus, the switching lossescan be significantly reduced. The proposed SVPWM strategyhas been realized on a seven-level converter to demonstrate theprinciple of operation. The advantages of the proposed schemeand architecture are verified by both simulation and experimentalresults.

Index Terms— Multilevel converters, renewable energysystems, space vector pulsewidth modulation (SVPWM).

I. INTRODUCTION

SOLAR photovoltaic (PV) converters continue to be oneof the most active research areas, both for grid-connected

and stand-alone applications [1]–[7]. Two-level multistringconverters are utilized to interface several PV strings to acommon dc–ac converter [8], [9]. This architecture featuresseveral advantages, such as independent maximum powerpoint (MPP) tracking of each string and the possibility toscale the system by plugging more strings to the existing plant.Multilevel converter topologies have also been investigated forPV applications [10]. The multilevel converter topologies, ingeneral, can generate high-quality voltage waveforms, wherepower semiconductor switches are operated at a very lowfrequency [11]. Due to the low switching frequency, the powercan be efficiently transferred with better power quality and lowelectromagnetic interference noise.

Manuscript received February 10, 2014; revised May 9, 2014 and July 28,2014; accepted September 4, 2014. Date of publication September 17, 2014;date of current version October 29, 2014. Recommended for publication byAssociate Editor C. Oates.

The authors are with the Power Electronics and Drives Laboratory,Department of Electrical Engineering, Erik Jonsson School of Engineeringand Computer Science, University of Texas at Dallas, Richardson,TX 75080 USA (e-mail: [email protected]; [email protected];[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JESTPE.2014.2358590

In addition, multilevel converters feature several dc links,allowing independent voltage control, and MPP tracking ineach string. There are three traditional multilevel convertertopologies; the diode clamped (DCC) [12], flying capacitorclamped [13], and cascaded H-bridge (CHB) converters.Among them, the three-level DCC converter is widelyaccepted in industries for different applications. However,it has several disadvantages at higher voltage levels, such ashigher cost due to more number of power devices, deviationin dc link capacitor voltage, and so on. These issues arealso valid for flying capacitor based multilevel converters.Though CHB converters do not have dc link capacitor voltagedrifting issue, multiple isolated dc sources, which are usuallyprovided by phase shifted transformers, are needed. To addressthe issues associated with the traditional multilevel convertersmentioned above, a number of multilevel converters withhybrid configurations, such as input switched converters, areproposed in [14]–[17].

Several space vector modulation strategies are proposedto modulate the output voltage of multilevel convertersin [18]–[31]. In [19], an SVPWM modulation strategy hasbeen proposed for three-level converter. The idea is to dividethe complete space vector into six two-level sectors. However,a systematic switching sequence has not been presented andthe computation would be heavier with the increasing numberof voltage levels. Majority of these modulation strategiesinvolve high-computation cost, which is not practical to beimplemented with low-cost controllers for medium powerapplications. In this paper, a new SVPWM control strategy foran input switched multilevel converter topology, which treatsthe multilevel converter as a two-level converter, is proposed tomodulate the output voltages, allowing simple implementation.The proposed technique relies on introducing an offset vectorclose to the reference vector, shifting the origin to this offsetvector, and operating in a two-level hexagon sector. A simpleyet effective algorithm is proposed to generate the offsetvector with minimum amount of computation. The proce-dure of synthesizing the reference voltage vector is a simplethree-step process: 1) locating the offset vector; 2) determiningswitching pattern; and 3) calculating dwelling time of eachnearest vector (NV). The subprocesses of determination ofthe switching pattern and calculation of dwelling time are

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LI et al.: NEW SVPWM MODULATED INPUT SWITCHED MULTILEVEL CONVERTER 921

Fig. 1. PV generation system with seven-level hybrid input switched converter.

independent of the voltage levels, thus high-resolution voltagedoes not add any implementation complexities to those twosubprocesses. However, the process of offset vector locatingalgorithm is dependent on the voltage resolution. The higher isthe voltage resolution the more complicated is the implementa-tion. For an N-level converter, the time complexity of the pro-posed SVPWM strategy is O(2n). In this paper, the proposedSVPWM technique is analyzed on a seven-level input switchedconverter configuration. With the proposed SVPWM strategy,the switching frequency of the input switched converter canbe significantly decreased, and the H-bridge can be switchedat close to line frequency.

This paper is organized as follows. In Section II, operatingprinciples and switching states of the hybrid input switchedmultilevel converters are introduced. The new SVPWM strat-egy is described in Section III. The modeling and con-trol of grid-connected multilevel converter is explained inSection IV. The simulation and experimental results areprovided in Section V to show the effectiveness of the pro-posed SVPWM strategy for stand-alone and grid-connectedoperations. Finally, the conclusion derived from the study ispresented in Section VI.

II. OPERATION PRINCIPLES OF THE

MULTILEVEL CONVERTER

The seven-level input switched multilevel converter consistsof two stages, as shown in Fig. 1. The first stage is formedby three power arms, which are named as input switchedpower converter for the rest part of this paper. Each powerarm includes two devices in back-to-back configuration. Thedc link consists of three capacitors C1, C2, and C3, whichare fed by the battery energy storage system, and divides thelink voltage equally to Vdc/3. It is worth mentioning that theswitches S1, S4, S3, and S6 are exposed to Vdc/3, S2, and S5are exposed to Vdc/6 and H-bridge switches are exposed to Vdc,which limits the feasibility of the converter for medium voltageapplications. The two power switches in each arm are gatedON/OFF in a complementary pattern. The ON/OFF state of each

power switch is determined by the direction of load currentand the voltage level of the first stage. When S1 is turned-ON and other switches are OFF, the output voltage of the firststage is Vdc, the current flows through S1 and D4. Similarly,other output voltages can be achieved by different switchingstates. The converter has 12 switching states that can generateseven different voltage levels Vdc, 2Vdc/3, Vdc/3, 0, −Vdc,2Vdc/3, and Vdc/3, as shown in Table I. The switching statesare combinations of the three switching states provided by theinput switched power converter and the four switching statesof the H-bridge. Since the H-bridge is functioning as a variablegain voltage amplifier, which could provide gains of +1, −1,and 0, it only needs to switch around the zero voltage crossingpoints, thus effective switching frequency of the H-bridge isclose to line frequency.

This topology of input switched multilevel converter isnot suitable for high-voltage/power applications due to thefact that the power devices of the H-bridge need to standa voltage rating of dc link voltage. The application of thistopology is directly limited to the voltage rating of availablepower devices. However, the advantage of this topology isthe capability to provide more voltage levels with reducednumber of power devices, in comparison with traditionalmultilevel converter topologies. Therefore, this topology ismore suitable in applications to improve the output voltage andcurrent quality with reduced component count and switchingfrequency.

III. MODULATION STRATEGY

For a multilevel converter, the reference voltage vectorcan be synthesized by three NVs as defined in [32]. Therelationship can be described as

Ts �Vref = d1Ts �V1 + d2Ts �V2 + d3Ts �V3 (1)

where �Vref is the reference voltage vector; �V1, �V2, and �V3 arethe three NVs; Ts is the switching time period of the carriersignal; d1Ts , d2Ts , and d3Ts are the dwelling time for the


Fig. 2. Space vector diagram of the seven-level converter.

TABLE I

SWITCHING TABLE

three NVs; di = Ti/Ts (i = 1, 2, 3). For each phase, theoutput voltage can be expressed as

Vi = (Si − 3) × Vdc

3(i = a, b, c). (2)

Si can be any of the seven states from the set {0, 1, 2, 3,4, 5, 6}, and can be used to represent the voltage level ofeach phase. Then, (Sa , Sb, Sc) can be utilized to signify avoltage vector. For example, (Sa , Sb , Sc) = (3, 4, 5) meansthat the phase A voltage is 0, phase B voltage is Vdc/3, and

Fig. 3. Subvector space synthesis with offset vector. (a) Space vector diagramof sector one. (b) Subsector used for synthesizing the remaining referencevector.

phase C voltage is 2Vdc/3. The resultant space vector diagramof the seven-level converter is shown in Fig. 2. By intro-ducing an offset vector, the reference voltage vector can berewritten as

�Vref = d1 �V1 + d2 �V2 + d3 �V3

= d1( �Voffset + �V ′

1

) + d2( �Voffset + �V ′

2

) + d3( �Voffset + �V ′

3

)

= �Voffset + d1 �V ′1 + d2 �V ′

2 + d3 �V ′3. (3)

Equation (3) can also be rephrased by

�Vref = �Voffset + �Vrefx . (4)

For a given reference vector, different combinations ofoffset and remaining reference vectors can be found. Thecombination that contains the smallest remaining referencevector is preferred because the remaining reference vectorcan be synthesized by the vectors in the subvector space ina way similar to that for two-level inverters with minimumswitching-state transitions. The resultant subvector space isshown in Fig. 3. �V1, �V2, and �V3 are the three NVs, as shown


TABLE II

SECTOR NUMBER, DIRECTION, AND POSITION UPDATE

with dashed black arrow line; the blue solid arrow line indi-cates the reference voltage vector �Vref ; the offset vector �Voffsetand remaining reference vector �Vrefx are expressed with redsolid arrow line; the purple hexagon displays the subvectorspace which will be used to synthesize the remaining referencevector; �V ′

1, �V ′2, and �V ′

3 are the three vectors in the subvectorspace. Here, three NVs are selected such that the resultantremaining reference vector becomes the smallest. The offsetvector in Fig. 3(a) is �V1. There are two-coordinate systems,where the origin of the initial coordinate system, O, is shiftedby an offset vector, where the offset vector becomes the originof the new coordinate system, O ′. The reference vector, �Vref ,in the coordinate system with O as the origin is equivalent tothe remaining reference vector, �Vrefx , in the new coordinatesystem with O ′ as the origin. The remaining reference vectorcan be calculated once the offset vector is determined, whichcan be synthesized in subvector space, as shown in Fig. 3(b),in a similar way to that for two-level inverters.

The procedure of synthesizing the reference voltage vectoris a three-step process. First, the position of the offset vectorneeds to be located, then the switching sequence shouldbe determined, finally, the dwelling time of the NVs arecalculated.

A. Locating Offset Vector

The process to search for the combination with smallestremaining reference vector aims to enclose the remainingreference vector by the smallest hexagon in the space vectordiagram by shifting the coordinate origin. At each point, theorigin of the coordinate can be moved along six directions,i.e., along A, B , and C , and as well as the opposite directionsof A, B , and C . The direction to choose is determined by therelative position relationship between the reference vector andthe coordinate system. There are a number of paths to shift theorigin of the coordinate system closer to the destined point,while the one with minimum number of steps is preferred dueto the reduced time and computation cost. The sector numberthat the remaining reference vector locates in current coordi-nate system determines the direction of movement of next step.

Fig. 4. Flowcharts for (a) sector number determination and (b) offset vectorlocation.

This relationship is summarized in Table II, and the flowchartof the implementation is given in Fig. 4(b). After each step,the position information of the remaining reference vector isupdated accordingly, as shown in Table II. The voltages inTable II are normalized by the maximum available referencevoltage. The origin of the coordinate system continues to beshifted until the magnitude of the remaining reference vectoris smaller than l1 which is shown in Fig. 3(b). The flowchartof the searching process is shown in Fig. 4(b). An example isgiven in Fig. 5 to illustrate the searching procedure. It is to benoted that under the worst case, the number of steps neededto locate the offset vector is N − 1 for N-level multilevelconverter. Once the offset vector is determined, the rest parts ofthe reference voltage vector synthesis, which are determinationof switching pattern and calculation of dwelling time of eachNV is the same as that for a two-level converter, thus theoverall computation cost of the proposed SVPWM strategy issimilar to that of a two-level converter.

B. Switching Sequence Determination

The switching sequence can be determined accordingto Table III. Each switching sequence is comprised of fourspace vectors, i.e., �V1, �V2, �V3, and �V4. �V1 and �V4 are theoffset vectors determined by the offset vector locating process,as described in Section III-A. There are six switching patternsavailable to be chosen. From Table III, it can be seen that thereis only one phase involving switching actions during spacevector transitions. The switching state of the correspondingphase is just changed to the adjacent one, which results inminimum number of switching transitions. The switch patternis determined by the sector number, where the remainingreference vector locates in the subvector space. For the caseshown in Fig. 3(b), the remaining reference vector locates


Fig. 5. Process of the offset vector determination.

TABLE III

SECTOR NUMBER AND SWITCHING SEQUENCE

in Sector 2. Then, switching pattern for Sector 2 from Table IIIshould be adopted for the switching sequence generation. Theswitching sequence is (Sa, Sb, Sc) → (Sa, Sb + 1, Sc) →(Sa + 1, Sb + 1, Sc) → (Sa + 1, Sb + 1, Sc + 1). The switchingstate of one phase is changed to the adjacent one in eachstep. The switching sequence in other sectors can be selectedaccordingly.

C. Dwelling Time Calculation

Using (3), the remaining voltage reference can beexpressed as

�Vrefx = d1 �V ′1 + d2 �V ′

2 + d3 �V ′3. (5)

The dwelling times can be calculated as⎧⎪⎪⎪⎨

⎪⎪⎪⎩

d2Ts = 6 ×[Vα sin

(n

3π

)− Vβ cos

(n

3π

)]Ts

d3Ts = −6 ×[

Vα sin

(n − 1

3π

)− Vβ cos

(n − 1

3π

)]Ts

d1Ts = (1 − d2 − d3)Ts

(6)

Fig. 6. Duty cycle generation of switching vectors. (a) Using two-phaseshifted triangle carriers. (b) Using a single triangle carrier.

Fig. 7. System diagram of grid-connected seven-level converter.

where Vα and Vβ are the projections of the remainingreference vector on the α–β plane, and n denotes the sectornumber within the subvector space. Two duty cycle gener-ation methods for switching vectors are shown in Fig. 6.It is worth mentioning that there is an equivalent carrierbased pulsewidth modulation (PWM) to the proposed SVPWMscheme, as the case for other SVPWM strategies. By arrangingthe three phase gating pulses in a center aligned profile,the carrier based PWM would be equivalent to the pro-posed SVPWM. Details of finding the equivalent carrierbased PWM to one SVPWM scheme are discussed in [33].However, the proposed SVPWM strategy could provide otherflexibilities to realize parallel control objectives like com-mon mode voltage control with utilization of redundantswitching states, which is not easy to be implemented withcarrier based PWM approaches. With regard to the redundantswitching state, with the proposed SVPWM strategy, theinformation of redundant switching states can be extracted,and is readily available. In this paper, the SVPWM strategyis focused to modulate the output voltages. However, it ispossible to extend the modulation strategy to realize othercontrol objectives like common mode voltage elimination,switching loss minimization, and so on, using these redundantswitching states.

IV. MODELING AND CONTROL OF

GRID-CONNECTED CONVERTER

The block diagram of the grid-connected power sys-tem using the hybrid input switched converter, modulatedwith the proposed SVPWM strategy, is shown in Fig. 7.An LCL filter is utilized to improve the quality ofthe generated voltage waveform through eliminating the


switching frequency components. The state equations ofthe system in abc-coordinate system can be presentedas follows:

⎧⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎩

�vs = L f 1d�is

dt+ RL f 1�is + �vcf + �vn

�vcf = L f 2d�ig

dt+ RL f 2�ig + �vg − �vn

C fd�vcf

dt= (Rd + 1)(�is − �ig)

(7)

where

�vs =⎡

⎣vsa

vsb

vsc

⎤

⎦ �vg =⎡

⎣vga

vgb

vgc

⎤

⎦ �vc f =⎡

⎣vc f a

vc f b

vc f c

⎤

⎦

�is =⎡

⎣isa

isb

isc

⎤

⎦ �ig =⎡

⎣iga

igb

igc

⎤

⎦. (8)

The synchronous d − q frame control has the particu-lar advantage of controlling the active and reactive currentdirectly, which is very convenient for the power flow con-trol. The system-state equations in (7) can be mapped tothe dq0 synchronous coordinate system with the transforma-tion matrix as

T = 2

3

⎡

⎢⎢⎢⎢⎢⎣

cos(ωt) cos

(ωt − 2π

3

)cos

(ωt + 2π

3

)

− sin(ωt) cos

(ωt − 2π

3

)cos

(ωt + 2π

3

)

1

2

1

2

1

2

⎤

⎥⎥⎥⎥⎥⎦

.

(9)

After the transformation and small-signal perturbation, thesmall-signal model of the system in the synchronous coordi-nate system can be presented as (10), shown at the bottomof the page, where Vdc is the dc-link voltage; Dmd and Dmq

are the steady-state value of modulation index, while ddm and

dqm are the small signals of the modulation index. For the

grid-connected operation, the nominal output phase voltageis 110 V, while the nominal output phase current is 6 A,which gives a nominal power level of 2 kVA. As the dc-linkvoltage is 300 V, the modulation index is calculated to be 0.52(the effective dc-link voltage is 600 V due to the voltage gainfunction of the H-bridge stage) to achieve the desired phasevoltage level. As an LCL filter is used to smooth the gridcurrent, the parameters of the filtering inductors and capacitors

should be determined before the compensation of the loopgain.

A. Determination of the LCL Parameters1) Parameter of Converter Side Inductors: The value of

the converter side inductors can be determined based on therequirement of current ripple as

�i = Vdc/3

8L f 1 fsw. (11)

Take the current ripple as 10% of the peak value of the gridcurrent, the minimum value of the converter side inductor canbe calculated as L f 1 = 2.94 mH. Practically, a value of 3 mHis used for the converter side inductors.

2) Parameter of Filtering Capacitors: In general, funda-mental reactive power absorbed by filter capacitors should beless than 5% of rated power to avoid significant decrease ofpower factor. Thus, the value of the filtering capacitors can bedetermined as

C f = P

3 × 2π fL V 2g

× 5%. (12)

Substitute the known values in (12), the maximum value ofthe filtering capacitors can be calculated as C f = 7.3 μF.Practically, a value of 6.8 μF is used for the filteringcapacitors.

3) Parameter of Grid-Side Inductors: The value of thegrid-side inductors can be determined by the attenuation ratioof the harmonic currents at switching frequency. The harmoniccurrent attenuation ratio can be presented as

ig

is= 1

(2π fsw)2 L f 2C f + 1. (13)

By selecting the harmonic current attenuation to be 5%,the value of grid-side inductors can be determinedas L f 2 = 2.6 mH.

4) Resonant Frequency of the LCL Filter: The resonantfrequency of the LCL filter can be calculated based on thevalues as determined above

fres =√

L f 1 + L f 2

L f 1 L f 2C f= 1.64 kHz. (14)

5) Parameter of Damping Resistors: To avoid resonance,damping resistors valued as Rd = (1/3ωresC f ) = 5 � orlarger are usually placed in series with the filter capacitor,which can damp the resonance of the LCL filter.

d

⎡

⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

i ds

i qs

i dg

i qg

vdc f

vqc f

⎤

⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

/dt =

⎡

⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

− R f 1L f 1

ω 0 0 − 1L f 1

0

−ω − R f 1L f 1

0 0 0 − 1L f 1

0 0 − R f 2L f 2

ω − 1L f 2

0

0 0 −ω − R f 2L f 2

0 − 1L f 2

Rd+1C f

0 − Rd+1C f

0 0 ω

0 Rd+1C f

0 Rd+1C f

−ω 0

⎤

⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

⎡

⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

i ds

i qs

i dg

i qg

vdc f

vqc f

⎤

⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

+

⎡

⎢⎢⎢⎢⎢⎢⎣

DmdL f 1

VdcL f 1

0 0 0DmqL f 1

0 VdcL f 1

0 0

0 0 0 −1L f 2

0

0 0 0 0 −1L f 2

0 0 0 0 0

⎤

⎥⎥⎥⎥⎥⎥⎦

⎡

⎢⎢⎢⎢⎢⎢⎣

vdc

ddm

dqm

vdg

vqg

⎤

⎥⎥⎥⎥⎥⎥⎦

(10)


Fig. 8. (a) Bode plot of the system control to output transfer function withand without damping. (b) Bode plot of the damped system control to theoutput transfer function with and without PI compensation.

B. Compensation of Loop Gain

With reference to the control decoupling approach aspresented in [34], the transfer function of grid currents toconverter output voltages in synchronous dq0 frame can bepresented with assumption that R f 1 and R f 2 are small enoughto be neglected

G(s) = Rd C f s+1

L f 1 L f 2C f s3+(L f 1 + L f 2)RdC f s2+(L f 1+L f 2).

(15)

Substitute the parameters as calculated in the first stepinto (15), the bode plot of the transfer function is presentedin Fig. 8(a), the transfer function without damping resistorsis also included to show the comparison. A PI compensatoris designed to boost the loop gain, while to increase thebandwidth of the system. The transfer function of the PI com-pensator is shown as follows:

Gc(s) = 10(1 + 0.1s)

0.1s. (16)

The bode plots of the system control to the output transferfunction are shown in Fig. 8(b). From the figure, it can beclearly seen that the bandwidth of the system is boosted from30 to 200 Hz, while holds the phase margin of 90◦ with theinclusion of the PI compensator.

V. SIMULATION AND EXPERIMENTAL RESULTS

Simulations and experiments are conducted to verify theeffectiveness and viability of the seven-level input switchedconverter modulated with the proposed SVPWM strategyfor stand-alone and grid-connected operations. The stand-alone operation is conducted with open-loop strategy, whilethe grid-connected operation is conducted with close-loopstrategy. Scaled down parameters are used in this paperfor the proof of the concept. Modulation strategy remainsthe same for higher power, and hence, this concept canbe scaled to higher power level without changing the algo-rithm. The parameters used in the simulations and experi-ments of the stand-alone operation are listed in Table IV.For the stand-alone operation, different modulation depthsare implemented to explore the relationships among modu-lation index, voltage resolution, and voltage total harmonicdistortion (THD). The corresponding results are shownin Figs. 9–15. The gating pulses when the modulation index

TABLE IV

SIMULATION PARAMETERS FOR STAND-ALONE OPERATION

Fig. 9. Gating pulse patterns when (a) ma = 0.8 and (b) ma = 0.57.

Fig. 10. Simulation results of line voltages and phase currents. (a) ma = 0.8.(b) ma = 0.57, and line currents when (c) ma = 0.8, (d) ma = 0.57 [5ms/div].

Fig. 11. Simulation results of line currents in α-β plane. (a) ma = 0.8.(b) ma = 0.57.

(ma) is 0.8 and 0.57 are shown in Fig. 9(a) and (b), respec-tively, from which it can be clearly seen that the switch pairsS1 and S4, S2 and S5, and S3 and S6 are not gated on at thesame time. As mentioned before, the power switches in the H-bridge stage almost switch at line frequency. The waveforms ofthe three-phase line voltages, phase voltages, and line currentsunder different modulation depths are displayed in Fig. 10. Theline currents waveforms in α–β plane are shown in Fig. 11.In comparison of the results under both modulation indexes, itcan be observed that more voltage levels are available when the


Fig. 12. Frequency spectrum analysis at 5 kHz switching frequency.(a) ma = 0.8. (b) ma = 0.57.

Fig. 13. THD plot as a function of (a) modulation index when switchingfrequency is 5 kHz and (b) switching frequency when modulation indexis 0.57.

Fig. 14. Experimental waveforms of line voltages in stand-alone operation.(a) Line voltages when ma = 0.8 [200 V/div, 5 ms/div]. (b) Line voltageswhen ma = 0.57 [200 V/div, 5 ms/div]. (c) Line voltages when ma transientfrom 0.8 to 0.57 [200 V/div, 10 ms/div]. (d) Frequency spectrum of linevoltage when ma = 0.57.

modulation index is higher, which provides lower voltage THDand better power quality. To support this, the frequency spec-trum analysis of the line voltages for both cases is shown inFig. 12. The line voltage THD is 13.38% when the modulationindex is 0.8, while the THD is 18.31% when the modulationindex is 0.57. The harmonics around the switching frequency,5 kHz, can be observed from the figure. The relationshipof the voltage THD and the modulation index for the givenswitching frequency of 5 kHz is plotted in Fig. 13(a). As it canbe seen, the voltage THD decreases as the modulation indexincreases. It is worth mentioning that inverters usually operatewith high-modulation index to maximize the utilization of dclink capacitors. The relationship of voltage THD and switchingfrequency for the given modulation index of 0.57 is shown inFig. 13(b). From the figure, it can be seen that the voltageTHD does not significantly decrease as switching frequencyreaches to a specific level.

Fig. 15. Experimental results of line currents. (a) ma = 0.8. (b) ma = 0.57[2 A/div, 10 ms/div].

Fig. 16. Line voltages and line currents waveforms under active and reactivepower control with grid connection of the proposed system.

This relationship provides insightful information andguidance on the determination of switching frequency,addressing the tradeoff between the voltage THD andpower loss. Experiments are conducted with a scaled-downconverter prototype in the laboratory. The proposed SVPWMstrategy is implemented in TIs DSP (TMS320F28335), whilethe gating signals are generated with Xilinx Spartan 6 FPGA.The corresponding experimental results are presented inFigs. 14 and 15. In Fig. 14(a) and (b), the results of linevoltages under different modulation depths are presented, fromwhich it can be seen that the experimental results are consistentwith the simulation results. The line voltages when the modu-lation index transients from 0.8 to 0.57 are shown in Fig. 14(c).The line voltages transient between two modulation indexessmoothly without introducing much voltage overshoot.

Simulations are conducted to demonstrate the grid-connected operation of the converter. The nominal outputphase voltage is 110 V, while the nominal output phase currentis 6 A. As the dc-link voltage is 300 V, the modulation index iscalculated to be 0.52 (the effective dc-link voltage is 600 V dueto the voltage gain function of the H-bridge stage) to achievethe desired phase voltage level. According to the discussion inthe converter modeling part, the parameters for the LCL filterare determined as L f 1 = 3 mH, L f 2 = 2.6 mH, andC f = 6.8 μF. The voltage and current waveforms under activeand reactive power control scenarios are given in Fig. 16. Thesystem is operating under stand-alone mode, and the outputof the converter is connected with a three-phase RL load(R = 92 � and L = 21 mH) before t = 0.05 s. The operation


Fig. 17. The grid voltage and current waveforms (phase A and B) for grid-connected operation. (a) Pure active power is injected to the grid. (b) Purereactive power is injected to the grid. (c) Transient from pure reactive power toactive power injection. (d) Start-up transient [200 V/div, 2 A/div, 10 ms/div].

is switched to grid-connected mode at t = 0.05 s, at the sametime the Id reference steps from 0 to 5 A. Starting from thismoment, the active power begins to be injected to the gridfrom the power converter. The grid voltages and currents arein phase due to pure active power injection. At t = 0.15 s,the Id reference drops from 5 to −5 A, thus the active poweris transferred from the grid to the power converter. Duringthis time, the voltage and current waveforms are 180° phaseshifted. The Iq reference rises from 0 to 10 A at t = 0.25 s.With the references of this combination, the active power istransferred from the grid to the power converter, while thereactive power is transferred from the power converter tothe grid. The grid voltage and current waveforms with gridconnection are shown in Fig. 17. In Fig. 17(a), pure activepower is transferred from the power converter to the grid, andthe phase voltages and currents are in phase. Reactive poweris injected from the power converter to the grid, as shownin Fig. 17(b), while the phase voltages and phase currents are90° phase shifted. The transition from reactive power injectionto active power transmission is displayed in Fig. 17(c). Bothactive power and reactive power are transferred to the grid forthe case shown in Fig. 17(d), which also presents the start-uptransient.

VI. CONCLUSION

This paper presents an SVPWM strategy for multilevelconverters used in PV generation applications. This strategyhas been applied to a seven-level hybrid input switchedmultilevel converter, which is a cascade connected inputswitched and H-bridge power converters, adopted for eachphase. The proposed SVPWM strategy treats the multilevelconverter as a two-level converter by introducing an offsetvector for output voltage modulation. The offset vector andsystematic switching sequence determination procedures areprovided within the framework of this paper. The simulationand experimental results for stand-alone and grid-connectedoperations are presented to verify the validity of the proposedstrategy. The results demonstrate the following advantages:1) the switching-state transitions are minimum, and thus, input

switched converter can be switched at very low frequencies;2) the H-bridge converter is switched at close to linefrequency; and 3) low-computation cost due to operation insubvector space similar to two-level converters.

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Xiong Li (S’13) received the B.E. (Hons.) degree inelectrical engineering from Central South University,Changsha, China, in 2011. He is currently workingtoward the Ph.D. degree with the Power Electronicsand Drives Laboratory, University of Texas at Dallas,Richardson, TX, USA.

His current research interests include the controlof multilevel converters with applications for renew-able energy systems, design of power electronicinterfaces, and energy management strategies forrenewable energy sources.

Serkan Dusmez (S’11) received the B.S. (Hons.)and M.S. degrees in electrical engineering fromYildiz Technical University, Istanbul, Turkey, in2009 and 2011, respectively, and the M.S. degreein electrical engineering from the Illinois Instituteof Technology, Chicago, IL, USA, in 2013. He iscurrently pursuing the Ph.D. degree with the Uni-versity of Texas at Dallas, Richardson, TX, USA.

He was a Faculty Research Assistant with thePower Electronics, Energy Harvesting and Renew-able Energies Laboratory, Department of Electrical

and Computer Engineering, University of Maryland at College Park, CollegePark, MD, USA, from 2012 to 2013. He has authored or co-authored over35 journal and conference papers. His current research interests include designof power electronic interfaces and energy management strategies for renewableenergy sources, integrated power electronic converters for plug-in electric, andreal-time fault diagnosis of power converters.

Udupi Rajagopal Prasanna (M’11) received theB.E. degree in electrical and electronics engineeringfrom the National Institute of Technology Karnataka,Surathkal, India, in 2006, and the Ph.D. degree inpower electronics and alternate energy conversionfrom the Indian Institute of Science, Bangalore,India, in 2011.

He was a Post-Doctoral Research Fellow with theDepartment of Electrical and Computer Engineering,National University of Singapore, Singapore, until2013. He is currently with the University of Texas

at Dallas, Richardson, TX, USA, as a Research Scholar. His current researchinterests include high-frequency soft-switching power converter, hybrid energymanagement in the field of alternate energy sources, hybrid electric vehicles,fuel cell vehicles, and modeling of multidisciplinary energy systems usingbondgraph technique.

Dr. Prasanna is a reviewer of the IEEE TRANSACTIONS, the Institution ofEngineering and Technology, the Journal of Franklin Institute (Elsevier), andInderscience.

Bilal Akin (S’03–M’08–SM’13) received theB.S. and M.S. degrees in electrical engineeringfrom Middle East Technical University, Ankara,Turkey, in 2000 and 2003, respectively, and thePh.D. degree in electrical engineering from TexasA&M University, College Station, TX, USA, in2007.

He was a Research and Development Engi-neer with Toshiba Industrial Division, Houston,TX, USA, from 2005 to 2008. From 2008 to 2012,he was a Research and Development Engineer with

the C2000 Embedded Control Group, Texas Instruments Incorporated, Dallas,TX, USA. Since 2012, he has been with the University of Texas at Dallas,Richardson, TX, USA, as an Assistant Professor. His current research interestsinclude advanced control methods in motor drives, real-time fault diagnosis ofindustrial systems, digital power management, renewable systems, and variousDSP-based industrial applications.


Kaushik Rajashekara (M’86–SM’89–F’99)received the B.Eng., M.Eng., and Ph.D. degreesfrom the Indian Institute of Science, Bangalore,India.

He joined Delphi Corporation, Kokomo, IN,USA, in 1989, which was a division of GeneralMotors (GM), Detroit, MI, USA. At Delphi andGM, he held various technical and managerialpositions. He was also a Technical Fellow andthe Chief Scientist for propulsion, advanced drivesystems, and fuel cell-based on-board power

generation. In 2006, he joined Rolls-Royce Corporation, Indianapolis, IA,USA, as the Chief Technologist for electric power and control systems.He was also an Adjunct Professor with the School of Engineering, PurdueUniversity, West Lafayette, IN, USA, from 1992 to 2006. Since 2012,he has been a Distinguished Professor of Engineering and the EndowedChair of the Erik Jonsson School of Engineering and Computer Sciencewith the University of Texas at Dallas, Richardson, TX, USA. He hasauthored over 100 papers and holds 35 patents on power conversion relatedto electric, hybrid, and fuel cell vehicles. He has given over 100 invitedpresentations in various international conferences and local IEEE chapters.

His current research interests include power conversion and control in theareas of electrification of transportation and renewable energy systems.

Prof. Rajashekara was elected as a member of the U.S. National Academyof Engineering (NAE) for contributions to electric power conversion systemsin transportation in 2012, and as a Foreign Fellow of the Indian NAE in2012. He has been a fellow of the SAE International for contributions to theadvancement of power conversion and propulsion systems since 2006. He wasa Distinguished Lecturer of IEEE IAS from 2006 to 2007, and a ProminentLecturer from 2008 to 2011, and is currently a Distinguished Lecturer ofthe IEEE Vehicular Technology Society. He was inducted into the DelphiInnovation Hall of Fame in 1999, and received the Delphi President’s Award.He was a recipient of the IEEE Richard Harold Kaufmann Award for outstand-ing contributions to the advancement of electrical systems in transportation in2013, the IEEE Industry Applications Society (IAS) Outstanding AchievementAward for outstanding contribution for the application of electricity to industryin 2009, and the IEEE IAS Gerald Kliman Award for contributions to theadvancement of power conversion technologies through innovations and theirapplications to the industry in 2006. He was also a recipient of the 2013Distinguished Alumnus Award of the Indian Institute of Science, and the2012 SAE Charles M. Manly Memorial Medal for outstanding technicalpaper.

Documents

A New SVPWM Modulated Input Switched Multilevel Converter for Grid-Connected PV Energy Generation Systems