Addition (2)

Outline

• Full Adder• 3-Bit Adder• 2’s Complement• Subtraction

A Half Adder

A half adder is useful for adding LSB.

Limitation of a Half Adder

A half-adder does not account for carry-in.

Derivation of the Sum Bit (∑) of a Full Adder

Cin ∑half B A ∑full

0 0 0 0 0

0 1 0 1 1

0 1 1 0 1

0 0 1 1 0

1 0 0 0 1

1 1 0 1 0

1 1 1 0 0

1 0 1 1 1

A+B can be derived from the ∑half of the half adderThe sum of Cin and ∑full can be derived from an XOR gate!

Perhaps this suggests that I need another half adder!

Derivation of the Carryout Bit of a Full Adder

• Since the Co bit in a half adder is generated by an AND gate, let’s AND ∑HA and Cin and see what we get!

Derivation of the Co bit of a Full AdderCin∙∑half Cin ∑half Co,half B A Co of

the full

adder0 0 0 0 0 0 0

0 0 1 0 0 1 0

0 0 1 0 1 0 0

0 0 0 1 1 1 1

0 1 0 0 0 0 0

1 1 1 0 0 1 1

1 1 1 0 1 0 1

0 1 0 1 1 1 1

Cin∙∑half generates partially correct Co.So far, we have not used information from the output of the half adder.So let’s use Co,half in the full adder circuit….

Truth Table of Co of a Full Adder Cin B A Co

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Identical to ∑ of a Half Adder

Use a Half Adderwith Cin and ∑HA to generate Co

Schematic of a Full Adder

Derivation of the Sum Bit (∑) of a Full Adder

Cin B A ∑full

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

++ +

(+)+Cin(+A)

B)

Derivation of the Co bit of a Full AdderCin B A Co of

the full

adder0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

++ +

B)+ + )= B)+AB

A 3 bit parallel adder

• Since it is only possible to show magnitude witha binary number, the sign (+) or (-) is shown by adding an extra “sign” bit.– A sign bit of 0 indicates a positive number.– A sign bit of 1 indicates a negative number.