Adv CMOS Jongholee

8/13/2019 Adv CMOS Jongholee

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Semiconductor Materialsand Device Laboratory

Jong-Ho Lee

[email protected]

School of EECS and ISRC, Seoul National University

Bulk FinFETs: Fundamentals,

Modeling, and Application


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1

Introduction

Fundamentals of Bulk FinFETs

Modeling

Applications

Conclusions

Outline


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The scaling of conventional planar MOSFETs has been facing

problems such as subthreshold swing degradation, significant

DIBL, fluctuation of device characteristics, and leakage.

To solve the problems, 3-D device structures could be a solution

and have been studied.

FinFETs (built on bulk silicon or SOI wafers) among 3-D devices

are very promising candidate for future nano-scale CMOS

technology and high-density memory application.

For the bulk FinFETs which is going to be applied to mass

production, we discuss about fundamental properties, modeling,

and application of the bulk FinFETs.

Introduction

2


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Whats bulk FinFET?

FinFET

SOI FinFET Bulk FinFET

3-D view ofbulk FinFET

Si Sub

SiO2

G fin

Si Sub

SiO2

G fin

Low wafer cost

Low defect density

No floating body effect

High heat transfer rate

to substrate

Good process compatibility

S/D

S/D

Hin xj

WinTOX

Heat

Korea/USA patent

Bulk FinFETs (Double- or Tri-gate MOSFETs)

ID-VGS Characteristics of 40 nm bulk N FinFET

3


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S/D

S/D

H in xj

W inT OX

Heat

Comparison between Our Structure and Intels

Our Structure Intels StructureConventionalPlanar Structure

4


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5

As+, 20 keV 3x1015/cm2, 2 Fin

25 nm

50 nm

40 nm

-0.5 0.0 0.5 1.0 1.510-10

10-9

10-8

10-7 VDS = 0.1 V

Vbs = 0 V

Vbs = -1 V

Vbs = -2 V

DrainC

urrent(A)

Gate Voltage (V)

ID-VGS Characteristics of 40 nm bulk N FinFETOxide

Si

CMP and

partial etch-back

Poly-Si

40 nm

Gate Poly-Si Etching

T. Park et al., SNU/KNU, Physica E19, p.6, 2003T. Park et al., SNU/KNU, Nanomes03 2003

Top Si Width 25 nm

Bottom Si Width 100 nm

Si Fin Height 230 nm

First Bulk FinFET in the World


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T. Park et al., SNU/Samsung/KNU, p.135, Symp. on VLSI Tech. 2003

-0 .5 0.0 0.5 1.0 1.5 2.010

-14

10-13

10 -12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

Conv. DRA M C el l Tr .DIBL = 108 m V/V

Vds = 0.1 V

Vds = 0.6 V

Vds = 1.1 V

Vds = 1.6 V

Dra

inCurrent(A

)

G ate Vol tage (V)

Vbs = 0 V

FinFET

DIBL = 24 mV /V

Fin Top W idth = 30 nm

Fin Bottom Width = 61 nm

Fin Height = 99 nm

LD R A W N

= 120 nm

W = 120 nm

L = 120 nm

181 nm

99 nm

61 nm

30 nm

82

Si Substrate

SiO2

Poly-Sifin body

SEM cross-section

Gate

Electr

ode

SiO2

SiN

SiSubs

trate

Fin

SiO2

6

First Bulk FinFET at Industry


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7

Introduction


Modeling

Applications

Conclusions

Outline


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Gate

Oxide

Fin

Gate

Fin

Gate

Fin

(a) (b) (c)

DG Structure TG Structure

90o Corner Half-circle Corner

8

Body Shape of FinFET


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10 20 30 40 500.1

0.2

0.3

0.4

0.5

Nb=1x10

19cm

-3

Tox

=1.5 nm

xj,S/D

=66 nm

Hfin

=70 nm

Bulk

SOI

Fin Width (nm)

V

th

(V)

Lg

=25 nm

0

30

60

90

120

150

180

DIBL(mV/0.9V)

10 20 30 40 50

70

75

80

85

90

95

100

xj,S/D

=66 nm

Hfin

=70 nm

Nb=1x10

19cm

-3

Tox

=1.5 nmLg=25 nm

VDS

=0.9 V

Subthreshold

Swing(mV/dec)

Fin Width (nm)

BulkSOIVDS

=0.05 V

The bulk FinFETs (solid circles) have nearly the same Vth, DIBL, and SS

characteristics as those of SOI FinFETs (open circles).

Vth & DIBL SS

9

Equivalent FinFET on Bulk and SOI Wafers


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Equivalent FinFET on Bulk and SOI Wafers

Tri-gate on bulk-silicon and SOI substrates have similar short channel

performance

Source: Intel


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Heat transfer rate : Bulk SOI

Bulk FinFET has a device temperature less by 130 oC than SOI FinFET at a

fixed VGS of 0.9 V.

-0.2 0.0 0.2 0.4 0.6 0.8 1.0

300

325

350

375

400

425

450

475

130oC

Bulk

SOI

VDS=0.9 V

Tox

=1.5 nm

DeviceTemperature

(K)

Gate Voltage (V)

Lg=30 nm

12

Device Temperature Characteristics

Si Nanoelectronics, 102-103, 2003


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-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50

0.0

0.1

0.2

0.3

0.4

0.5

WFin

: 10, 15, 20, 30, 50 nm

WFin: 10, 15, 20, 30, 50 nm

Body Bias (V)

VT

(V)

70

80

90

100

110

120

Subthresh

oldSwing(m

V/dec)

LG=25 nm

No VT increase ata given back bias

S B

G G

Silicon Nanoelectronics workshop, p.102, 2003

Back-bias Effect

Properties of Bulk FinFETs13


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80 82 84 86 88 90 9280

90

100

110

120

LG=30 nm

HFin=70 nm WFin =20 nm

Angle () (deg)

DIBL(mV/V)

Na=1x10

19cm

-3

n+

poly gate

70

80

90

100

110

120

SS(mV)

20 nm

Fin

-0.2 0.0 0.2 0.4 0.6 0.8 1.00.6

0.7

0.8

0.9

1.0

1.1

1.2

VDS

=0.9 V

VDS=0.05 V

WFin

=20nm

HFin

=70nm

LG

=30nm

90o

83.3o

81.6o

Gate Bias (V)

N

ormalizedDrain

Current

Device Characteristics with Body Angle

Tapered fin widens degradedSCEs

Closer to 90o of body angle, better

DIBL and drain current


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Impact of Fin Profile

Rectangular Fin profile improves SCEs for LG scaling:

Lowers SSATLowers DIBL

Symp. on VLSI Tech, Intel, 2006


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Gate

Fin

Si Substrate

Gate

Fin

BOX

(a) (b) (c) (d)

Bulk SOI

Gate

Fin

BOX

Gate

Fin

BOX

Process variation

17

Bottom Corner Effect

Invited talk at ECS, ECSTransactions, 19 (4) 101-112 (2009)


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Ioff : (a) < (b) < (c) < (d)

-0.2 0.0 0.2 0.4 0.6 0.8 1.010

-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Hfin

=70 nm

VDS

=0.05 V

VDS

=0.9 V

n+poly gate T

ox=1.5 nm

Wfin

=20 nm

Lg=100 nm

Bulk FinFET (a)

SOI FinFET (b)

SOI FinFET (d)

ID(A)

VGS

(V)

Nb=2x10

18cm

-3

(a) (b) (c) (d)0.01

0.02

0.03

0.04

0.05

0.06

SOI

Thresho

ldVoltage(V)

Bulk

Vth : (a) > (b) > (c) > (d)

ID vs VGS Vth vs Structure

18

Bottom Corner Effect


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Wfin DIBL & Vth

Low doped bulk or SOI FinFETs narrow Wfin for good characteristics

5 10 15 200.30

0.32

0.34

0.36

0.38

0.40

Simulation

Model

Fin Width (nm)

Vth

(V)

Hfin=70 nm

Lg=30 nm

Nb=5X1016cm-3

m=4.71 V

0

50

100

150

200

250

300

350

body

Si substrate

WFin

GateTOX

oxide

Local doping @ xP=80 nm

DIBL(mV/V

)

Rounded corner

corner effect

Low doped channel

Nb=5x1016 cm-3

Local doping

xp=80 nm

NLocal=3x1018 cm-3

19

Fin Body Width Effect of Bulk FinFET with Low Nb


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Planar MOSFET : Delay Time (due to Vth) with negatively increasing VBS

SOI or Bulk FinFETs : nearly constant Delay Time with VBS more

effective devices for the full-down circuits

-0.50 -0.25 0.00 0.25

0.8

1.0

1.2

1.4

1.6

Planar MOSFETBulk FinFET

SOI FinFET

Norma

lizedDelayTim

e

VBS(V)

Nb=2x10

18cm

-3C=20 fF

Tox

=1.5 nm Lg=50 nm

-0.50 -0.25 0.00 0.25

0.8

1.0

1.2

1.4

1.6

V1

CVb

Vcc

Vin

Full-down delay time vs VBS Inverter circuit

Speed Characteristics

ECS meeting (invited talk), May, 2008

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(a) Small signal equivalent circuit for RF device modeling.

(b) Comparison of RF parameters extracted from bulk and SOI DG FinFETs.

CgdRg

vgs

Gate

Drain

Substrate

gmvgsCm dt

dVgsCgs

gmbvbs

gds Csd

vbs

CjdCjs

Rsub

Source

P

O

R

T

1

P

O

R

T

2

Intrinsic Body

CgdRg

vgs

Gate

Drain

Substrate

gmvgsCm dt

dVgsCm dt

dVgsCgs

gmbvbs

gds Csd

vbs

CjdCjs

Rsub

Source

P

O

R

T

1

P

O

R

T

2

Intrinsic Body

177 GHz170 GHzfT

-0.0033 fF-0.0037 fFCsd

-fF0.0151 fFCjs

-8200 Rsub

-fF0.014 fFCjd

472 461 Rg

0.038 fF0.037 fFCgd

0.073 fF0.0713 fFCdg

0.113 fF0.116 fFCgs

0.414 S0.427 Sgds

166 S160 Sgm

0.286 V0.31 VVth

SOI DG

FinFET

Bulk DG

FinFET

177 GHz170 GHzfT

-0.0033 fF-0.0037 fFCsd

-fF0.0151 fFCjs

-8200 Rsub

-fF0.014 fFCjd

472 461 Rg

0.038 fF0.037 fFCgd

0.073 fF0.0713 fFCdg

0.113 fF0.116 fFCgs

0.414 S0.427 Sgds

166 S160 Sgm

0.286 V0.31 VVth

SOI DG

FinFET

Bulk DG

FinFET

(a) (b)

21

Speed Characteristics


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20 30 40 50 60 700.1

0.2

0.3

0.4

0.5L

g=100 nm

Tox

=1.5 nm

VGS

=1.0 V, VDS

=1.5 V

Na=3x10

18cm

-3

c=1x10

-7cm

2

n+poly gate

Solid : d=100 nm

Open : d=5 nm

Fin Width (nm)

Vdrop

(V)

2000

2200

2400

2600

2800

3000

3200 PeakElectronTempe

rature(K)

Effect of S/D Resistance with Fin Body Width

Wfin electron temp.

: Ohmic drop across Rsd (Wfin less than 50 nm)

Rsd=Ras+Rsh+Rc

22


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25/45


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25

Introduction


Modeling

Applications

Conclusions

Outline


27/45

2-D schematic view of symmetric

double-gate MOSFET.

Gate

Gate

Source

(n+)

Drain

(n+)Fin

Body

Lov

Tox

Wfin

L

Lg

VGS

VGS

VDS

Oxide

y

x

0

Bulk FinFET or SOIFinFET (not shown)

Side-channel

S/D

S/D

TFOX

A

A

Side-channel of bulk or SOI FinFETs :

DG structure key point

26

Schematic View of DG MOSFETs


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27

Short-channel effect

xm xm

S D

xls xld

Lc=L-2xm

xrs=xcs xrd=xcd

S

(a) (b)

xcs

xhs

G

G

Tox

Wfin

SiO2

SiO2

b dep hs hd th ,SC E

ox c

qN x x x / 2V

C L

b dep

th ,SCE FB B

ox

h

c

qN xV V 2 1

C

x

L

Charge-sharing length

hs hd

h

x xx

2

: Vth model of the conventional

planar MOSFETs

:DG M OSFETsfin

0.5W

Vth Modeling of Side-Channel (1)


29/45

28

Narrow-width effect

S DG

xhs xhdLg

Hg

Lc

xdf

(a) SiO2 SiO2Fin

Body

xdf

Hg G G

TgateTox

Wfin

(b)

b d e p d f

t h , N W E o x g

q N x x

V C 4 H

gateox

th ,s 2

dep b

d

ox

f

T8V ln 1

x qNx

T

: an effective widthdepleted by gate fringingfield

Vth Modeling of Side-Channel (2)


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Vth Modeling of Bulk FinFETs

g

M S B

E

2 e

b d e p d f t h , N W E

o x g

q N x xVC 4 H

gateox

of

ox

T2C ln 1

T

gateox

df th ,w oc 2

dep b ox

T8x V ln 1

x qN T

b dep df h

th ,w oc FB B w

ox m g

qN x xxV V 2 1

C L 2 x 4 H

b dep hs hd

th ,SCE

ox m

qN x x xV

C 2 L 2 x

Vth equations of bulk FinFETs based on 3-D charge sharing

SCE

NWE

: in NMOSFET with n+ poly gate

Thexdf and the

Vth,woc are

obtained by

solving theseequations

b dep h

th ,SC E FB B

ox m

qN x xV V 2 1

C L 2 x

IEEE Trans on Electron Devices, p. 537, 2007

29

30


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0.0 0.2 0.4 0.6 0.8 1.0

0.08

0.12

0.16

0.20

WB=15 nm

L=60 nm

gm,max

Method

Proposed Model

CC Method

L=30 nm

L=190 nm

Vth

(V)

VDS

(V)

Tox

=1.5 nm

Nb

=5x1018

cm-3

n+poly gate

Vth0

0.0 0.2 0.4 0.6 0.8

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Simulation

Proposed Model

CC Method

ID(mA/m)

VDS

(V)

n=200 cm2

/V-sec n+

poly gateW

B=15 nm

Tox

=1.5 nm

VGS

=0.4 V

L=30 nm

Nb=2x10

18cm

-3

VDS,sat

=0.426 V

Nb=5x10

18cm

-3

VDS,sat

=0.271 V

Vth Model Considering Drain Bias

Jpn. Journal of Applied Physics

Verification in Double-Gate MOSFETs

30


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32


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0.0 0.2 0.4 0.6 0.8 1.010

-10

10-9

10

-8

10-7

10-6

10-5

10-4

10-3

VGS

(V)

ID(A/m)

Nb=5x10

18cm

-3

Wfin

=15 nm

Tox

=1.5 nm

VDS

=0.05 V

n=200 cm

2/V-sec

n+poly gate

0.0

0.2

0.4

0.6

0.8

1.0Simulation

Model

ID(mA/m)

Vth=0.1297 V

L=30 nm

L=190 nmV

th=0.1899 V

0.0 0.2 0.4 0.6 0.8

0

2

4

6

Simulation

Model

I

D,drift(mA/m)

VDS

(V)

Nb=5x10

18cm

-3

n+poly gateW

fin=15 nm

VGS

=0.4 V

Tox=1.5 nm

n=200 cm

2/V-sec

L=30 nm

VDS,sat

=0.274 V

VDS,sat

=0.679 V

VGS

=0.8 V

Nb=5x1018 cm-3, Wfin=15 nm, Tox=1.5 nm, n=200 cm

2V-1s-1

ID vs VGS ID vs VDS

Models show a good agreement with simulation data.

32

DC Models of Doped DG MOSFETs (3)

33


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33

oxide

Si substrate

Gate

Body

Wsc

Ws

WtcWtc

channel

Wsc

Ws

Hg

xh

bodyWfin

Gate

Tox

r

xdep

Wc

(a) (b) (c)(a) Schematic 3-D view for considering the

corner effect

(b) Cross-sectional view of the fin body

with 90 o corner

(c) Cross-sectional view of the fin body

with half-circle corner

Schematic Views for Considering Top Corner

Effect

33

34


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h2 x

13 L

,

' 0.5 2

2 13

c b fin hFB B

ox

th c

q N WV

CV

L

Vth,s model for side-channel with a fully depleted fin body

Vth,c model for corner-channel with a fully depleted fin body

: SCE term in the corner region regardless of the corner shape

: Corner Vth model

Corner factor(=0.4)

: Fitting parameterCorner-channel

b fin dfhF B B

ox g

th ,s

qN 0.5W xV 2 1

C L 4 H V

SCE & NWE

Side-channel

SCE NWE

bulk FinFET only

34

Vth Model of FinFET with Top Corner (1)

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20 30 40 50 60 70 80 90 100-0.2

0.0

0.2

0.4

0.6

0.8

1.0

c=0.4

VDS=0.05 V

n+poly gate

Nb=5x10

18cm

-3

MS

=-1.0683 V

W fin=20 nmH

fin=70 nm

Tox

=1.5 nm

Nb=10

19cm

-3

MS

=-1.0862 V

oxide

Si substrate

body

WFin

GateTOX

Si substrate

oxide

Simuation

Model

Vth

(V)

Gate Length (nm)

5 10 15 20

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7Gate

Tox

body

Si substrate

oxide

Wfin Hg

c=0.4

Nb=5x10

18cm

-3

MS

=-1.0683 V

Nb=10

19cm

-3

MS

=-1.0862 V

Lg=100 nm

Simuation

Model

Vth

(V)

Wfin

(nm)

n+poly gate

Tox

=1.5 nm

VDS

=0.05 V

Hfin

=70 nm

Vth vs Lg Vth vs Wfin

Models show a good agreement with simulation data.

Hfin=70 nm, VDS=0.05 nm, Tox=1.5 nm, n+ poly gate

35

Vth Model of FinFET with Top Corner (3)

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Vth Modeling of Bulk FinFETs

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0Mod.

c=0.25

Lg=100 nm

m=4.71 V

m=4.17 V

10.60.3

Radius Ratio [=r/0.5Wfin]

r

0.5Wfin

Body

Nb=1x1019cm-3, H

g=70 nm

Nb=5x10

18cm

-3, H

g=70 nm

Nb=5x10

18cm

-3, H

g=40 nm

Nb=2x10

18cm

-3, H

g=70 nm

Vth

(V)

0

VDS

=0.05 VW

fin=20 nm

Sim.

30 40 50 60 70 80 90 100-0.2

0.0

0.2

0.4

0.6

0.8

1.0

c=0.25

VDS

=0.05 Vn

+

poly gate

Nb=5x10

18cm

-3

MS

=-1.0683 V

Wfin

=20 nm

Hg=70 nm

Tox

=1.5 nm

Nb=10

19cm

-3

MS=-1.0862 V

oxide

Si substrate

body

WFin

GateTOX

Si substrate

oxide

SimuationModel

Vth

(V)

Gate Length (nm)

Verification of the Model

IEEE Trans on Electron Devices, p. 537, 2007

36

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3-D schematic view 2-D schematic view

Bulk FinFET

as an example

S/D

S/D

Hg

XjSDE

0

WfinTFOX

A

A

body

Gate

Si substrate

oxide

Top-channelregion

Field

penetrationregion

from top-gate

Electricfield

The electric field penetration region

(hatched triangle) from the top-gate into

the side-channel region.

Current Model of FinFET (1)

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ID vs VGS

With Vth,s & Vth,c

Before considering field penetration

effect

With Vth0,s & Vth0,t

After considering field penetration

effect

-0.2 0.0 0.2 0.4 0.6 0.8 1.010

-14

10-13

10-12

10-1110

-10

10-9

10-8

10-7

10-6

10-5

10-4

Hg=70 nm

VDS

=0.05 V

Wfin

=20 nm

Lg=100 nm

Simulation

Side-channel (model)

Top-channel (model)

Total (model)

ID(A)

VGS(V)

Nb=5x10

18cm

-3

-0.2 0.0 0.2 0.4 0.6 0.8 1.0

0.0

1.0x10-5

2.0x10-5

3.0x10-5

Simulation

Side-channel (model)

Top-channel (model) Total (model)

ID(A)

Nb=5x10

18cm

-3

Lg=100 nm

Wfin

=20 nm

VDS

=0.05 V

Hg=70 nm

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

ID(A)

VGS

(V)

Current Model of FinFET (5): An Example

39


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ID vs VGS

Continuous Current Model of DG MOSFET

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

1.0x10-5

2.0x10-5

3.0x10-5

4.0x10-5

5.0x10-5

6.0x10-5

7.0x10-5

8.0x10-5

9.0x10-5

1.0x10-4

0.0 0.2 0.4 0.6 0.8 1.010

-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Simulation

Nb= 2x10

18cm

-3

Nb= 10

18cm

-3

Nb= 10

17cm

-3

Nb= 0 cm

-3

ModelId(A)

Vgs

(V)

Vds

=1V

tox

= 1.5nm

tb= 10nm

Lg= 1m

W = 1m

Lines: Model

Symbols: Simulation

g=bg= midgap when Nb=0

No source/drain resistances

Good agreement

From intrinsic to ~1017 cm-3:

nearly the same

bsi

bb

t

x

q

kTtxqNx

2coslncosln

2

8

)4()(

22

.tan4

2

oxb

oxsi

ox

oxbbfbgs

qt

kTtttqNVV

.22/

0

)(

d

s

b

ft

kT

q

i

f

g

nd eqndL

WI

40


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Introduction


Modeling

Applications

Conclusions

Outline

S f41


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First SRAM Application of Bulk FinFET

Bulk FinFETControl planar FET Nano width planar FET

Inverter

schematic

SNM Comparison

IEDM, p.27, 2003

SEM

Top

view

IEEE Trans on Electron Devices, p.481, 2006

B lk Fi FET i SRAM C ll42


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Si

SiO2

SiN

GatePoly

-Si

SiFin

-1.00 -0.75 -0.50 -0.25 0.00 0.25

10-10

10-9

10-8

10-7

10-6

10

-5

10-4

10-3

10-2

10-1

DrainCurre

nt(A)

Gate Voltage (V)

Triple Gate PMOSFET, Vds = -0.1 V

Triple Gate PMOSFET, Vds = -1.1 V

Planar PMOSFET, Vds = -0.1 V

Planar PMOSFET, Vds = -1.1 V

VBS

= 0 V

-2.5 -2.0 -1.5 -1.0 -0.5 0.0

0.0

-1.0x10-5

-2.0x10-5

-3.0x10-5

-4.0x10-5

-5.0x10-5

-6.0x10-5

-7.0x10-5

DrainCurre

nt(A)

Drain Voltage (V)

VBS

= 0 V

Solid : Triple Gate PMOSFET

Dashed : Planar PMOSFET

IEEE Electron Device Letters, p. 798, 2004

Bulk pFinFET in a SRAM Cell

SEM View and I-V Curves of pMOSFET

SEM view

ID-VGS curves

ID-VDS curves

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World 1stSaddle MOSFET for DRAM Cells

Si sub.

S/D

SiO2

Fin body

Gate A`

A

BB`

IEEE Electron Device Letters, p. 690, 2005

A A`

B B`

xjS /D

Gateinsulator

G

ate

S /D

L g

Gateinsulator

Gate

S iO 2

Si sub.

W fin

L ov_side

Localdoping

-0.3 0.0 0.3 0.6 0.9 1.2 1.510

-16

10-14

10-12

10-10

10-8

10-6

10-4

Saddle m 4.71 V

Recess m 4.17 V

VDS

=

0.05 V 1.5 V

Saddle

Recess

Drain

Current(A)

Gate Voltage (V)

Lg=12 nm W

fin=20 nm T

ox=3.5 nm

Recess depth=50 nm

xjS/D,LDD

=21 nm

xjS/D,HDD

=33 nm

Schematic View and Comparison of I-V Curves

Saddle Recess

SS 69.5 132

DIBL 21 170

Schematic view

Korea/USA patents

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Summary

Brief introduction

Fundamentals of Bulk FinFET

- Nearly the same scalability and performance as those of SOI

FinFET, and has several advantages

- Body shape, temperature, back-bias, S/D resistance, and speed- Design guideline on body doping and width

Model explains very well the behavior of Vth, internal physics, and

I-V of double/tri-gate bulk FinFETs

Bulk FinFETs could be applied to SRAM, low-power logics, and be

modified to DRAM cell

Documents

Adv CMOS Jongholee