AEA c4 diode circuit L4 - hcmut.edu.vntcdungnghi/AEA_PFIEV_S1_AY1213/AEA_c4_diode_circu…Full-wave rectifier (Chỉnh lưu toàn sóng) • The transformer secondary winding is center-tapped

Diode Circuits

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Diode models

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Diode models

3 !!!!!!!Trương!Công!Dung!Nghi

Rectifier circuits (Mạch chỉnh lưu)

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Input voltage Transformer o/p Rectifier o/p Filter o/p DC o/p voltage voltage voltage voltage

Block diagram of a dc power supply


Transformer

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1:2

120 Vac 240 Vac

Step-up

4:1

120 Vac 30 Vac

Step-down

1:1

120 Vac 120 Vac

Isolation

VP

Primary(input)

Secondary(output)

VS

IP IS

NP NS

• If perfect flux linkage between the primary and the secondary windings is assumed, then

orNS

NP=

VS

VP

NS

NP=

IPIS


Transformer• Ex: The fuse shown in following figure is used to limit the current in

the primary of the transformer. Assuming that the fuse limits the value of IP to 1A, what is the limit on the value of the secondary current?

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Load

1:41AF1

IS =NP

NSIP =

1

4(1A) = 250mA


Half-wave rectifier (Chỉnh lưu bán kỳ)

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RL

RL

VL

VL

VP

VP VS

VS


Half-wave rectifier (Chỉnh lưu bán kỳ)

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RL VLVP VS

VL(pk) = VS(pk) � VD

VS(pk) =NS

NPVP (pk)

Vpk =p2Vrms


Half-wave rectifier (Chỉnh lưu bán kỳ)• Ex: Using the piecewise-linear diode model, sketch the transfer

characteristic vO versus vS and the waveform of vO.

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vS < VD0 : vO = 0

vS � VD0 : vO =R

R+ rD(vS � VD0)


Half-wave rectifier (Chỉnh lưu bán kỳ)• Ex: Using the piecewise-linear diode model, sketch the transfer

characteristic vO versus vS and the waveform of vO.

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Rectifier design - important parameters• Current-handling capability required of the diode, determined by the

largest current the diode expected to conduct.• Peak inverse voltage (PIV): the maximum inverse voltage that the

diode must be able to withstand without breakdown, determined by the largest reverse voltage that is expected to appear across the diode.

• Ex:

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PIV = VS (pk) for half-wave rectifier


Full-wave rectifier (Chỉnh lưu toàn sóng)• The transformer secondary winding is center-tapped to provide two

equal voltage across the two halves of the secondary winding.

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InputSignal

Full-waverectifier output

F1

Load


Full-wave center-tap rectifier

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F1

VLIL

IP(pk)

2SV≅

F1

VLIL

IP (pk)

2SV≅


Full-wave center-tap rectifier• Ex: Determine the dc (average) load voltage for the circuit shown in

the following figure, using the constant-voltage-drop model with VD = 0.7V.

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F1

VLRL5.1k!

D1

D2

30 Vac

15

15

0

VL(pk) =VS(pk)

2� 0.7V

VL(dc) =2VL(pk)

⇡

VS(pk) =p2VS(rms) =

p2⇥ 30V = 42.4V


Full-wave center-tap rectifier• Ex: Determine the peak inverse voltage of the following circuit,

assuming the diodes to be ideal.

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F1

VLRL5.1k!

D1

D2

34 Vpk

+17Vpk

0

(on)

(off)

34 Vpk

-17Vpk24Vac

PIV = 2VL(pk) = VS(pk)


Full-wave bridge rectifier

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InputSignal

Full-waverectifier output

F1

Load

D2

D1

D3

D4


Full-wave bridge rectifier

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F1D2

D1

D3

D4 VL

VS

F1D2

D1

D3

D4 VL

VS


Full-wave bridge rectifier• Ex: Determine the load voltage value for the circuit shown in figure,

using the constant-voltage-drop model with VD = 0.7V.

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F1D2

D1

D3

D4

12Vac

RL12k!

(pk) (rms) ac

(pk) (pk)

(pk)(ave)

(ave)(ave)

2 2 12V 16.97V

1.4V 15.57V

2 2 15.57V 9.91V

9.91V 825.8µA12kΩ

S S

L S

LL

LL

L

V VV V

VV

VI

R

π π

= = × =

= − =

×= = =

= = =


Full-wave bridge rectifier• Determine the peak inverse voltage.

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F1D2

D1

D3

D4

12Vac

RL12k!

F1D2

D1

D3

D4 RL

VS

F1D2

D4 RL

VS VS

(pk)PIV SV≅


Center-Tap vs Bridge

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F1

Load

D2

D1

D3

D4

F1

Load

2 diodes(1 diode in the current path)

4 diodes(2 diodes in the current path)

Current passing through half of secondary winding at a time.

Current passing through full secondary winding all time.

VL(pk) 'VS(pk)

2VL(pk) ' VS(pk)

PIV ' VS(pk) ' 2VL(pk) PIV ' VS(pk) ' VL(pk)


Rectifier with a Filter Capacitor

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Half-waverectifier Filter

Vr

Vr = ripple voltage


Rectifier with a Filter Capacitor• Assume the diode to be ideal.• vI > 0: the diode conducts and the capacitor

is charged ⇒ vO = vI

• vI < VP: the diode becomes reverse biased⇒ vO = VP = const.

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• Practical situation: a load resistor R isconnected across the capacitor C.



• Diode-off interval:

• At the end of the discharge interval,the ripple voltage Vr:

• Conduction interval Δt:


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vO = VP e�t/CR

Vr ' VP � VP e�T/CR

' VPT

CR(since CR � T, e�T/CR ' 1� T/CR)

VP cos (!�t) = VP � Vr

cos (!�t) ' 1� 1

2(!�t)2

) !�t 'r

2Vr

VP


Ripple voltage vs Filter time constant

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C constant

R = 500Ω

R = 1kΩ

R = 1.5kΩ

R constant

C = 150mF

C = 300mF

C = 470mF


Clipper (limiter) circuits (Mạch xén)• For inputs in a range [L_/K, L+/K],

the limiter acts as a linear circuit ⇒ vO = KvI

• vI exceeds the thresholds, vO is limited to the upper/lower limiting levels.

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General transfer characteristic of a limiter circuit Applying a sine wave to a limiter


Clipper (limiter) circuits (Mạch xén)

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RS

D1 RL

IT

Vin(pk)in(pk)

L

L S

R VR R+

-0.7V

RS

D1 RLIF

Negative shunt clipper



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+0.7VRS

D1RLIF

( )in(pk)L

L S

R VR R

−+

RS

D1 RL

IT

-Vin(pk)

Positive shunt clipper



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VB

RS

RLVB + 0.7V

VB

RS

RL -VB - 0.7V

Biased shunt clipper


Clampers (DC restorers) (Mạch kẹp)

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Input signalsource

Positiveclamper Load

0V 0V20Vpp

20Vpp

Input signalsource

Negativeclamper Load

0V20Vpp 0V20Vpp


Clamper operation

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D1 RL5 V

On

VCVC5 V

D1 RL5 V

Off

+5 V

-5 V0 V

-10 V

0 V


Clamper circuits

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C1

D1 RL

C1

D1 RL

Negative clamper Positive clamper


Clamper circuits


Voltage multipliers• Half-wave voltage doubler:

34

VS

C1

D1

D2

C2 RL


Voltage multipliers

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VS(pk)C1 D1

D2

C2 RLOn

Off

IS IL

VS(pk)

VC2

VS(pk)C1 D1

D2

C2 RLIS

Off

OnVS(pk)

VC2

VC2=2VS(pk)


Zener diode

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IR VZ

ZZ

Ideal: ZZ = 0

Prac.: ZZ > 0

IZK=

IZT=

IZM=

Zener kneecurrent

Zener testcurrent

MaximumZener current

IR

VRVZ

IF

VF

RVSIR

IZK=

IZT=

IZM=

Zener kneecurrent

Zener testcurrent

MaximumZener current

IR

VRVZ

IF

VF

RVSIR


Zener diode• Ex: The zener diode has a constant reverse breakdown voltage VZ =

8.2V for 75mA ≤ iZ ≤ 1A. Find R so that VL = VZ is maintained at 8.2V while Vi varies by ±10% from its nominal value of 12V.

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Vi = 12V ± 10%

R

RL = 9ΩVL

IL =VL

RL=

VZ

RL=

8.2

9= 0.911A

IZ IL

R =Vi � VZ

IZ + IL(1)

Use (1) to find R for maximum zener current IZ at the largest value of Vi:

R =(1.1)(12)� 8.2

1 + 0.911= 2.62⌦

Check if IZ ≥ 75mA at the lowest value of Vi:

IZ =Vi � VZ

R� IL =

(0.9)(12)� 8.2

2.62� 0.911 = 81.3mA

Documents

AEA c4 diode circuit L4 - hcmut.edu.vntcdungnghi/AEA_PFIEV_S1_AY1213/AEA_c4_diode_circu…Full-wave rectifier (Chỉnh lưu toàn sóng) • The transformer secondary winding is center-tapped