Amplifier Design in ADS for Radar Applicationsread.pudn.com/downloads154/ebook/682565/功率放大器的设计.pdfFaint Solid = ADS Models Momentum Component. Aerospace and Defense

Presented by: HeeSoo LEE

Aerospace and Defense Symposium 2005Aerospace and Defense Symposium 2005

Amplifier Design in ADS for Radar Applications


Amplifier Design in ADSfor Radar Applications

Page 2

Objectives

• Overview of a systematic medium power amplifier design flow in ADS

• Overview of available tools and utilities in ADS for amplifier design

• Demonstrate ADS co-simulation capability • Demonstrate ADS layout for amplifier design



Page 3

Typical Block Diagram of a Radar System

Local Oscillator

TIMING SYNC

PulseGenerator

ToDisplay

LNA

PA

SYNCHRONOUSI/Q DETECTOR

RECEIVERPROTECTOR

Transmitter

Receiver

ADC and Signal

Processor



Page 4

Power Amplifier in Radar System

• In this presentation, design3 Watts medium output power two stage power amplifier20+dB gain at 1.95GHz frequencyOverall, good input and output matchTwo separate amplifiers without inter-stage matching

12 dB 8 dB14.8 dBm 26.8 dBm 34.8 dBm

NE6510179ANE651R479A



Page 5

Power Stage Amplifier

Deliver 3 Watts

12 dB 8 dB14.8 dBm 26.8 dBm 34.8 dBm

NE6510179ANE651R479A



Page 6

3 Watts HJ-FET NE6510179A

• NEC L&S band medium power HJ-FET• Good for power stage transistor because of

– Typical 35dBm output power @5V– Typical 10dB Gain at 1.9GHz

• Also ADS design kit is available with nonlinear models– http://www.cel.com/prod/prod_ads_update.asp

Source: NEC



Page 7

Graphical Method of Determining Ropt*

• Ropt, the load impedance at drain terminal that gives the maximum output power for devices* in Class A operation

• Easy to calculate• Reasonably accurate

• 2.67Ω Ropt with NE6510179A at 5V, 1.2A bias point

Ropt = (VBias-VKnee)2

2 x POut

* : Steve C. Cripps, RF Power Amplifier for Wireless communications Artech House Publishers

Vds

Ids

VKnee

Imax

VmaxVBias



Page 8

Modeling of FET Ground Pad Inductance

• Substrate on RT Duroid 5870, 31mil thick and ½ oz• Model ground pad in preparation for determining the

optimal load impedance from a load-pull simulation– Momentum EM Simulation to get S-parameters– Calculation of Leff from Z-parameters: 0.163nH at 2GHz

ADS Layout for ground

Recommended PCB Layout

Substrate

31 mil

AIR

GND

RT Duroid 5870

½ oz

Leff = Imaginary (Z11)

ω



Page 9

DesignGuides in ADS – Bridging the Gap

FilterBluetooth

Linearization

Mixer OscillatorPLL

RF SystemAmplifierPassive

DesignGuides

Simulation Technology

Applications

Linear, NonlinearCircuit EnvelopeTime DomainAgilent PtolemyElectromagneticOthers

Amplifier, FiltersMixers, OscillatorPassives, SystemMod/DemodsPackagingOthers



Page 10

What and Where to use DesignGuides

UWB



Page 11

Determine Optimum Load Impedance -Load-Pull*

Simply replace it with your own device!

Complex Load Impedance

• Use Amplifier DesignGuides Load-Pull– Pre-configured simulation setup– Pre-configured data post-processing

Ground pad is attached to the device!

1-Tone Nonlinear Simulations / Load-Pull – PAE, Output Power Contours

Menu

*Also available in load-pull application guides



Page 12

Load-Pull Simulation Result

• Simulation maps complex load impedances to power and PAE contours

• Pre-configured data display for gain compression, PAE, harmonics and more

• Load reflection coefficient that gives maximum power is at 0.924/-169.396

Load impedances is mapped to Power and PAE contours36dBm

35.5dBm



Page 13

A: 2.67 Ω B: 2.0 + j4.65 Ω

Comparison of Graphical and Load-Pull Methods• Graphical Method

DC only calculation

2.67 Ω• Load-Pull Method

Complete non-linear AC/RF simulationΓRopt = 0.924/-169.396

ZRopt = 2.0 + j*4.65 Ω• Reasonable agreement but slightly different due to

– Where to look into the impedance• Graphical method, at A plane: Drain terminal of intrinsic transistor• Load-Pull method, at B plane: Drain terminal of extrinsic or packaged

transistor– Package parasitic



Page 14

Determine Optimum Source Impedance –Linear method

• No information on output power but small signal gain

• Choice 1 : Conjugate match– Good for maximum gain– Good for Input match– Output match is question

• Choice 2: Mismatched input for optimum output match– Better output match with a little

loss of gain– As an example, 0.936/-156.351

gives 1.4dB mismatch loss but better match for output

Mapped input gain circle for transistor’s output impedance

Optimum transistor output match for maximum power

Max Gain = 9.978dB at 1.95GHz



Page 15

Determine Optimum Source Impedance –Source-Pull

• Use Amplifier DesignGuides Source-Pull– Pre-configured simulation setup– Pre-configured data post-processing – Brute-force solution for finding optimum source impedance– Full understanding on output power with varying source

impedance

0.778/-159.090

1-Tone Nonlinear Simulations / Source-Pull – PAE, Output Power Contours

Menu



Page 16

Stability

• NE6510179A is stable at 1.95GHz design frequency with the addition of pad ground inductance

• Mu factor is over 1

Input Stability Circle

Output Stability Circle



Page 17

Matching Network Design

? ?



Page 18

Smith Chart Utility

• User interactive matching network design• View frequency response• View matching network topology• Define Q of the circuit• Build ADS schematic• Easy to use

Source and Load TerminationsSeries ComponentsShunt ComponentsTransmission Line and Transformers



Page 19

Matching Utility

• Available network topologies– Lowpass– Highpass– Bandpass

• Source/Load impedance can be defined over wide frequency range

• Matching element transformation utility



Page 20

Output Matching Network Design

• Design with Smith Chart Utility

• Design for reflection coefficient from load-pull, ΓRopt 0.924/-169.396

• Ideal lumped passive and transmission line elements

ΓRopt 0.924/-169.396

Display of Smith Chart Utility

Enter conjugate of ΓRoptfor load termination5.6 pF

59.85 deg

50 Ohm

0.627 pF Reflection Trajectory

Q circle



Page 21

Input Matching Network Design

• Design with Smith Chart Utility

• Design for reflection coefficient from source-pull, ΓIN opt 0.778/-159.090

• Ideal lumped passive and transmission line elements

ΓIN opt 0.778/-159.090

Input Match

3.3 pF

46 deg

50 Ohm

1.37 pF

Conjugate of ΓINoptfor load termination



Page 22

Impedance Loci with Different Width and Length of Transmission Line

• Discrete SMT capacitance value limits flexibility of design

• Parameter sweep simulation capability allows designers to understand– Impedance loci of network

with varying physical dimension

• Consider bandwidth of network with each combination

Output matching with different capacitance Blue: 0.5pF, Red: 1.0pF

Output matching

Input matching



Page 23

Realization of Input and Output Networks

• Replace ideal capacitors with discrete vendor SMT capacitors • SMT capacitors from Taiyo-Yuden • ADS model library is available (Download from Web)

– http://66.40.41.39//simtools/index.cfm

1.2pF 1 pF

Physical Realization

5.6 pF

59.85 deg

50 Ohm

0.627 pF

3.3 pF

46 deg

50 Ohm

1.37 pF



Page 24

Linear Simulation With ADS Models

• Transmission lines in input and output matching networks were chosen to be close to 50 Ω lines

• 7.81 dB small signal gain at 1.95GHz• Excellent match for input and reasonable match for output



Page 25

Non-Linear Simulation with ADS Models

• Use Amplifier DesignGuides’ pre-configured power simulation setup

• Gain compression at 37.07dBm • 38.24% PAE• 7.81 dB small signal gain

1-Tone Nonlinear Simulations / Spectrum,Gain,Harmonic Distortion vs Power (w/PAE)

Menu



Page 26

Linear Simulation with Momentum Component

• Layout look alike Momentum Component for physical layout– Nested EM simulation for physical layout– Accurate simulation for layout parasitics– Overcome limitation of valid model range for circuit models

• Frequency response is shifted

Shifted

Comparison with ADS model simulation

Solid = Layout Simulation

Faint Solid = ADS Models

Momentum Component



Page 27

Detuned Matching Network

• Input and output impedances are detuned from desired impedances due to physical layout parasitics

• Very convenient SProbe simulation component

0.778/-159.090

ΓIN optΓRopt

0.924/-169.396

Sprobe Component



Page 28

Advanced Model Composer (AMC)

W12

W3

freq

W12

W3

freq

W12

W3

freq

W12

W3

freq

W12

W3

freq

W12

W3

ADS Model Composer builds parameterized models for passive componentscontinuous frequency range & discrete and/or continuously varying layout parameters

component : tee_s : symmetrical teemodel is function of :

substratefrequency rangelayout parameters W12 & W3

continuous frequencydiscrete W12 discrete W3

continuous frequencydiscrete W12 continuous W3

continuous frequencycontinuous W12 continuous W3

single frequencysingle W12, W3

continuous frequencysingle W12, W3

Momentum calculates S-data•



Page 29

AMC Model for In/Output Matching Network

• Two perturbed parameters – Line width and length

• Once the model is developed, AMC provides very fast simulation speed without a loss of accuracy

Line Width

Line Length

Parameter Sweep Simulation with AMC Input Matching Network Model

Parameter Sweep Simulation with AMC Output

Matching Network Model



Page 30

Tuned Matching Network

• Input and output matching networks are tuned for desired impedances

• Linear and Non-linear simulations are performed– Swept input power –20 to 30dBm

Gain Compression 36dBm, 4W



Page 31

Bias Circuit Design

• Transistor Bias Utility for biasing circuit for transistors– Unregulated bias network for BJT and FET– OPAMP based active biasing network up to 4 devices– OPAMP based regulated biasing network up to 4 devices

• LineCalc Utility for synthesizing transmission lines

31 mil RT Duroid 5870

50 Ohm - 91 mil

Resistive bias networkOpamp based active biasOpamp based regulated bias



Page 32

Linear Simulation with Bias Lines

• Bias lines for source and drain terminals are attached• 8.179dB small signal gain at 1.95GHz• Very good input and output return loss

Due to λ /4 lines



Page 33

Final Non-Linear Simulation

• 8.179dB gain at small signal• 35.48dBm 1dB gain compression• 35% PAE at 35.5dBm Pout



Page 34

Driver Stage Amplifier

Deliver 480 mW

12 dB 8 dB14.8 dBm 26.8 dBm 34.8 dBm

NE6510179ANE651R479A



Page 35

1 Watt HJ-FET NE651R479A

• NEC L&S band medium power HJ-FET• Good for driver stage transistor because of

– Typical 29.5dBm output power– Typical 12dB Gain at 1.95GHz

• ADS design kit is available with nonlinear models– http://www.cel.com/prod/prod_ads_update.asp

Source: NEC



Page 36

Load and Source Matching Network

• HJ-FET NE651R479A is biased at 5V, 250mA• Optimum source and load impedances were

extracted from Load-Pull and Source-Pull Simulation

ΓIN opt 0.846/-153.444 ΓRopt 0.707/-169.644



Page 37

Linear Performance of Driver Amplifier

• 13.1dB small signal gain at 1.95GHz• Good input and output return loss characteristic

Due to λ /4 bias lines



Page 38

Non-Linear Performance

• 1dB gain compression at 30.57dBm• 41% PAE at 30.56dBm Pout

• 13.1 dB small signal gain



Page 39

Final Integration and Layout

Deliver 3 Watts

12 dB 8 dB14.8 dBm 26.8 dBm 34.8 dBm

NE6510179ANE651R479A



Page 40

Linear Performance of Two Stage Amplifier

• Total 21.37dB small signal gain• Good match for input and reasonable match for output• Hierarchical design is employed with a sub-network



Page 41

Non-Linear Power Simulation Setup

• Use Amplifier DesignGuides’ pre-configured power simulation setup

• Hierarchical design is employed with a sub-network



Page 42

Non-Linear Performance (1)

Gain Compression at 35.33 dBm

Pre-configured data presentation from Amplifier DesignGuides



Page 43

Non-Linear Performance (2) - PAEPre-configured data presentation

from Amplifier DesignGuides• Overall 39.55% PAE



Page 44

Non-Linear Performance (3) - AM-to-PMPre-configured data presentation

from Amplifier DesignGuides



Page 45

ADS Layout for Two Stage Amplifier



Page 46

Co-Simulation of Power Amplifier in Radar System



Page 47

Power of Co-Simulation in ADS

Top Level Radar System Using ADS Ptolemy

Concept – Block Diagram

Transmitter System Using ADS Circuit Envelope

Power Amp Circuit Using ADS EM-Circuit Co-simulation

Baseband Float/Fixed PointHDL(Verilog & VHDL), MatLab®C++.System-C

Behavior RF/Analog Subsystem, Circuit, Transistor Level Models

Physical, EM Models, Circuit Models

Connected Solution



Page 48

Transmitter Response with 2-Stage Power AMP

• 70 dB System Gain• Double Conversion• Simulated with Circuit Envelope



Page 49

Top Level Radar System Performance with 2-Stage Power AMP

Top Level Radar System Design Using ADS Ptolemy

Target Distance & RCS



Page 50

Co-Simulation ResultLFM Chirp Source Spectrum

Transmitter Output Spectrum

Output to Dynamic VSA Software

Click the graph to animate in slide show mode…



Page 51

Summary

• ADS provides an integrated and seamless design environment for designing medium power amplifier

• ADS DesignGuides and Application Guides bridge the gap between complex simulation technologies and advanced applications

• ADS Momentum and Momentum Component provide both accuracy and convenience for taking into account physical layout parasitics

• ADS Co-Simulation capability allows “single click” simulation for multiple simulation technologies and various abstract level models

Documents

Amplifier Design in ADS for Radar Applicationsread.pudn.com/downloads154/ebook/682565/功率放大器的设计.pdfFaint Solid = ADS Models Momentum Component. Aerospace and Defense