An Oscillator Design Based on MOS-NDR Inverter...vol 41, pp. 148-153, 1994 8. Tomoyuki Akeyoshi, Koichi Maezawa, and Takashi Mizutani, “Weighted sum threshold logic operation of

An Oscillator Design Based on MOS-NDR Inverter

Cher-Shiung Tsai1 Chung-Chih Hsiao Kwang-Jow Gan Jia-Ming Wu Ming-Yi Hsieh Chun-Chieh Liao Shih-Yu Wang Feng-Chang Chiang Chia-Hung Chen Dong-Shong Liang Yaw-Hwang Chen

Department of Electronic Engineering Kun Shan University of Technology Tainan Taiwan 710 ROC

e50401mailksutedutw

Abstract-- First we create a MOS-NDR (negative

differential resistance) cell and then put two MOS-NDR

cells in cascode (totem-pole) structure With MOBILE

(monostable-bistable transition logic element) theorem

we can built a MOS-NDR inverter by placing a NMOS

in parallel with the lower part of the cascode structure

The MOS-NDR inverter cascades two Common-Source

amplifier and feedback to MOS-NDR inverter The

circuit will start an oscillation Such a phenomenon

is similar to ring oscillator The frequency of the

MOS-NDR oscillator will be 116 MHz when voltage is

27 volts Those MOS-NDR devices are adapted from

CIC standard 035um CMOS process

Keywords monostable-bistable transition logic element

(MOBILE) negative differential resistance (NDR)

common-source Amplifier ring oscillator

1 Introduction

There are many kinds of oscillators but we

seldom see an oscillator built by MOS-NDR [1-3]

devices In this thesis we propose a MOS-NDR

Inverter [4-5] by MOBILE [6-8] Theorem Just like

ring oscillator [9] theorem the MOS-NDR inverter

can also implement an oscillator The MOS-NDR

oscillator can reach 100 MHz easily and has low

noise character

The MOS-NDR oscillator can change output

frequency by adjusting MOS sizes or resistance

values Under different voltage the oscillation

frequency will increase as supply voltage increases It

shows the MOS-NDR oscillator is a voltage control

oscillator (VCO) The MOS-NDR oscillator supplies

flexibility and easiness in design

2 MOS-NDR Device

In the beginning we present a MOS- NDR

device which is composed of one PMOS transistor

and three NMOS transistors as shown in Fig 1 This

MOS-NDR device can exhibit various negative

differential resistance (NDR) current-voltage

characteristics by choosing appropriate values for the

transistors parameters

Fig 1 Configuration of MOS-NDR device circuit

In this circuit transistor mn2 acts like a variable

resistor When supply voltage Vdd equals to zero mn2

is off and mn3 is on While supply voltage Vdd

increases transistor mn2 is on and voltage Vc will

decrease to make transistor mn3 turn off Because

transistor mn3 is large size when supply voltage Vdd

increases but total current Idd decreases It creates a

NDR phenomenon Fig 2 shows the I-V

characteristics of the MOS-NDR device by H-spice

simulation

Fig 2 The simulated I-V curve of Fig 1

3 MOS-NDR Inverter

In this work we demonstrate an inverter gate

design that is based on the monostable-bistable

transition logic element (MOBILE) theory A

MOBILE cell is consisted of two NDR devices in

cascade structure as shown in Fig 3 During a period

when the input signal rises the voltage at the output

node between the two NDR devices goes to one of

the two stable states (low and high corresponding to

ldquo0rdquo and ldquo1rdquo in binary logic) depending on which

NDR devices is reached the second positive

differential resistance (PDR) region first The

controlled process obeys a rule the MOS-NDR

device with the smaller peak current is always

reached the second PDR region first Based on the

MOBILE theory and control rule the measured result

of inverter logic is implemented

In Fig 3 when input (Vin) is in high state then

NMOS is on The summation of driver current and

NMOS current is larger than load current the

operating point will be located at point Stable1 and

output state is in low state as Fig 4 shows

Fig 3 Configuration of an inverter by MOS-NDR

circuit

Vin=High Vout=Low Fig 4 When IDriver+VingtILoad operating point at

stable1 and output is in low State

On the contrary in Fig 3 when input (Vin) is in

low state then NMOS is off The driver current is

smaller than load current the operating point will be

located at point Stable2 and output state is in high

state as Fig 5 shows Such an operation just likes an

inverter

Vin=Low Vout=High

stable2 Fig 5 When IDriver ltILoad operating point at stable2

and output is in high state

VS V

I Load Driver

Out(H)

V

I

VS

Driver + VinLoad

Out(L)

stable1

4 MOS-NDR Oscillator

Fig 6 shows the oscillator circuit of MOS-NDR

devices The 1st stage is NDR inverter and 2nd stage

is voltage amplifier which consisted by two common

source amplifiers After MOS-NDR inverter the

output signal could be reduced it needs voltage

amplification The signal of feedback must be the

same as original input signal it needs two

common-source amplifier because common-source

amplifier has high voltage gain and phase change of

180 degrees The theorem of an oscillator is the

feedback signal must be the same as the past original

input signal but out of phase with 180 degrees The

total change of the MOS-NDR oscillator is 540

degrees (= 180 degrees) it satisfies the oscillation

phase The voltage amplifier (2nd stage) also supplies

a time delay to decide the oscillation frequency Such

a phenomenon is similar to ring oscillator All devices

in Fig6 are from CIC standard 035um CMOS

process except resistor R1 and R2 Resistors R1 and

R2 are external devices We put these elements on

bread board to establish the MOS-NDR oscillator and

measure it

Fig 6 Configuration of the MOS-NDR oscillator

circuit

5 Experimental Results In this thesis we use Tektronix TDS3034B

oscilloscope to measure MOS-NDR inverter circuit

and oscillator circuit Fig 7 shows the input (upper)

and output (lower) signals in MOS-NDR inverter

circuit of Fig 3

Fig 7 Input signal (upper) and output signal (lower)

reveal inverter operation

It is an inverter operation the input is 2 Vp-p and

output is 05Vp-p The MOS-NDR inverter is the same

as CMOS inverter except output voltage is not full

swing

Fig 8 shows the MOS-NDR oscillator output

waveform output signal is 14Vp-p and frequency is

1116 MHz as supply voltage is 27 Volts R1 and R2

of the MOS-NDR oscillator (Fig 6) are small

resistance resistors which below 10 Ohms

Fig8 Output waveform of MOS-NDR

oscillator under 27 volts supply voltage

Fig 9 shows MOS-NDR oscillator frequencies

NDR1

NDR2

Vs

(Load)

(Driver)

OUT

mn1

R1 R2

mn2

NMOS

Vin

under different supply voltages The oscillation

frequency increases as supply voltage increases It

shows that the MOS-NDR oscillator is a voltage

control oscillator (VCO) with good linearity The

start oscillation voltage of the MOS-NDR oscillator

is 21 Volts

Fig 9 Oscillator output frequency under different

supply voltage

We also use Tektronix TDS3034B oscilloscope

to measure FFT (fast Fourier transform) response of

Fig 8 In Fig 10 the MOS-NDR oscillator shows

FFT diagram with pretty good low-noise

characteristics

In Fig 10 because the difference between the

highest peak and 2nd highest peak is about 28 dB it

means that the main frequency signal is twenty-five

(102820 =2512) times stronger than the other

frequencies signals If the output signal 15 Vp-p then

the other frequencies signals must be smaller than

006 (=152512) Vp-p

But the differences between the highest peak

and most other peaks is more than 40 dB in Fig 10

so most frequencies signals must be smaller than

0015 Vp-p (1510(4020) = 0015) We can see that

most signals are low-noise except oscillation

frequency signal

Fig 10 Configuration of FFT corresponding to Fig 8

6 Conclusions

In this work we present a MOS-NDR cell which

consisted of three NMOS transistors and one PMOS

transistor We use the cell combined with a large size

NMOS transistor to build an MOS-NDR inverter by

MOBILE (monostable-bistable transition logic

element) theorem then we use the dominant

MOS-NDR inverter and two common-source

amplifiers to establish MOS-NDR oscillator

Such an oscillator shows pretty good response in

frequency domain and low-noise characteristics Itrsquos

also a good voltage control oscillator (VCO) The

MOS-NDR oscillator has both easiness and flexibility

in design items

Acknowledgements

The authors would like to thank the Chip

Implementation Center (CIC) for their great effort

and assistance in arranging the fabrication of this

work This work was supported by the National

Science Council of Republic of China under the

contract no NSC93-2218-E-168-002

References

1 L O Chua J B Yu and Y Y Yu ldquoNegative resistance

devicesrdquo Int j Cir Appl vol 11 pp 161-186 1983

2 S Sen F Capasso A Y Cho and D Sivco rdquoResonant

tunneling device with multiple negative differential

resistance digital and signal processing applications

with reduced circuit complexityrdquo IEEE Trans

Electron Devices vol 34 pp 2185-2191 1987

3 C S Tsai S B Kuo K J Gan Y H Chen C C Hsu

K R Lee and D S Liang ldquoDesign and Fabrication

of Prototype MOS-NDR Devices by CMOS

Technologyrdquo 2003 EDMS pp 235-238

4 K J Chen T Waho K Maezawa and M Yamamoto

ldquoAn exclusive-OR logic circuit based on controlled

quenching of series-connected negative differential

resistance devicesrdquo IEEE Electron Device Lett vol

17 pp 309-311 1996

5 Cher-Shiung Tsai and Shin-Bin Kuo

ldquoInvestigation of Inverter Design by MOS-NDR

Devives and MOBILE Theoryrdquo 2003 International

Conference on Informatics Cybernetic and Systems

義守大學 pp 296-300

6 K Maezawa H Matsuzaki M Yamamoto

and T Otsuji ldquoHigh-Speed and low-power operation

of a resonant tunneling logic gate MOBILErdquo IEEE

Electron Device Lett vol 19 pp 80-821998

7 K Maezawa T Akeyoshi and T Mizutani

ldquoFunctions and applications of monostable-bistable

transition logic elements (MOBILESrsquos) having

multi-input terminalsrdquo IEEE Trans Electron Devices

vol 41 pp 148-153 1994

8 Tomoyuki Akeyoshi Koichi Maezawa and Takashi

Mizutani ldquoWeighted sum threshold logic operation of

MOBILES (monostable-bistable transition logic

elements) using resonant tunneling transistorsrdquo IEEE

Electron Device Lett vol 14 pp475-477 Dec 1979

9 Adel S Sedra and Kenneth C Smith

ldquoMicroelectronic Circuitsrdquo 5th edition pp 1027

2004

Implementation of R-BJT-NDR Devices and Inverter Circuit by BiCMOS Technology

Dong-Shong Liang Kwang-Jow Gan Chung-Chih Hsiao Cher-Shiung Tsai

Yaw-Hwang Chen Shun-Huo Kuo and Hsin-Da Tesng

Department of Electronic Engineering Kun Shan University of Technology Tainan Hsien Taiwan ROC

E-mail Addresssulnmailksutedutw

ABSTRACT

The negative differential resistance (NDR) device studied in this work is composed of the resistors (R) and bipolar junction transistors (BJT) devices This NDR device can be represented as R-BJT-NDR device Comparing to the conventional NDR devices such as resonant tunneling diodes (RTDrsquos) the RTDrsquos are often implemented by the technique of III-V compound semiconductor The fabrication cost of these RTDrsquos is more expensive than that of Si-based technique However our R-BJT-NDR devices and circuits are composed of the resistors and BJT devices Therefore we can fabricate the R-BJT-NDR devices by the standard CMOS or BiCMOS process Furthermore the modulation of the current-voltage (I-V) characteristics of this R-BJT-NDR device is easier than that of the RTD device We can obtain different NDR I-V characteristics by simply adjusting the proper values of resistors Finally we demonstrate an inverter circuit design based on the R-BJT-NDR devices and circuits that are implemented by the standard 035μm BiCMOS process

Keywords negative differential resistance (NDR) device resonant tunneling diodes (RTD) inverter circuit 035μm BiCMOS process

1 INTRODUCTION Functional devices and circuits based on

negative differential resistance (NDR) devices have generated substantial research interest owing to their unique NDR characteristics [1]-[3] The best famous known NDR device is the resonant tunneling diodes (RTD) [4-5] The fabrications of these NDR devices are often based on the technique of compound semiconductor Comparing to silicon-based integrated circuit the cost of compound semiconductor is more expensive However we proposed a NDR device that is composed of the resistors (R) and bipolar junction transistors (BTJ) devices We call this device as R-BJT-NDR device Because this device is totally composed of the R and BTJ devices it is suitable for the process of Si-based CMOS or BiCMOS process

In this paper we investigate the current-voltage (I-V) characteristics by modulating the parameters of the R-BJT-NDR device The fabrication of the device is utilized by 035μm BiCMOS process Furthermore we will demonstrate an inverter design based on the R-BJT-NDR device under 3V bias

2 CIRCUIT ANALYSIS

Figure 1 shows this R-BJT-NDR device

composed of two n-p-n transistors and five resistors During suitably arranging the values of the five resistors we can obtain the I-V curve with NDR characteristics Figure 2 shows the simulated I-V characteristics by Hspice program The electrical parameters are R1=45kΩ R2=53kΩ R3=100kΩ R4=12

kΩ and R5=6kΩ The I-V characteristics can be divided into four regions The first segment (I) of the I-V characteristics represents a situation when Q1 and Q2 are cut off the second segment (II) indicates the case when Q1 is cut off but Q2 is conducted the third segment (III) refers to the state when both Q1 and Q2 are conducted and the forth segment (IV) corresponds to the state when Q1 is saturated but Q2 is cut off

VS

R1

R2

R3

R4

R5Q1

Q2

Fig 1 The NDR device is composed of two transistors and five resistances

Fig 2 The simulated I-V characteristics by Hspice program

The I-V characteristics of this R-BJT-

NDR device can be modulated by the relative values of the resistors Figures 3 and 4 are the simulated I-V characteristics by varying the values of the resistors R1 and R2 respectively By keeping the other parameters at some fixed values the peak currents and voltages will be increased by increasing the values of the resistor R1 However the peak currents and voltages will be decreased by increasing the

values of the resistor R2 Based on the circuit analysis the peak voltage is approximated to the value of (1+R1R2)xVr1 The parameter Vr1 is the cut-in voltage of the transistor Q1 Therefore this R-BJT- NDR device possesses the ability of the adjustable I-V characteristics during suitably designing the resistance

Fig 3 The simulated I-V characteristics by modulating the values of R1 resistor


3 MESURED RESULTS

The fabrication of this R-BJT-NDR device is designed based on the standard 035μm SiGe process Figure 5 shows the layout of the R-BJT-NDR device Figure 6 shows the measured I-V characteristics using the Tektronix 370B Programmable curve tracer The parameters are designed as R1＝55kΩ R2=33kΩ R3=100kΩ R4=12kΩ and R5=55kΩ The peak current and voltage are about 11mA and 18V respectively The valley

current and voltage are about 06mA and 25V respectively Figures 7 and 8 show the measured I-V characteristics by varying the values of R1 and R2 respectively

Fig 5 The layout of the R-BJT-NDR device

0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

Fig 6 The measured I-V characteristics of the R-BJT-NDR device

0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K

Fig 7 The measured I-V characteristics of the R-BJT-NDR device by varying the R1 values

0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K


Based on the measured results this R-BJT-NDR device could exhibit the NDR characteristics by suitably controlling the parameters The tendency of the measured I-V characteristics is satisfactory by comparing to the simulated results

4 INVERTER DESIGN

Figure 9 shows the inverter circuit with a NDR device in series with a NMOS device The input voltage is the gate voltage of the NMOS device

Fig 9 The inverter circuit design based on this R-BJT-NDR device and a NMOS

The operating principle of the static inverter can be explained by the load-line method as shown in Fig 10 When two devices are connected in series the upper R-BJT-NDR device is treated as a load device to the pull-down NMOS device The operation point (Q) at any bias (VS) can be obtained by the stable intersection point of the two I-V characteristics The voltage value of the operation point Q is the output voltage of the circuit In Fig 9 the load-line curve is the I-V characteristics of the R-BJT-NDR device The driver curve is the I-V characteristics of the NMOS When the input voltage is at low level (0V) the gate voltage of the NMOS is lower than the VT so the NMOS will be located at OFF state The operating point will be located at the intersection point (Q) of two I-V characteristics of the load and driver devices The output voltage will be approximately the same value as the voltage VS The output state is at the high level

Fig 10 The load-line analysis of the inverter circuit

However when the input voltage is at high level (3V) the NMOS will turn on The operating point will be located at the intersection point (Q) of two I-V characteristics As seen the output state is at the low level The key point on designing this inverter circuit is the I-V characteristics of the NMOS device at the high state should be higher than the peak current of the R-BJT-NDR device

The result of the operation of the inverter circuit is shown in Fig 11 The supply voltage VS is chosen at 3V As seen when the input voltage has reached the low state (0V) the output voltage is at the high state (3V) When the input voltage has reached the high state (3V) the output voltage is at the low state (02V) Therefore this circuit can be operated as an inverter

Fig 11 The results of the inverter circuit

5 CONCLUSIONS

We have demonstrated the design and fabrication of the R-BJT-NDR device and inverter circuit based on the standard 035μm BiCMOS process The modulation of the I-V characteristics of this R-BJT-NDR device is easier than that of the RTD device We can obtain different NDR I-V characteristics by simply adjusting the proper values of resistors

This R-BJT-NDR device is more convenient to integrate with other active MOS and BJT devices and passive R L and C devices These phenomena might provide the practical application in some NDR-based

circuits It means that the R-BJT-NDR device might have the potential to achieve the design of system-on-a-chip (SOC)

ACKNOWLEDGMENTS

The authors would like to thank the Chip Implementation Center (CIC) for their great effort and assistance in arranging the fabrication of this chip This work was supported by the National Science Council of Republic of China under the contract no NSC93-2215-E-168-002

REFERENCES

[1] S Sen F Capasso A Y Cho and D SivcoldquoResonant tunneling device with multiple negative differential resistance digital and signal processing applications with reduced circuit complexityIEEE Trans Electron Devices vol 34 pp 2185-2191 1987

[2] K J Chen K Maezawa and M Yamamoto ldquoInP-based high-performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devicesrdquo IEEE Electron Device Lett vol 17 pp 127-129 1996

[3] Z X Yan and M J Deen rdquoA new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion loadrdquo IEEE J Solid-State Circuits vol 27 pp 1198-1202 1992

[4] K Maezawa H Matsuzaki M Yamamoto and T Otsuji ldquoHigh-speed and low-power operation of a resonant tunneling logic gate MOBILErdquo IEEE Electron Device Lett vol 19 pp 80ndash82 Mar 1998

[5] J P A van der Wagt H Tang T P E Broekaert A C Seabaugh and Y C Kao rdquoMultibit resonant tunneling diode SRAM cell based on slew-rate addressingrdquo IEEE Trans Electron Devices vol 46 pp 55-62 1999

High-Frequency Voltage-Controlled Oscillator Design by MOS-MDR Devices and Circuits

Kwang-Jow Gan Dong-Shong Liang Shih-Yu Wang Chung-Chih Hsiao

Cher-Shiung Tsai Yaw-Hwang Chen and Feng-Chang Chiang

Department of Electronic Engineering Kun Shan University of Technology

This paper describes the design of a novel voltage-controlled oscillator (VCO) based on the new-type MOS-NDR devices and circuits The MOS-NDR device is composed of three N-type metal-oxide-semiconductor field-effect-transistor (MOS) devices that can exhibit the negative differential resistance (NDR) characteristics in its current-voltage (I-V) curve by suitably arranging the parameters The length of three MOS devices is fixed at 035μm The width is designed as 1μm 10μm and 40μm respectively The I-V curve of the MOS-NDR device can exhibit a Λ-type characteristic When we connect a NMOS device with a MOS-NDR device in parallel the total current is the sum of the currents through the NMOS and MOS-NDR devices Therefore we can modulate the total current by the gate voltage of the NMOS Firstly we design a low-power inverter by combining two series-connecting MOS-NDR devices according to the monostable-bistable transition logic element (MOBILE) theory Secondly we design an oscillator by cascading this MOS-NDR inverter with the other two common-source amplifiers as shown in Fig 1 The signal will be feedback from the output of the second common-source amplifier to the input of the MOS-NDR inverter Under suitable design we can obtain an oscillator with its frequency proportional to the magnitude of input bias Vds1 or Vds2 This new VCO has a wide range of operation frequency from 065MHz to 155GHz It consumes 7mW in its central frequency of 12GHz using a 24V power supply The fabrication of this VCO is based on the standard 035μm CMOS process and occupied an area of 128 x 45 μm2

Fig 1 The circuit configuration of a novel voltage-controlled oscillator (VCO)

MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2

Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process

Kwang-Jow Gan Dong-Shong Liang Chung-Chih Hsiao Shih-Yu Wang Feng-Chang Chiang

Cher-Shiung Tsai Yaw-Hwang Chen Shun-Huo Kuo and Chi-Pin Chen

Department of Electronic Engineering Kun Shan University of Technology Taiwan ROC

Abstract--We propose a new MOS-NDR device that is composed of the metal-oxide-semiconductor field-effect- transistor (MOS) devices This device could exhibit the negative differential resistance (NDR) characteristics in the current-voltage characteristics by suitably modulating the MOS parameters We design a logic circuit which can operate the inverter NOR and NAND gates The devices and circuits are fabricated by the standard 035μm CMOS process

1 INTRODUCTION

Functional devices and circuits based on negative differential resistance (NDR) devices have generated substantial research interest owing to their unique NDR characteristic [1]-[2] Taking advantage of the NDR feature circuit complexity can be greatly reduced and novel circuit applications have also obtained

Some applications make use of the monostable- bistable transition logic element (MOBILE) as a highly functional logic gate [3]-[4] A MOBILE consists of two NDR devices connected in series and is driven by a suitable bias voltage The voltage at the output node between the two NDR devices could hold on one of the two possible stable states (low and high corresponding to ldquo0rdquo and ldquo1rdquo) depending on the relative difference of peak current (IP) between two devices

We propose a MOS-NDR device that is composed of the metal-oxide-semiconductor field-effect-transistor (MOS) devices Then we design a logic circuit that can operate the inverter NOR and NAND function in the same circuit It is different from the CMOS logic family constructed by NMOS and PMOS devices Finally we fabricate the MOS-NDR devices and logic circuits by standard 035μm CMOS process

2 DEVICE STRUCTURE AND OPERATION

Figure 1 shows a MOS-NDR device which is composed of three NMOS devices and one PMOS device This circuit is derived from a Λ-type topology described in [5]-[6] This MOS-NDR device can exhibit various NDR current-voltage (I-V) characteristics by choosing appropriate MOS parameters Figure 2 shows the simulation results by HSPICE program

If the Vgg voltage is fixed at some value the operation of this MOS-NDR device can be divided into four situations by gradually increasing the bias Vdd The first situation mn1 is saturation mn2 is cutoff mn3 is linear and mp4 is cutoff The second situation mn1 is saturation mn2 is saturation mn3 is from linear to saturation and mp4

is cutoff The third situation mn1 is saturation mn2 is saturation mn3 is saturation and mp4 is cutoff Finally the fourth situation mn1 is saturation mn2 is linear mn3 is cutoff and mp4 is linear until saturation Fig 1 The circuit configuration for a MOS-NDR device

Fig2 Simulation result for the MOS-NDR device by HSPICE program

The value of Vgg voltage will affect the I-V curve especially in its peak current Figure 3 shows the I-V characteristics measured by Tektronix 370B with the Vgg voltage varied from 15V to 33V gradually The width parameters are designed as mn1=5μm mn2=100μm mn3=10μm and mp4=100μm The length parameters are all fixed at 035μm The I-V characteristic could be divided into three segments as the first PDR segment the NDR segment and the second PDR segment in sequence

mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR

Fig 3 The measured I-V characteristics for a MOS-NDR devices with different Vgg voltages

3 LOGIC CIRCUIT DESIGN

Our logic circuit design is based on the MOBILE theory A MOBILE circuit consists of two NDR devices connected in series and is driven by a bias voltage VS The logic circuit configuration is shown in Fig 4 T1 is used as the controlled gate T2 and T3 are the input gates with square wave signal The width parameters are all 5μm The upper NDR1 device is treated as a load device to the pull-down NDR2 driver device When the bias voltage is smaller than twice the peak voltage (2VP) there is one stable point (monostable) in the series circuit However when the bias voltage is larger than two peak voltages but smaller than two valley voltages (2VV) there is two possible stable points (bistable) that respect the low and high states (corresponding to ldquo0rdquo and ldquo1rdquo) respectively A small difference between the peak currents of the series-connected NDR devices determines the state of the circuit

Fig 4 Configuration of the logic circuit

The circuit shown at upper left corner of Fig 4 is a

MOS-NDR device with parallel connection of a T1 NMOS The total current ITotal is the sum of the currents through the MOS-NDR and NMOS devices ITotal=INDR+IMOS Since IMOS is modulated by the gate voltage (T1) so is ITotal

Figure 5 shows the measure I-V characteristics of a MOS-NDR device with T1 varying from 0 to 33V gradually As seen we can modulate the peak current of the MOS-NDR device through T1 gate

0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)

T1 varied from 0Vto 33V

0V1V15V2V

25V3V

33V

Fig 5 Measured I-V characteristics with different T1 voltages

If the IP of the driver is smaller than IP of the load (with T2 or T3 OFF) the circuit switches to the stable point Q corresponding to a high output voltage as shown in Fig 6 The operation point Q is located at the second PDR region of the driverrsquos I-V curve On the other hand a bigger peak current (with T2 or T3 ON) of the driver will result in the stable point Q with low output voltage At this time the operation point Q is located at the second PDR region of the loadrsquos I-V curve Therefore an inverter operation can be obtained at the output node between the two NDR devices Similarly if we design the logic function according to the MOBILE theory and truth table we can obtain the NOR and NAND gate logic operation Fig 6 The MOBILE operation is dependent on the relative difference in the peak current of load and driver devices

4 EXPERIMENT RESULTS

The MOS-NDR devices and logic circuits are fabricated by the standard 035μm CMOS process The length parameters for all MOS are fixed at 035μm The width parameters of the two MOS-NDR devices are designed as mn1=5μm mn2=100μm mn3=10μm and mp4=100μm The width parameters for T1 T2 and T3 are fixed at 5μm

For the inverter operation T2 gate is chosen as the input square wave with signal varied from 0 to 2V The supply voltage VS is fixed at 15V that is bigger than 2VP

T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I

but is small than 2VV voltage The operation of T1 control gate is cutoff The Vgg voltages are 33V and 28V for NDR1 and NDR2 respectively The inverter operation is shown in Fig 7 As seen when the input voltage has reached the low state (0V) the output voltage will be at the high state On the other hand when the input voltage has reached the high state (2V) the output voltage must be at the low state

Fig 7 The measured results for the logic circuit

For the NOR gate operation T2 and T3 gates both are the input square wave with signal varied from 0 to 2V The period of T2 is two times of the period of T3 signal The controlling gate T1 is fixed at 12V According to the truth table when the input T2 and T3 gates are located at low level the peak current of ITotal of NDR2 device must be smaller than the peak current of ITotal of NDR1 device Then the stable operating point will be located at the relative ldquohighrdquo level at the output node If one (or both) of the input T2 and T3 is (are) located at high voltage level the peak current of ITotal of NDR2 device must be bigger than the peak current of ITotal of NDR1 devices The stable operating point will be located at the relative ldquolowrdquo level at this case Therefore we design the Vgg voltages with 33V and 25V for NDR1 and NDR2 respectively

As for the operation of a NAND gate when the input T2 and T3 gates both are located at high level the peak current of ITotal of NDR2 device must be bigger than the peak current of ITotal of NDR1 device The stable operating point will be located at the relative ldquolowrdquo level On the other hand the peak current of ITotal of NDR2 device must be smaller than the peak current of ITotal of NDR1 device for the other cases The stable operating point will be located at the relative ldquohighrdquo level Therefore the control gate T1 is designed fixed at 33V The Vgg voltages are fixed at 33V and 25V for NDR1 and NDR2 respectively

The parameters are designed and shown in Table I The operation results for this logic circuit are shown in Fig 7 respectively As seen we can obtain the inverter NOR and NAND gate operation at the same circuit only by modulating the relative parameters

Table I The parameters condition for the logic circuit

Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V

T2 INPUT INPUT INPUT

T3 OFF INPUT INPUT

NDR1 Vgg 33V 33V 33V


5 CONCLUSIONS

We have demonstrated the logic circuit design based on the MOS-NDR devices and circuits This circuit design is operated according to the principle of MOBILE theory Our MOS-NDR devices and circuits are fabricated by the technique of Si-based CMOS technique The fabrication cost will be cheaper than that of resonant tunneling diodes (RTD) implemented by the technique of compound semiconductor Furthermore our NDR devices are composed of the MOS devices so these NDR devices are easy to combine with other devices and circuit to achieve the system-on-a-chip (SoC) If the integrated circuit is fabricated with transistor dimensions less than 01μm technique the applications based on the MOS-NDR devices and circuits are still useful Therefore the MOS-NDR devices and circuit have high potential in the SoC applications

ACKNOWLEDGMENTS

The authors would like to thank the Chip Implementation Center (CIC) of Taiwan for their great effort and assistance in arranging the fabrication of this chip This work was supported by the National Science Council of Republic of China under the contract no NSC93-2218- E-168-002

REFERENCES


[2] T H Kuo H C Lin R C Potter and D ShupeldquoA novel AD converter using resonant tunneling

diodesIEEE J Solid-State Circuits vol 26 pp 145-149 1991

[3] K Maezawa H Matsuzaki M Yamamoto and T Otsuji ldquoHigh-speed and low-power operation of a resonant tunneling logic gate MOBILErdquo IEEE Electron Device Lett vol 19 pp 80-82 1998


[5] C Y Wu and K N Lai ldquoIntegrated Λ -type differential negative resistance MOSFET devicerdquo IEEE J Solid-State Circuits vol 14 pp 1094-1101 1979

[6] A F Gonzalez and P Mazumder ldquoMultiple-valued signed-digit adder using negative differential- resistance devicesrdquo IEEE Trans Comput vol 47 pp 947-959 1998

Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits

Dong-Shong Liang Kwang-Jow Gan Chung-Chih Hsiao Cher-Shiung Tsai Yaw-Hwang Chen

Shih-Yu Wang Shun-Huo Kuo Feng-Chang Chiang and Long-Xian Su


Abstract--This paper describes the design of a

voltage-controlled oscillator (VCO) based on the negative differential resistance (NDR) devices The NDR devices used in the work is fully composed by the metal-oxide- semiconductor field-effect-transistor (MOS) devices This MOS-NDR device can exhibit the NDR characteristic in its current-voltage curve by suitably arranging MOS parameters The VCO is constructed by three low-power MOS-NDR inverter This novel VCO has a range of operation frequency from 151MHz to 268MHz It consumes 245mW in its central frequency of 260MHz using a 2V power supply This VCO is fabricated by 035μm CMOS process and occupied an area of 120 x 86 μm2

I Introduction

In recent years several new applications based on resonant tunneling diode (RTD) have been reported [1]-[4] The negative-differential-resistance (NDR) current-voltage (I-V) characteristics of the RTD devices have several advantages and they may have high potential as functional devices due to their unique folding I-V characteristics However these RTD devices are fabricated by the compound semiconductor and process Therefore this kind of NDR device is difficult to combine with other devices and circuits to achieve the system-on-a-chip (SoC)

Therefore we proposed a new MOS-NDR device that is fully composed of metal-oxide-semiconductor field-effect-transistor (MOS) devices During suitably arranging the MOS parameters we can obtain the NDR characteristic in its I-V curve We call this NDR device as MOS-NDR device Because this NDR device is consisted of the MOS devices yet it is much more convenient to combine other devices and circuits to achieve the SoC by standard CMOS process

We will demonstrate a novel voltage-controlled oscillator (VCO) designed based on the MOS-NDR devices and circuit The VCO is constructed by three cascading low-power MOS-NDR inverters The basic inverter is composed by two series-connected MOS-NDR devices according to the monostable-bistable transition logic element (MOBILE) The signal will be feedback from the output of the third MOS-NDR inverter to the input of the first MOS-NDR inverter Under suitable design we can obtain an oscillator with its frequency proportional to the magnitude of input bias We design and implement this VCO by the 035μm CMOS process

II MOS-NDR Device and Inverter DESIGN

Figure 1 shows a MOS-NDR device which is

composed of three NMOS transistors This circuit can show the Λ-type NDR I-V characteristic by suitably arranging the MOS parameters Figure 2 shows the I-V curve measured by Tektronix-370B curve trace with the width parameters of the three MOS devices as 1μm 10μm and 40μm respectively The MOS length is fixed at 035μm The VGG is fixed at 33V

Fig 1 The circuit configuration of a Λ-type MOS-NDR device

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)

W1=1uW2=10uW3=40u VGG=33V

(1) (2) (3) (4)

Fig 2 The measured I-V characteristic for a MOS-NDR device

If we connect a NMOS with a MOS-NDR device in

parallel we can modulate the peak current of MOS-NDR devicersquos I-V curve through the gate voltage of NMOS The circuit is shown in Fig 3 The total current ITotal is the sum of the currents through the MOS-NDR and NMOS devices ITotal=INDR+IMOS Since IMOS is modulated by the gate

voltage (VG) so is ITotal Our inverter circuit design is based on two series-connected MOS-NDR devices as shown in Fig 4 This circuit is called as monostable-bistable transition logic element (MOBILE) [5]-[6] The input node is located at the VG gate The output node is located between the two MOS-NDR devices When the bias voltage is smaller than twice the peak voltage (2VP) there is one stable point (monostable) in the series circuit

However when the bias voltage is larger than two peak voltages but smaller than two valley voltages (2VV) there will be two possible stable points (bistable) The intersection point located at the NDR region for two I-V curve will be regarded as unstable point The two stable points that respect the low and high states (corresponding to ldquo0rdquo and ldquo1rdquo) respectively are shown in Fig 5 A small difference between the peak currents of the two devices determines the state of the circuit If the peak current of the driver device is smaller than that of the load device the operation point will be located at the high state On the other hand if the peak current of the driver device is bigger than that of the load device through the VG voltage the operation point will be located at the low state

Fig 3 The peak current of MOS-NDR device can be controlled by the VG voltage

Fig 4 The MOS-NDR inverter designed by MOBILE theory

Fig 5 The bistable states when VS is bigger than2VP but smaller than 2VV

By suitably determining the parameters of devices and circuits we can obtain the inverter result as shown in Fig 6 Figure 7 illustrates the relationship between the input bias VS and the power dissipation for a MOS-NDR inverter The power dissipation of this inverter is 575mW using a 2V power supply

Fig 6 The MOS-NDR inverter result

16 2 24Input Bias (V)

0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)

Fig 7 The power dissipation for a MOS-NDR inverter

III VCO DESIGN

The circuit configuration of the novel VCO is shown in Fig 8 The oscillator circuit is composed of three cascading MOS-NDR inverters The signal will be feedback from the output of the third MOS-NDR inverter to the input of the first MOS-NDR inverter This VCO is designed and fabricated by the standard 035μm CMOS process and occupied an area of 120 x 86 μm2 Figure 9 shows the layout of VCO

Fig 8 The circuit configuration of the VCO

Fig 9 The layout of VCO

IV SIMULATION RESULTS

Under suitable parameters design we can obtain an oscillator with its frequency proportional to the magnitude of input bias VS Figure 10 shows the simulated waveform of the oscillator under 2V bias voltage by HSPICE program Figure 11 shows its spectrum

Figure 12 illustrates the relationship between the input bias and the oscillation frequency This VCO has a range of operation frequency from 151MHz to 268MHz The relationship between the power dissipation and input bias is shown in Fig 13 It consumes 245mW in its central frequency of 260MHz using a 2V power supply

Fig 10 The simulated waveform of the oscillator



120

160

200

240

280

Freq

uenc

y (M

Hz)

Fig 12 The relationship between the input bias and the oscillation frequency


0

10

20

30

40

Pow

er D

issi

patio

n (m

W)

Fig 13 The power dissipation for a VCO

V Conclusions We have designed a voltage-controlled oscillator

(VCO) based on the Λ-type MOS-NDR devices and circuits The VCO is composed of three cascading low-power MOS-NDR inverters For chip area die consideration we use fully MOS devices instead of LC-tank structure The oscillation frequency is from 151MHz to 268MHz This VCO is designed by the standard 035μm CMOS process If we fabricated this VCO by 018μm CMOS process the oscillation frequency will be increased above GHz

ACKNOWLEDGMENTS


REFERENCES

[7] S Sen F Capasso A Y Cho and D SivcoldquoResonant tunneling device with multiple negative differential resistance digital and signal processing applications with reduced circuit complexityIEEE

Trans Electron Devices vol 34 pp 2185-2191 1987 [8] T H Kuo H C Lin R C Potter and D ShupeldquoA

novel AD converter using resonant tunneling diodesIEEE J Solid-State Circuits vol 26 pp 145-149 1991

[9] LO Chua ldquoSimplicial RTD-Based Cellular Nonlinear Networksldquo IEEE Trans on Cir and Sys-I Fundamental Theo and Appl vol50 no4 April 2003

[10] Y Kawano Y Ohno S Kishimoto K Maezawa T Mizutani and K Sano ldquo88 GHz dynamic 21 frequency divider using resonant tunnelling chaos circuitrdquo Electron Lett vol 39 no 21 pp 1546-48 2003



Design and Fabrication of Voltage-Controlled Oscillator by Novel MOS-NDR Device

Kwang-Jow Gan Chung-Chih Hsiao Shih-Yu Wang Feng-Chang Chiang Cher-Shiung Tsai Yaw-Hwang Chen Dong-Shong Liang Chun-Da Tu Wei-Lun Sun Chia-Hung Chen

Chun-Ming Wen Chun-Chieh Liao Jia-Ming Wu and Ming-Yi Hsieh

Department of Electronic Engineering Kun Shan University Tainan County 710 Taiwan

Abstract mdash This paper describes the design of a

voltage-controlled oscillator (VCO) using the novel MOS-NDR devices The VCO circuit is constructed by cascading a MOS-NDR inverter with the other two common-source amplifiers This novel VCO has a range of operation frequency from 119MHz to 188MHz under the bias voltage from 18V to 28V The fabrication of this VCO is based on the standard 035μm CMOS process and occupied an area of 003mm2

Index Terms mdash voltage-controlled oscillator MOS- NDR inverter 035μm CMOS process

I INTRODUCTION

Negative differential resistance (NDR) devices have attracted considerable attention in recent years because of their potential as functional devices for circuit applications [1]-[3] Taking full advantages of NDR we can reduce circuit complexity to enhance circuit performance in terms of operation speed chip area and power consumption However these NDR devices such as resonant tunneling diodes (RTD) are fabricated by the III-V compound semiconductor Therefore this kind of NDR device is difficult to combine with other devices and circuits to achieve the system-on-a-chip (SoC)

In this paper we proposed a MOS-NDR device that is made of metal-oxide-semiconductor field- effect-transistor (MOS) devices During suitably controlling the MOS parameters we can obtain the NDR characteristic in its I-V curve Because this NDR device is consisted of the MOS devices it is much more convenient to combine other devices and circuits to achieve the SoC by standard Si-based CMOS or BiCMOS process

The voltage-controlled oscillator (VCO) is one of the important components in the phase-locked loop We will demonstrate a VCO circuit based on the MOS-NDR devices and circuits This oscillator is composed of an NDR-based inverter two common source amplifiers and a CMOS inverter This novel

VCO has a range of operation frequency from 119MHz to 188MHz under the bias voltage from 18V to 28V The fabrication of this VCO is based on the standard 035μm CMOS process and occupied an area of 003mm2

II MOS-NDR INVERTER

Our logic circuit design is based on the Monostable-Bistable transition Logic Element (MOBILE) theory [4]-[5] A MOBILE circuit consists of two MOS-NDR devices connected in series and is driven by a bias voltage VS as shown in Fig 1 The MOS-NDR device used in this work that is made of three NMOS and an external bias VGG It can present a λ-type I-V curve with suitable control the width of each MOS device [6] The value of Vgg voltage will affect the peak current of the I-V curve of the MOS-NDR device

Fig 1 Inverter circuit configuration for a MOBILE MOS-NDR device

Figure 2 shows the I-V curve with the VGG voltage varying from 15V to 33V by a step of 03V The width parameters of the three MOS devices are designed as 1μm 10μm and 40μm respectively The MOS lengths are all fixed at 035μm The MOS-NDR2 device is connected with a NMOS in

parallel The total current ITotal is the sum of the currents through the NMOS and MOS-NDR2 That is ITotal= IMOS+IMOS-NDR2 Since IMOS is modulated by the Vin voltage so is ITotal Therefore we can modulate the peak current of this combined circuit through the magnitude of the Vin as shown in Fig 3 The Vin voltages are varied from 1V to 22V with a step 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)

W1=1uW2=10uW3=40uVGG=15V~33V Step=03V

VGG=15V

VGG=33V

Fig 2 The measured results for the MOS-NDR device by modulating the VGG voltage

Fig 3 Modulation of peak current by Vin voltage

The upper MOS-NDR1 device is treated as a load device to the pull-down MOS-NDR2 driver device When the bias voltage is smaller than twice the peak voltage (2VP) there is one stable point (monostable) in the series circuit However when the bias voltage is bigger than 2VP but is smaller than 2VV there is two possible stable points (bistable) that respect the low and high states (corresponding to ldquo0rdquo and ldquo1rdquo) respectively A small difference between the peak currents of the series-connected NDR devices determines the state of the circuit The selection of the stable operating point could be explained by means of the load-line method as shown in Fig 4

If the peak current of the driver is smaller than the peak current of the load the circuit switches to the stable point Q corresponding to a high output voltage as shown in Fig 4 As shown the operation point Q is located at the positive differential resistance (PDR) region of the loadrsquos I-V curve In order to obtain a small peak current in MOS-NDR2 device we can adjust the value of the Vgg voltage to be smaller than that of MOS-NDR1 device On the other hand a bigger peak current in the driver will result in the stable point Q with low output voltage At this time the operation point Q is located at the PDR region of the driverrsquos I-V curve Thus the state of the circuit is determined by the magnitude of the peak current of the MOS-NDR2 driver device that can be controlled by the Vin voltage Therefore an inverter operation can be obtained at the output node between the two MOS-NDR devices By suitably determining the parameters of devices and circuits we can obtain one of the inverter logic results as shown in Fig 5

Fig 4 MOBILE operation of an inverter circuit

Fig 5 Measured result for an inverter circuit

III VCO Design

The CMOS LC-tank oscillators have shown an excellent phase noise performance with low power consumption However the large chip area of the inductor L has become critical drawback in LC VCOs On the other hand the ring VCOs have the advantages such as the ease of integration with CMOS technique and the smaller chip area The

oscillation frequency of the ring oscillator is inversely proportional to the number of delay stages N Employing fewer delay stages can also reduce the power dissipation and chip area The oscillator circuit is composed of a NDR inverter two common source amplifier and a CMOS inverter as shown in Fig 6

Fig 6 The circuit configuration of a novel VCO

The VCO signal will be feedback from the output of the second common source amplifier to the input of the MOS-NDR inverter The output of every circuit is affected by the previous one and then the last circuit output goes back to affect the first MOS-NDR inverter There has been transmission delay between every circuit so that it makes circuit produce oscillation The novel VCO is fabricated using 035μm CMOS technology as shown in Fig 7 The layout of this VCO is occupied an area of 003 mm2

Fig 7 Layout and PAD of the VCO chip

Figure 8 shows the output waveform with 156MHz oscillation frequency under 23V bias voltage Under suitable design we can obtain an oscillator with its frequency proportional to the magnitude of input bias Figure 9 shows the relationship between the input bias and the oscillation frequency This novel VCO has a range of operation frequency from 119MHz to 188MHz under the bias voltage from 18V to 28V

Fig 8 The 156MHz oscillation frequency under 23V bias voltage

16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)

Fig 9 Oscillation frequencies of the VCO

IV CONCLUSIONS

We have designed a voltage-controlled-oscillator (VCO) based on the Λ-type NDR-based devices and circuits The NDR devices are all made of the MOS devices Therefore we can fabricate the VCO circuit based on the standard 035μm CMOS process In comparison with the LC-tank VCO structure this novel MOS-NDR VCO will occupy less chip area This novel VCO has a range of operation frequency from 119MHz to 188MHz under the bias voltage from 18V to 28V

Furthermore even if the integrated circuit is fabricated with transistor dimensions less than 035μm technique the applications based on the MOS-NDR devices and circuits are still useful Therefore it can provide some useful applications in the NDR-based circuit and system design

ACKNOWLEDGMENTS

The authors would like to thank the Chip Implementation Center (CIC) for their great effort

and assistance in arranging the fabrication of this chip This work was supported by the National Science Council of Republic of China under the contract no NSC94-2815-C-168-005-E

REFERENCES

[1] F Capasso S Sen A C Gossard A L Hutchinson and J H English ldquoQuantum-well resonant tunneling bipolar transistor operating at room temperaturerdquo IEEE Electron Device Lett vol EDL-7 pp 573-576 1986

[2] H Matsuzaki T Itoh and M Yamamoto ldquoA Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTsrdquo Proc IEEE 9th Great Lakes Sympo on VLSI Michigan 1999 pp154-157

[3] H L Chan S Mohan P Mazumder and G I Haddad Compact Multiple Valued Multiplexers Using Negative Differential Resistance Devices IEEE J Solid-state Circuits vol 31 pp 1151-1156 1996

[4] K Maezawa and T Mizutani ldquoA new resonant tunneling logic gate employing monostable-bistable transitionrdquo Japan J ApplPhys vol 32 pt 2 no 1AB p L42 Jan 15 1993


[6] C Y Wu and K N Lai ldquoIntegrated λ-type differential negative resistance MOSFET devicerdquo IEEE J Solid-State Circuits vol 14 pp 1094-1101 1979

Investigation of MOS-NDR Voltage Controlled Ring

Oscillator Fabricated by CMOS Process

Kwang-Jow Gan Dong-Shong Liang Chung-Chih Hsiao Cher-Shiung Tsai and Yaw-Hwang Chen

Abstract- A voltage-controlled ring oscillator

(VCO) based on novel MOS-NDR circuit is described This MOS-NDR circuit is made of metal-oxide- semiconductor field-effect-transistor (MOS) devices that can exhibit the negative differential resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters The VCO is constructed by three low-power MOS-NDR inverters This novel VCO has a range of operation frequency from 38MHz to 162MHz It consumes 24mW in its central frequency of 118MHz using a 2V power supply This VCO is fabricated by 035μm CMOS process and occupy an area of 0015 mm2

I Introduction In recent years several new applications based on

resonant tunneling diode (RTD) have been reported [1]-[3] The negative-differential-resistance (NDR) current-voltage (I-V) characteristics of the RTD devices have several advantages and they may have high potential as functional devices due to their unique folding I-V characteristics However these RTD devices are fabricated by the III-V compound material and process Therefore this kind of NDR device is difficult to combine with other devices and circuits to achieve the system-on-a-chip (SoC)

Therefore we proposed a new NDR device that is totally composed of metal-oxide-semiconductor field-effect-transistor (MOS) devices We can obtain the NDR characteristic in its I-V curve by suitably arranging the MOS parameters We call the NDR device to be as MOS-NDR device in this work Because this NDR device is consisted of the MOS devices yet it is much more convenient to combine other devices and circuits to achieve the SoC by standard CMOS process

Our novel voltage-controlled ring oscillator (VCO) is constructed by three low-power MOS-NDR inverters The MOS-NDR inverter logic gate can be obtained by connecting two MOS-NDR devices in series according to the Monostable-Bistable transition Logic Element (MOBILE) theory [4]-[5] The signal will be feedback from the output of the third MOS-NDR inverter to the input of the first MOS-NDR inverter Under suitable design we can obtain an oscillator with its frequency proportional to the magnitude of input bias We demonstrate this VCO based on the standard 035μm CMOS process

II MOS-NDR DEVICE AND INVERTER

Our logic circuit design is based on the MOBILE theory A MOBILE circuit consists of two MOS-NDR devices connected in series and is driven by a bias voltage VS as shown in Fig 1 The MOS-NDR device used in this work that is made of three NMOS and an external bias VGG It can present a λ-type I-V curve with suitable control the width of each MOS device [6] The value of Vgg voltage will affect the peak current of the I-V curve of the MOS-NDR device


0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V


Figure 2 shows the I-V curve with the VGG voltage varying from 15V to 33V by a step of 03V The width parameters of the three MOS devices are designed as 1μm 10μm and 40μm respectively The MOS lengths

Kwang-Jow Gan Dong-Shong Liang Chung-Chih HsiaoCher-Shiung Tsai and Yaw-Hwang Chen are with the Department of Electronic Engineering the Kun Shan University Taiwan

E-mail sulnmailksutedutw

are all fixed at 035μm The MOS-NDR2 device is connected with a NMOS in parallel The total current Itotal is the sum of the currents through the NMOS and MOS-NDR2 That is Itotal= IMOS+IMOS-NDR2 Since IMOS is modulated by the Vin voltage so is ITotal Therefore we can modulate the peak current of this combined circuit through the magnitude of the Vin as shown in Fig 3 The Vin voltages are varied from 1V to 22V with a step 03V






III VCO DESIGN The CMOS LC-tank oscillators have shown an

excellent phase noise performance with low power consumption However the large chip area of the inductor L has become critical drawback in LC VCOs On the other hand the ring VCOs have the advantages such as the ease of integration with CMOS technique and the smaller chip area The oscillation frequency of the ring oscillator is inversely proportional to the number of delay stages N Employing fewer delay stages can also reduce the power dissipation and chip area

The circuit configuration of the novel VCO is shown in Fig 6 The oscillator circuit is composed of three low-power MOS-NDR inverters Every MOS-NDR inverter is regarded as a delay stage With the 2V supply voltage the current consumption is about 12mA The signal will be feedback from the output of the third MOS-NDR inverter to the input of the first MOS-NDR inverter The output of every circuit is affected by the previous one and then the last circuit output goes back to affect the first MOS-NDR inverter There has been transmission delay between every circuit so that it makes circuit produce oscillation The novel VCO is fabricated using 035μm CMOS technology as shown in Fig 7 The layout of this VCO is occupied an area of 0015 mm2

Fig 6 Circuit configuration of the ring VCO


16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)

Fig 8 The relationship between the oscillation frequency

and the bias VS

Figure 8 shows the measured results for the ring VCO circuit If we changed the value of VS voltage we can find that the oscillation frequency is proportional to the magnitude of input bias If we modulate the VS

voltage from 16V from 24V step 02V the oscillator frequency is increased from 38GHz to 162MHz

IV CONCLUSIONS We have designed a voltage-controlled-oscillator

(VCO) based on the Λ-type NDR-based devices and circuits The VCO is composed of three cascading low-power MOS-NDR inverters The NDR devices are all made of the MOS devices Therefore we can fabricate the VCO circuit based on the standard 035μm CMOS process In comparison with the LC-tank VCO structure this novel MOS-NDR VCO will occupy less chip area This novel VCO has a range of operation frequency from 38MHz to 162MHz It consumes 24mW in its central frequency of 118MHz using a 2V power supply

Furthermore even if the integrated circuit is fabricated with transistor dimensions less than 035μm technique the applications based on the MOS-NDR devices and circuits are still useful We can predict the oscillation frequency will be capable for GHz operation by the Hspice simulated results from the 018μm CMOS process Therefore it can provide some useful applications in the NDR-based circuit and system design

ACKNOWLEDGMENTS The authors would like to thank the Chip

Implementation Center (CIC) for their great effort and assistance in arranging the fabrication of this chip This work was supported by the National Science Council of Republic of China under the contract no NSC94-2215-E-168-001

REFERENCES F Capasso S Sen A C Gossard A L

Hutchinson and J H English ldquoQuantum-well resonant tunneling bipolar transistor operating at room temperaturerdquo IEEE Electron Device Lett vol EDL-7 pp 573-576 1986

H Matsuzaki T Itoh and M Yamamoto ldquoA Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTsrdquo Proc IEEE 9th Great Lakes Sympo on VLSI Michigan 1999 pp154-157

H L Chan S Mohan P Mazumder and G I Haddad Compact Multiple Valued Multiplexers Using Negative Differential Resistance Devices IEEE J Solid-state Circuits vol 31 pp 1151-1156 1996

K Maezawa and T Mizutani ldquoA new resonant tunneling logic gate employing monostable-bistable transitionrdquo Japan J ApplPhys vol 32 pt 2 no 1AB p L42 Jan 15 1993

K J Chen K Maezawa and M Yamamoto ldquoInP-based high-performance monostable-bistable transition logic elements (MOBILEs) using integrated multiple-input resonant-tunneling devicesrdquo IEEE Electron Device Lett vol 17 pp 127-129 1996

C Y Wu and K N Lai ldquoIntegrated λ-type differential negative resistance MOSFET devicerdquo IEEE J Solid-State Circuits vol 14 pp 1094-1101 1979

A NAND Gate Design Based on MOS-NDR Devices and Circuits Implemented by CMOS Technology

Kwang-Jow Gan Chi-Pin Chen Long-Xian Su To-Kai Liang Cher-Shiung Tsai Yaw-Hwang Chen Chung-Chih

Hsiao Shih-Yu Wang and Feng-Chang Chiang


Abstract

A NAND logic circuit design based on the

MOS-NDR devices is demonstrated The MOS-NDR

device is consisted of the metal-oxide-semiconductor

field-effect-transistor (MOS) devices This device could

exhibit the negative differential resistance (NDR)

characteristics in the current-voltage curve by suitably

arranging the parameters of the MOS devices As a result

we design a NAND logic operation based on MOS-NDR

devices and circuits which is implemented by the

standard CMOS process

Keywords NAND logic circuit negative differential

resistance (NDR) characteristics 35μm CMOS process

I Introduction Functional devices and circuits based on negative

differential resistance (NDR) devices have generated

substantial research interest owing to their unique NDR

characteristic [1]-[2] Taking advantage of the NDR

feature circuit complexity can be greatly reduced and

novel circuit applications have also obtained

Some applications make use of the monostable-

bistable transition logic element (MOBILE) as a highly

functional logic gate [3]-[4] A MOBILE consists of two

NDR devices connected in series and is driven by a

suitable bias voltage The voltage at the output node

between the two NDR devices could hold on one of the

two possible stable states (low and high corresponding

to ldquo0rdquo and ldquo1rdquo) depending on the relative difference of

peak current between two devices

In this paper we propose a MOS-NDR device that is

composed of the metal-oxide-semiconductor field-

effect-transistor (MOS) devices Then we design a logic

circuit that can operate the NAND function We fabricate

the circuit by standard CMOS process

II The MOS-NDR Devices Figure 1 shows a MOS-NDR device which is

composed of three NMOS devices and one PMOS device

This circuit is derived from a Λ-type topology described

in [5]-[6] This MOS-NDR device can exhibit various

NDR current-voltage (I-V) characteristics by choosing

appropriate parameters for transistors

Fig 1 The circuit configuration for a MOS-NDR device

The value of Vgg voltage will affect the I-V curve

especially in its peak current Figure 2 shows the I-V

characteristics measured by Tektronix 370B with the

Vgg voltage varied from 15V to 33V gradually The

width parameters of the gate of the MOS devices are

described as mn1=5μm mn2=100μm mn3=10μm and

mp4=100μm The length parameters of four MOS are all

fixed at 035μm The I-V characteristics could be divided

into three segments as the first PDR segment the NDR

segment and the second PDR segment in sequence

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR

Fig 2 The measured I-V characteristics for a MOS-NDR devices with

different Vgg voltages

III Logic Circuit Design

Our logic circuit design is based on the MOBILE

theory A MOBILE circuit consists of two NDR devices

connected in series and is driven by a bias voltage VS

Figure 3 shows the logic circuit configuration T1 is the

control gate T2 and T3 are the input square wave signal

The width parameters are all 5μm The upper NDR1

device is treated as a load device to the pull-down NDR2

driver device When the bias voltage is smaller than

twice the peak voltage (2VP) there is one stable point

(monostable) in the series circuit However when the bias

voltage is larger than two peak voltages but smaller than

two valley voltages (2VV) there is two possible stable

points (bistable) that respect the low and high states

(corresponding to ldquo0rdquo and ldquo1rdquo) respectively A small

difference between the peak currents of the

series-connected NDR devices determines the state of the

circuit


MOS-NDR device with parallel connection of a T1

NMOS The total current ITotal is the sum of the currents

through the MOS-NDR and NMOS devices

ITotal=INDR+IMOS Since IMOS is modulated by the gate

voltage (T1) so is ITotal Figure 4 shows the measure I-V

characteristics of a MOS-NDR device with T1 varying

from 0 to 33V gradually As seen we can modulate the

peak current of the MOS-NDR device through T1 gate

Fig 3 The logic circuit configuration

0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V

Fig 4 The measured I-V characteristics with different T1

voltages

If the IP of the driver is smaller than IP of the load

(with T2 or T3 OFF) the circuit switches to the stable

point Q corresponding to a high output voltage as shown

in Fig 5 The operation point Q is located at the second

PDR region of the driverrsquos I-V curve On the other hand

a bigger peak current (with T2 or T3 ON) of the driver

will result in the stable point Q with low output voltage

At this time the operation point Q is located at the

second PDR region of the loadrsquos I-V curve Therefore an

inverter operation can be obtained at the output node

between the two NDR devices Similarly if we design

the logic function according to the MOBILE theory and

truth table we can obtain the NAND gate logic

operation

Fig 5 The MOBILE operation is dependent on the

relative difference of peak current

IV Experiment Results

The MOS-NDR devices and logic circuits are

fabricated based on the standard 035μm CMOS process

The length parameters for all MOS are fixed at 035μm

The supply voltage VS is fixed at 15V

For the NAND gate operation T2 and T3 gates both

are the input square wave The period of T2 is two times

of the period of T3 signal The control T1 gates is 33V

The Vgg voltages are 33V and 25V for NDR1 and

NDR2 respectively We design the logic circuit based on

the truth table and MOBILE theory The selection of the

operation point is dependent on the relative difference of

peak current between two devices Figure 6 shows the

measured result for the NAND logic circuit


V Conclusions We have demonstrated the NAND logic circuit

design based on the MOS-NDR devices and circuits

This circuit design is operated according to the principle

of MOBILE theory Our NDR devices and circuits can

be fabricated by the technique of Si-based CMOS

technique The fabrication cost will be cheaper than that

of resonant tunneling diodes (RTD) implemented by the

technique of compound semiconductor

Acknowledgement The authors would like to thank the Chip

Implementation Center (CIC) for their great effort and

assistance in arranging the fabrication of this chip This

work was supported by the National Science Council of

Republic of China under the contract no

NSC93-2218-E-168-002

References 1 S Sen F Capasso A Y Cho and D Sivco

ldquo Resonant tunneling device with multiple

negative differential resistance digital and signal

processing applications with reduced circuit complexityIEEE Trans Electron Devices vol

34 pp 2185-2191 1987

2 T H Kuo H C Lin R C Potter and D Shupe ldquoA novel AD converter using resonant tunneling

diodesIEEE J Solid-State Circuits vol 26 pp

145-149 1991

3 K Maezawa H Matsuzaki M Yamamoto and T

Otsuji ldquoHigh-speed and low-power operation of a

resonant tunneling logic gate MOBILErdquo IEEE

Electron Device Lett vol 19 pp 80-82 1998

4 K J Chen K Maezawa and M Yamamoto

ldquoInP-based high-performance monostable-bistable

transition logic elements (MOBILEs) using

integrated multiple-input resonant-tunneling

devicesrdquo IEEE Electron Device Lett vol 17 pp

127-129 1996

5 C Y Wu and K N Lai ldquoIntegrated Λ -type

differential negative resistance MOSFET devicerdquo

IEEE J Solid-State Circuits vol 14 pp

1094-1101 1979

6 A F Gonzalez and P Mazumder ldquoMultiple-valued

signed-digit adder using negative

differential-resistance devicesrdquo IEEE Trans

Comput vol 47 pp 947-959 1998

Oscillator Design by MOS-NDR Devices and Circuits

To-Kai Liang Kwang-Jow Gan Cher-Shiung Tsai Shih-Yu Wang Chung-Chih Hsiao Feng-Chang Chiang Yaw-Hwang Chen Chi-Pin Chen and Long-Xian Su


Abstract

The oscillator design based on the negative

differential resistance (NDR) devices and circuits is

demonstrated The NDR device is composed of

metal-oxide-semiconductor field-effect-transistor (MOS)

devices An inverter logic gate can be obtained by

connecting two MOS-NDR devices in series according to

the monostable-bistable transition logic element

(MOBILE) theory As a result we will demonstrate an

oscillator circuit with frequency 100MHz

Keywords MOS-NDR device MOBILE oscillator

circuit




characteristics [1]-[3] The best famous known NDR

devices are Esaki diodes and resonant tunneling diodes

(RTD) The fabrications of these NDR devices are based

on the technique of compound semiconductor

Comparing to Silicon-based integrated circuit the cost of

compound semiconductor is more expensive However

we proposed a new NDR device that is composed of


devices We call this device to be as MOS-NDR device

Because this device is totally composed of MOS devices it is suitable for the process of Si-based CMOS process

First we demonstrate an inverter circuit based on

the MOS-NDR device Then we design an oscillator

circuit composed of a NDR inverter a common source

amplifier and a CMOS inverter The measured results

show the oscillator frequency is about 100MHz

II The MOS-NDR Devices Figure 1 shows a prototype MOS-NDR device

which is composed of three NMOS transistors and one

PMOS transistor This circuit is derived from a Λ-type

topology described in [4] The gate of mn3 is connected

to the output of the inverter formed by mn1 and mn2 It

can exhibit various NDR current-voltage characteristics

by choosing appropriate values for transistors


The operation of this MOS-NDR device can be

divided into four situations by gradually increasing the

bias Vdd The first situation represents a condition when

mn1 is saturated mn2 is cutoff mn3 is linear and mp4 is

cutoff The second situation indicates the case when mn1

is saturated mn2 is saturation mn3 is from linear to

saturated and mp4 is cutoff The third situation refers to

the state when mn1 is saturated mn2 is saturated mn3 is

saturated and mp4 is cutoff Finally the fourth situation

corresponds to the state when mn1 is saturated mn2 is

mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG

linear mn3 is cutoff and mp4 is saturated Therefore we

can obtain various NDR I-V characteristics by choosing

appropriate values for MOS parameters

Figure 2 shows the measured I-V characteristics by

modulating the width of mn1 The other width

parameters of the gate of the MOS devices are described

as mn2=100μm mn3=10μm and mp4=100μm The

length parameters of four MOS are all fixed at 035μm

The Vgg voltage is fixed at 33V

0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1

Fig 2 The measured I-V characteristics for a MOS-NDR

devices by modulating the width of mn1

Fig 3 The peak current of MOS-NDR device could be

controlled by the VG voltage

Figure 3 shows the circuit with the parallel

connection of a NMOS and a MOS-NDR device The

total current ITotal is the sum of the currents through the

MOS-NDR and NMOS devices ITotal=INDR+IMOS

Since IMOS is modulated by the gate voltage (VG) so is

ITotal

III Inverter Circuit Design

Our inverter circuit design is based on the MOBILE



Figure 4 shows the configuration of a MOBILE circuit

The VG gate is used as the input signal gate The upper

NDR1 device is treated as a load device to the pull-down

NDR2 driver device When the bias voltage is smaller

than twice the peak voltage (2VP) there is one stable

point (monostable) in the series circuit However when

the bias voltage is bigger than 2VP but is smaller than

2VV there is two possible stable points (bistable) that

respect the low and high states (corresponding to ldquo0rdquo and

ldquo1rdquo) respectively A small difference between the peak

currents of the series-connected NDR devices determines

the state of the circuit

Fig 4 The circuit configuration of an inverter

If the peak current of the driver is smaller than the

peak current of the load the circuit switches to the stable



PDR region of the driverrsquos I-V curve In order to obtain a

small peak current in NDR2 device we can adjust the

value of the Vgg voltage to be smaller than that of NDR1

device On the other hand a bigger peak current in the

driver will result in the stable point Q with low output

voltage At this time the operation point Q is located at

the second PDR region of the loadrsquos I-V curve Thus the

state of the circuit is determined by the magnitude of the

peak current of the NDR2 driver device that can be

controlled by the input VG gate Therefore an inverter

operation can be obtained at the output node between the

two NDR devices Figure 6 shows the simulated result

for an inverter logic circuit The VS is fixed at 15V

Fig 5 The MOBILE operation of an inverter circuit

Fig 6 The simulated results of an inverter logic based on

the MOBILE theory

IV Oscillator Design

The oscillator circuit is composed of a NDR inverter

a common source amplifier and a CMOS inverter as

shown in Figure 7

Fig 7 The circuit configuration of an oscillator based on

the MOS-NDR devices

When the output of NDR inverter rises from VOL to

VOH it makes impact to the next CMOS inverter The

output of voltage will rise from VOH to VOL The output

of INV1 will connect to the common source amplifier

The common source amplifier can provide the

180∘phase reverse The voltage output will rise form

VOL to VOH As shown in Fig 7 every circuit output is

affected by the previous one and then the last circuit

output goes back to affect the first circuit-NDR inverter

There has been transmission delay between every circuit

so that it makes circuit produce oscillation

We add a CMOS inverter (INV2) in back of the

output of the common source amplifier We design and

modulate the kNkP ratio to a smaller value which makes

the output of the common source amplifier obtain a

perfect wave The INV2 can be used as a load as well

Figure 8 shows the measured results of an oscillator

The INV1 and INV2 with number SN74HC04 and

MM74HC04 respectively are used in the measurement

The oscillator frequency is about 100MHz

Fig 8 The measured results of an oscillator

V Conclusions We have designed and demonstrated an oscillator

circuit based on the MOS-NDR devices and MOBILE

theory The circuit configuration is similar to the ring

oscillator We first obtain an inverter output from the

MOS-NDR MOBILE circuit Then we connect the

output of the MOS-NDR inverter with a common source

amplifier and a CMOS inverter The result shows that the

oscillator frequency is about 100MHz



assistance in arranging the fabrication of this MOS-NDR

chip This work was supported by the National Science

Council of Republic of China under the contract no

NSC93-2218-E-168-002


ldquoResonant tunneling device with multiple negative

differential resistance digital and signal processing

applications with reduced circuit complexity

IEEE Trans Electron Devices vol 34 pp

2185-2191 1987

2 T H Kuo H C Lin R C Potter and D Shupe

ldquoA novel AD converter using resonant tunneling


145-149 1991






127-129 1996



IEEE J Solid-State Circuits vol 14 pp 1094-1101

1979

Frequency Multiplier Using Multiple-Peak MOS-NDR Devices and Circuits

To-Kai Liang Kwang-Jow Gan Cher-Shiung Tsai Yaw-Hwang Chen Chi-Pin Chen

Long-Xian Su Chung-Chih Hsiao Feng-Chang Chiang and Shih-Yu Wang


Abstract

The design of a frequency multiplier based on the

multiple-peak negative differential resistance (NDR)

devices and circuits is demonstrated The NDR device

used in this work is composed of


devices The multiple-peak NDR circuit is obtained by

connecting two MOS-NDR devices in series This circuit

can exhibit three stable operating points These

phenomena can be used in a circuit that multiplied the

input signal frequency by a factor of three We design

and fabricate the MOS-NDR device and frequency

multiplier circuit by the standard 035μm CMOS process

Keywords multiple-peak NDR circuit MOBILE

oscillator circuit

I Introduction The negative differential resistance (NDR) devices

have attracted considerable attention in recent years for

their potential as functional devices for circuit

application There are many applications in signal

processing for a device that exhibits more than one NDR

region To obtain the multiple-peak current-voltage (I-V)

NDR characteristics we can connect two or more NDR

devices in series or parallel

The best famous known NDR device is the resonant

tunneling diode (RTD) [1]-[2] The fabrications of the

RTD devices are based on the technique of compound

semiconductor Comparing to Silicon-based integrated

circuit the fabrication cost of compound semiconductor

is more expensive However we proposed a new NDR

device that is composed of metal-oxide-semiconductor

field-effect-transistor (MOS) devices We call this device

as MOS-NDR device Because this device is totally

composed of MOS devices it is suitable for the process

of Si-based CMOS process

In this paper we demonstrate a two-peak NDR

device by combining two discrete MOS-NDR devices in

series and obtain two NDR regions with characteristics

suitable for applications such as frequency multipliers

II The Multiple-Peak MOS-NDR Devices Figure 1 shows a MOS-NDR device which is

composed of three NMOS transistors and one PMOS

transistor The gate of mn3 is connected to the output of

the inverter formed by mn1 and mn2 This circuit is

derived from a Λ-type topology described in [3] It can

exhibit various NDR I-V characteristics by choosing

appropriate values for transistors


mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT

Fig 2 The piecewise-linear PWL approximation of the

I-V characteristics of a MOS-NDR device

We use the piecewise-linear (PWL) approximation

method to describe the I-V characteristics of a

MOS-NDR device According to the PWL

approximation method we could model the I-V curve of

a one-peak NDR device by three segments as shown in

Fig 2 The electrical parameters are defined as follows

RP is the positive differential resistance RN is the

negative differential resistance and RT is the resistance

of the right-most region VP is peak voltage and VV is

the valley voltage IP is the peak current and IV is the

valley current VT and IT are the corresponding voltage

and current at one point on RT segment We have

supposed that TPN RRR conggt

When two identical NDR devices are connected in

series there are two peaks and valleys in the combined

I-V characteristics Their combined I-V characteristics

can be obtained by the load-line technique as shown in

Fig 3 The upper NDR device is treated as a load device

to the pull-down NDR device (driver device) Therefore

the load line is the I-V characteristics of the upper NDR

device and represented by the dashed lines in Fig 3 The

I-V characteristics of the driver device are shown by the

solid lines As seen in Fig 3(a) the load line will move

towards the right along the voltage axis as the bias

voltage is increased gradually from zero voltage to high

voltage We can obtain the series current for different

bias voltage by the stable intersection point of the two

I-V characteristics

Therefore the forward I-V characteristics follow the

breakpoints A B C D and E in order as shown in Figs

3(a)-3(f) The combined two-peak I-V characteristics are

shown in Fig 4

Fig 3 The load-line analysis for two MOS-NDR devices

in series

Fig 4 The combined I-V characteristics for two

series-connected MOS-NDR devices

We fabricate the MOS-NDR devices by the standard

035μm CMOS process Figure 5 shows the layout of a

MOS-NDR device The width parameters of the gate of

the MOS devices are described as mn1=10μm

mn2=100μm mn3=10μm and mp4=100μm The length

parameters of four MOS are all fixed at 035μmThe bias

Vgg is fixed at 33V for both two devices The

experimental I-V curve measured by HP-4155A for two

series-connected MOS-NDR devices connected in series

is shown in Fig 6

As shown we can obtain two peaks and valleys in

the combined I-V characteristics The measured results

are similar to our load-line analysis as shown in Fig 4

Since absolutely identical NDR devices do not exist in

practice the peak and valley currents between two

devices are slightly different Therefore there are small

differences between the measured and analytic results

Fig 5 The layout of a MOS-NDR device

0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3

Fig 6 The measured I-V results for two MOS-NDR

devices connected in series

III Frequency Multiplier Design The two-peak I-V characteristics can form three

stable states in their positive differential resistance

segments Figure 6 shows a 2KΩ load line which

intersects the I-V characteristics to form three stable

points It can be used for signal processing applications

such as frequency multiplying and waveform scrambling

and descrambling An example of frequency

multiplication is illustrated in Fig 7

Fig 7 Circuit configuration of a frequency multiplier

When a sawtooth waveform was applied to the circuit in

Fig 8(a) the output was also a sawtooth with a

frequency three times higher than the input frequency as

shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)

Fig 8 (a) Sawtooth waveform that was applied to the

circuit shown in Fig 7 (b)Output waveform across the

resistor

IV Conclusions

In this work we have demonstrated the two-peak

NDR circuit with two MOS-NDR devices in series The

two-peak I-V characteristics can form three stable states

in their positive differential resistance segments As a

result we demonstrated a frequency multiplier using two

MOS-NDR devices and circuits that can multiply the

input signal frequency by a factor of three

The conventional NDR devices such as resonant

tunneling diodes (RTD) are implemented by the

technique of III-V compound semiconductor The

fabrication cost of these RTD devices is more expensive

than that of Si-based technique However our NDR

devices and circuits are composed of MOS devices

Therefore we can fabricate the MOS-NDR device and

frequency multiplier circuit by the standard CMOS

process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979

Design and Simulation of Voltage Controlled Oscillator with High Frequency by Negative Differential Resistance Devices and Integrated Circuits

To-Kai Liang Shih-Yu Wang Kwang-Jow Gan Cher-Shiung Tsai Chung-Chih Hsiao

Feng-Chang Chiang Yaw-Hwang Chen Chi-Pin Chen and Long-Xian Su


Abstract The voltage controlled oscillator (VCO) design

based on the negative differential resistance (NDR)

devices and integrated circuits is demonstrated The

oscillator frequency is proportional to the magnitude of

input bias The NDR device is composed of


devices Therefore the oscillator can be fabricated by

standard CMOS process We discuss the simulated

results under 035μm CMOS process

Keywords voltage controlled oscillator negative

differential resistance CMOS process

I Introduction In recent years several new memory and logic

circuits based on negative differential resistance (NDR)

devices have been reported [1]-[3] The current-voltage

(I-V) characteristics of the NDR devices have several

advantages and they may have high potential as

functional devices due to their unique folding I-V

characteristics These novel devices also might overcome

the limits imposed by the complexity of conventional

transistor

First we design an inverter based on the negative

differential resistance (NDR) device We present a NDR



to be as MOS-NDR device Because this device is totally

composed of MOS devices it is suitable for the CMOS

process

Then we design an oscillator circuit based on the

035μm CMOS technique This oscillator is composed of

an NDR-based inverter two common source amplifiers

and a CMOS inverter We find that the oscillator

frequency is proportional to the magnitude of input bias

Therefore it is suitable for the voltage controlled

oscillator (VCO) design

II The Λ-type NDR Device Figure 1 shows a Λ-type MOS-NDR device which

is composed of three NMOS transistors This circuit can

show the a Λ-type I-V characteristic [4]

Fig 1 TheΛ-type NDR device circuit

Figure 2 shows the I-V curve measured by

Tektronix-370B curve trace with the width parameters

of the gate of the MOS devicesWQ1=1μmWQ2

=10μmWQ3 =40μm Each MOS length is fixed at

035μm The VGG is fixed at 33V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)

Fig 2 The measured I-V characteristics of a Λ-type

MOS-NDR device

The I-V characteristics of this NDR device could be

controlled by the VGG voltage Figure 3 shows the I-V

curve with the VGG voltage varying from 15V to 33V

by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V

Fig 3 The measured I-V characteristics of a NDR device

by varying the VGG voltages

III The Inverter based on Λ-type NDR Device






ITotal Figure 5 shows the measured I-V characteristics of

the Λ-type MOS-NDR device with VG varying from 0V

to 19V

Fig 4 The peak current of Λ-type MOS-NDR device

could be controlled by the VG voltage

Fig 5 The measured I-V characteristics of the Λ-type

MOS-NDR device with VG varying from 0V to 19V

Our inverter circuit design is based on two

series-connected MOS-NDR devices as shown in Fig 6

This circuit is called as monostable-bistable transition

logic element (MOBILE) [5] The input node is located

at the VG gate The output node is located between the

two MOS-NDR devices When the bias VS is bigger than

two peak voltage (2VP) but is smaller than two valley

voltage (2VV) there is two possible stable points

(bistable) that respect the low and high states




circuit By suitably determining the parameters of

devices and circuits we can obtain the inverter logic gate

as shown in Fig 7

Fig 6 The inverter circuit design based on the MOBILE

Fig 7 The measured result for an inverter circuit

IV Oscillator Design The oscillator circuit is composed of a NDR inverter

two common source amplifier and a CMOS inverter as

shown in Figure 8

Fig 8 The circuit configuration of an oscillator

When the output of NDR-based inverter rises from

VOL to VOH it makes impact to the common source

amplifier Because it is an invert amplifier it provides a

360∘reverse for two cascade common source amplifiers

When it works to amplify the output of voltage it makes

the next circuit work The output of every circuit is


output goes back to affect the first NDR-based inverter



The final stage of the inverter is composed of a

CMOS inverter We design the kNkP ratio to a smaller

value that makes the output of common source amplifiers

to obtain a perfect wave All of the circuit components

are made of NMOS devices so we can design the

oscillator according to the standard 035μm CMOS

process Figure 9 shows the 035μm CMOS layout of the

circuit

Fig 9 The layout of the oscillator

V Simulation Results Figure 10 shows the simulated results for the output of every stage If we changed the value of Vds2 voltage we can find that the oscillation frequency is proportional to the magnitude of input bias If we modulate the Vds2 voltage from 18V

from 3V step 02V the oscillator frequency is increased from 065GHz to 155GHz Therefore this circuit can be regarded as the voltage-controlled-oscillator (VCO) It can provide some useful applications in the NDR-based circuit and system design Further theory analysis and experiment results are under progressing It will be discussed elsewhere in the future

Fig 10 The simulated results for the output of every

stage shown in Fig 8

16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)

Fig 11 The relationship between the frequency and the

bias Vds2

VI Conclusions We have designed a voltage-controlled-oscillator

(VCO) based on the Λ-type NDR-based devices and

circuits according to the standard 035μm CMOS process

The oscillator circuit configuration is similar to the ring

oscillator From the simulated analysis we find that the

oscillation frequency is proportional to the magnitude of

bias The oscillator frequency is about 155 GHz under

3V

Acknowledgement This work was supported by the National Science


NSC93-2218-E-168-002




processing applications with reduced circuit

complexityIEEE Trans Electron Devices vol

34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996

Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits

Dong-Shong Liang Kwang-Jow Gan Long-Xian Su Chi-Pin Chen Chung-Chih Hsiao Cher-Shiung Tsai

Yaw-Hwang Chen Shih-Yu Wang Shun-Huo Kuo and Feng-Chang Chiang


Abstract--This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters Due to its folding I-V characteristics multiple -peak NDR device is a very promising device for multiple -valued logic application This memory cell structure can be easily extended to implement more states in a memory circuit

I Introduction

The multiple-peak negative differential resistance (NDR) devices offer much promise for multi-valued memory circuits [1]-[4] Taking full advantages of the NDR device we can reduce circuit complexity to enhance circuit performance in terms of operation speed chip area and power consumption Previously published memory circuits usually consisted of resonant tunneling diode (RTD) in series However these RTD devices are fabricated by the III-V compound semiconductor and process Therefore the RTD devices are difficult to combine with other devices and circuits to achieve the system-on-a-chip (SoC)

However the MOS-NDR device used in this work is fully composed of metal-oxide-semiconductor field-effect- transistor (MOS) devices During suitably arranging the MOS parameters we can obtain the NDR characteristic in its I-V curve Therefore we can implement the MOS-NDR devices and related circuits by Si-based CMOS or BiCMOS process So it is much more convenient to achieve the SoC

Numerous multiple-peak applications using two or more NDR devices in series or vertical integration create the multiple-peak I-V characteristics These devices could be treated as independent devices connected in series However we use three MOS-NDR devices connected in parallel to create the three-peak I-V characteristics The three-peak MOS-NDR device can have four stable states at its positive differential resistance (PDR) segments during suitable load design Using this three-peak MOS-NDR device with a constant current source load a four-state multi-valued memory circuit is demonstrated by the 035μm CMOS process

II the multiple-peak MOS-NDR Device

The prototype MOS-NDR device as shown in Fig 1 is composed of three NMOS transistors and one PMOS transistor The gate of mn3 is connected to the output of the inverter formed by mn1 and mn2 It can exhibit various NDR current-voltage characteristics by choosing appropriate values for transistors Figure 2 shows the simulation results by HSPICE program The width parameters are designed as mn1=5μm mn2=100μm mn3=10μm and mp4=100μm The length parameters are

all fixed at 035μm The VGG is 33V This circuit also can show the Λ-type NDR I-V characteristic as shown in Fig 3 if we take off the mp4 device from Fig 1

Fig 1 Circuit configuration of a MOS-NDR device

Fig 2 Simulated result for the MOS-NDR device by HSPICE program

Numerous multiple-peak applications often use two or

more NDR devices in series or vertical integration to create the multiple-peak I-V characteristics But it is difficult to simulate the series circuit of NDR devices [5] Therefore we design the multiple-peak NDR characteristics by connecting the MOS-NDR devices in parallel as shown in Fig 4 The MOS-NDR1 and MOS-NDR2 are designed by the N-type devices The MOS-NDR3 is designed by the Λ-type device The mn4 mn8 and mn9 devices are used to delay the turn-on voltage of MOS-NDR2 and MOS-NDR3 respectively The simulated result is shown in Fig 5 The Vgg voltages are all fixed at 33V

mn1

mn2

3mp4

VGG

VDD

Fig 3 Simulated result for the Λ-type I-V characteristic

Fig 4 Circuit configuration of the multiple-peak MOS- NDR device

Fig 5 Simulated result for the multiple-peak MOS-NDR device

III MULTIPLE ndashVALUED MEMORY CIRCUIT DESIGN

Due to the folding I-V characteristics multiple-peak NDR device is a very promising device for multi-valued logic application The obvious method to bias the multiple-peak NDR device into the multiple stable states is to use a resistor or a constant current source as a load as shown in Fig 6 respectively For the three-peak MOS-NDR device there are at most four stable states from V1 to V4 When the series resistor exceeds the magnitude of the NDR of the multiple-peak device the series resistor can be considered as a load resistance which intersects the PDR regions of the multiple-peak device at multiple stable states When one locates the stable points one always locates the points of intersection on the PDR region because all the intersection points on the NDR region are always unstable

Fig 6 The I-V characteristics for multiple-valued memory circuit using either a resistor load or a constant current source

If a constant current source is used as the load device the current could be adjusted through appropriate device parameters to a value approximately halfway between the peak and valley current of the multiple-peak NDR device By comparing to the resistor load configuration the memory circuit using the constant current source as the load device has two advantages the better noise margins for the four stable states and the low power dissipation [6]

Fig 7 The four-valued MOS-NDR memory circuit

Figure 7 shows the four-state MOS-NDR memory circuit The voltage to be stored is provided at the cell input and loaded by momentarily enabling the write clock The input voltage then controls the voltage at the multiple-peak MOS-NDR node When the write clock is disabled the voltage across the MOS-NDR device adjusts to the nearest stable operating point thereby storing the input value at one of the four discrete levels

A saw-tooth wave is applied to the input of the memory circuit with amplitude of 35V A square wave is then applied to the write gate input which alternately turns the MOS on and off The output of this memory circuit gives the four stable memory values as shown in Fig 8 We can understand the attractive feature for this memory circuit for the constant-current-source load is that the noise margin would remain the same with a further increase in the number of current peaks of the multiple-peak MOS-NDR device The design of this memory circuit is demonstrated by the standard 035μm CMOS process We design the constant current source by the MOS devices

currentsource

V1 V2V3

V4

R

Fig 8 Simulated results for the MOS-NDR memory circuit

V CONCLUSIONS

In this work we have demonstrated the three-peak MOS-NDR circuit with three MOS-NDR devices connected in parallel The series combination of this device with a constant-current-source load is used to demonstrate the operation of a four stable state memory cell Because all of the devices used in this circuit are fully composed of MOS devices we can fabricate this memory circuit by the standard Si-based CMOS or BiCMOS process Furthermore this MOS-NDR device and circuit will be easy to integrate with other device and circuit to achieve the goal of SoC

Acknowledgments


References



[15] S J Wei and H C Lin ldquoMultivalued SRAM cell using resonant tunneling diodesrdquo IEEE J Solid-St Circuits vol 27 pp 212-216 1992

[16] A C Seabaugh Y C Kao and H T Yuan rdquoNine-state resonant tunneling diode memoryrdquo IEEE Electron Device Lett vol 13 pp 479-481 1992

[17] K J GanldquoHysteresis phenomena for the series circuit of two identical negative differential resistance devicesJapanese Journal of Applied Physics Vol 40 No 4A pp 2159-2164 2001


An oscillator design based on MOS differential amplifier by simulation

Cher-Shiung Tsai Ming-Yi Hsieh Jia-Ming Wu Chun-Chieh Liao Jeng-Lung Wu Kwang-Jow

Gan Yaw-Hwang Chen Dong-Shong Liang Chia-Hung Chen and Chung-Chih Hsiao Department of Electronic Engineering Kun Shan University

Tainan Taiwan 710 ROC

Abstract mdash In this thesis we present an oscillator mainly composed by a MOS differential amplifier The simulations use H-spice to verify the differential amplifier oscillator under CIC 035μm Si-Ge process parameters We have used discrete devices on bread board to prove such circuit is an oscillator circuit successfully [1-2] Simulations show such an oscillator can work stably from 08 volts to 33 volts supply voltage When supply voltage is close to 33 volts the output frequency will be more than 14 GHz The differential amplifier oscillator can start oscillating at low voltage when supply voltage is only 08 volts and output frequency is about 32 MHz We use FFT (Fast Fourier Transform) diagram to analyze the oscillator and shows the oscillator is with low noise characteristic Finally those simulation results reveal that the oscillator is not only an excellent voltage controlled oscillator (VCO) but also low power consumption

Keyword mdash Differential amplifier VCO FFT

I INTRODUCTION

We use the high input resistance high output resistance and high voltage gain characteristics of MOS differential amplifier [3-5] to create an oscillator Such oscillator is based on differential amplifier have two outputs one output is high voltage state and the other will be in low voltage state We connect one CMOS inverter and two CMOS inverters after two different outputs

It is an asymmetric structure and most output waveform tends to be square waveform The oscillator frequencies are decided by PMOS NMOS resistors MOS transistors and CMOS inverters In this thesis we present a different type oscillator and use simulation results to prove such oscillator is useful easiness and flexibility in design

II CIRCUIT THEOREM

The oscillator is composed of MOS differential amplifier by adding three CMOS inverters as shown in Fig1 A formal differential amplifier needs a constant current source but we use resistor NM1 to replace the constant current source for simplicity According to differential amplifier operation transistor M1 and M2 canrsquot be both off or both in triode state in the same time Transistors M1 M2 will both in saturation state or one is

saturation and the other is off Owing to we canrsquot fabricate two identical transistors M1 and M2 so most conditions are M1 saturation and M2 off or M1 off and M2 saturation

In Fig1 we assume M1 saturation and M2 off so voltage OP1 is in low state and voltage OP2 is in high state In the meanwhile voltage G1 is in high state and voltage G2 is low state After CMOS inverter (INV1) time delay voltage G2 becomes high state to turn on transistor M2 so voltage OP2 changes into low state After CMOS inverters (INV2 INV3) time delay voltage G1 changes into low state to turn off transistor M1

Base on same analysis M2 will be off and M1 will be saturation in the next run After a fixed period M1 and M2 will toggle their states Such onoff continuous switching phenomena will cause oscillation The nodes or transistors status in Fig1 shows in Table1

Fig1 The MOS differential amplifier oscillator

M1 M2 OP1 OP2 G1 G2

State1 Sat Off L H H L

State2 Off Sat H L L H

Table1 Status of transistors and nodes of Fig1

Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State

III SIMULATION RESULTS

In this thesis we use H-Spice and CIC 035um Si-Ge process parameter to run simulations The discrete devices are MOS transistors M1 (M2) resistors PM1 NM1 and CMOS inverters The channel length of all MOS devices in simulations is fixed and minimum value (l=035μm)

The output waveform under 08 volts supply voltage and oscillation frequency is 32 MHz as shown in Fig2 M1 (or M2) channel width is 15μm Resistor PM1 and NM1 are PMOS and NMOS respectively their gates are connected to ground or VDD to become resistors In Fig1 the channel width of PM1 and NM1 are 10μm 40μm respectively

Fig2 Output waveform under 08 volts

Fig3 shows the oscillator with same condition under 33 volts supply voltage and its output frequency is 14 GHz


Fig4 is the typical fast Fourier transform (FFT) diagram of the MOS differential amplifier oscillator Fig4 shows the oscillator with low noise characteristics The highest signal is more than the most other signals about 28 db in Fig4 It means the main oscillation signal is twenty-five (102820=251) times stronger than the most

other signals If the main signal is 15 volts then the most others signals shall be smaller than 006 volts Most conditions are noise signals will become larger as output frequency increases in the MOS differential amplifier oscillator

Fig4 Typical FFT diagram of the MOS differential amplifier oscillator

Fig5 shows resistor NM1 (width=40μm) and transistor Q1 (Q2) unchanged but PM1 channel width is changed from 4μm to 10μm Fig5 reveals larger channel width of PM1 will have higher output frequency because larger channel width has smaller resistance

1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u

Fig5 Oscillator output frequencies under different width of PM1 and supply voltages

Fig6 shows resistor PM1 (width=10μm) and transistor M1 (M2) unchanged but NM1 is changed from 20μm to 40μm Fig8 also reveals larger channel width of NM1 will have higher output frequency because larger channel width has resistance M1 (M2) in Fig4 or Fig5 is the same as Fig2 which the channel width of M1 (M2) is 15μm

Fig7 shows resistors PM1 (width=10μm) and NM1 (width=40μm) unchanged but transistor M1 (or M2) channel width is changed The channel widths of transistor M1 (or M2) are 7μm and 15μm respectively

1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u

Fig6 Oscillator output frequencies under different width of NM1 and supply voltages

The effect of M1 (or M2) is the same as those effects of resistors PM1 and NM1 on output frequency response The larger channel width transistor has higher output frequency because of higher gm value

08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u

Fig7 Oscillator output frequencies under different M1 (M2) and supply voltages

From Fig5 to Fig7 the oscillation frequency increases as supply voltage increases It shows the MOS differential amplifier oscillator is also a voltage controlled oscillator (VCO) The MOS differential amplifier oscillator shows excellent VCO linearity from 08 volts to 33 volts supply voltage as shown in Fig8 We will take use of the nice VCO linearity in our next new phase lock loop (PLL) project

Fig9 shows the power dissipation of MOS differential oscillator under different output frequencies Itrsquos only 10μW under 08 volts supply voltage and output frequency is 32 MHz While supply voltage is 33 volts its output frequency is 14 GHz but power dissipation will be only 225mW

The power dissipation is proportional to the square of output voltages in Fig9 It is consistent with CMOS devices power dissipation PDD = fCV2

DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO

Fig8 Voltage controlled oscillator (VCO) characteristics of Fig1

05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd

Fig9 Oscillator power dissipation under different output voltages

Fig10 shows the layout of the MOS differential amplifier oscillator with 035μm Si-Ge process We have applied CIC process successfully and will receive those chips in this September The applied CIC chip includes three different sizes to get 500MHz 700MHz and 900MHz output frequencies under 20 volts supply voltage respectively

Fig10 Layout of MOS differential amplifier oscillator

IV CONCLUSIONS

The MOS differential amplifier oscillator generates square wave not the same as traditional oscillators such as quarts oscillator or ring oscillator can generate sinusoidal waves It is the same as general oscillators that the noises of MOS differential amplifier oscillator are proportional to output frequencies

The MOS differential amplifier oscillator still has three advantages of good linearity voltage controlled (VCO) characteristic low noise and low power dissipation characteristics

In our simulations increase those channel widths of PM1 NM1 or M1 (M2) values can increase output frequency As we know VCO is the leading role of phase lock loop (PLL) circuit Our new project is phase lock loop circuits the MOS differential amplifier oscillator will be the first priority in our PLL VCO block

If we implement those MOS differential amplifier oscillators into IC chips in this September then we will measure output frequencies and power dissipations under different supply voltages We will also get FFT (Fast Fourier Transform) diagram to analyze the noise characteristics When we have those measurement data then we will compare those differences between simulations and experiments

Finally we will find out the limitations of the H-spice on frequency domain power dissipation and noise characters

ACKNOWLEDGEMENTS

The authors would like to thank the National Science Council of Republic of China for their generous and kind support This work was supported by the National Science Council of Republic of China under the contract no NSC93-2218-E-168-002

REFERENCES [1] Cher-Shiung Tsai Chun-Chieh Liao Jia- Ming Wu

Ming-Yi Hsieh Kwang-Jow Gan Dong-Shong Liang Yaw-Hwang Chen Chia-Hung Chen and To-Kai Liang ldquoAn Oscillator Design Based on BJT Differential Amplifierrdquo 第三屆微電子技術發展與應用研討會國立高雄海洋科技大學 94520 2005

[2] Cher-Shiung Tsai Jia-Ming Wu Ming-Yi Hsieh Chun-Chieh Liao Tien-Hung Chang Kwang-Jow Gan Dong-Shong Liang Yaw-Hwang Chen Chia-Hung Chen Chun-Ming Wen ldquoA MOS DIFFERENT- IAL AMPLIFIER OSCILLATORrdquo 16th VLSI DesignCAD Symposium 花蓮美崙大飯店 9489~12 2005

[3] Richard C Jaeger and Travis N Blalock ldquoMicroelectronic Circuit Designrdquo 2nd edition pp 1087-1108 2003

[4] Adel S Sedra and Kenneth C Smith ldquoMicroelectronic Circuitsrdquo 5th edition pp 687-719 2004

[5] Randall L Geiger Phillip E Allen and Noel R Strader ldquoVLSI Design Techniques for Analog and Digital Circuitsrdquo pp 431-454 1990

Adel S Sedra and Kenneth C Smith ldquoMicroelectronic

Circuitsrdquo 5

Frequency Divider Design Using Negative Differential Resistance Device

Kwang-Jow Gan Chun-Da Tu Chi-Pin Chen Yaw-Hwang Chen Cher-Shiung Tsai Dong-Shong

Liang Wei-Lun Sun Chia-Hung Chen Chun-Ming Wen Chung-Chih Hsiao Shih-Yu Wang and Feng-Chang Chiang


Abstract mdash This paper demonstrate a chaos generator

using a R-BJT-NDR device We utilize two bipolar junction transistors and four resistors to construct the R-BJT-NDR device which can show the negative differential resistance (NDR) characteristic in its current-voltage curve by suitably modulating the resistances We will demonstrate a frequency divider using the chaos generator This circuit is consisted of a R-BJT-NDR device an inductor and a capacitor We investigate the effects of the input frequency and the bias voltage on the operation

Index Terms mdash chaos generator R-BJT-NDR device

frequency divider

I INTRODUCTION

The negative differential resistance (NDR) devices are attractive for high-frequency applications and high-speed logic applications [1]-[3] One of the most important features of the NDR devices is their strong nonlinearity A circuit consisting of such nonlinear characteristic often shows the chaos phenomenon In this paper we will design a chaos generator circuit using an R-BJT-NDR device and demonstrate its application to a dynamic frequency divider

The frequency divider is simply made of a R-BJT-NDR device an inductor and a capacitor The R-BJT-NDR device is composed of two bipolar junction transistors and four resistors During suitably arranging the resistances we can obtain the NDR characteristic in its current-voltage (I-V) curve In comparison with the traditional NDR devices such as resonant tunneling diode (RTD) the fabrication of R-BJT-NDR device will be much cheaper and easier than RTD

The applications using nonlinear circuits using the chaotic behavior have been studied intensively in the field of information processing and communication systems [4] In this work we investigate the operating margins of this circuit with respect to input signal frequency and the bias voltage

II R-BJT-NDR DEVICE

We proposed a NDR device that is composed of the bipolar junction transistors (BTJ) and resistors (R) devices We call this device as R-BJT-NDR device Because this device is fully composed of the BJT and R it is suitable for the process of Si-based CMOS or BiCMOS technique This R-BJT-NDR device is composed of two n-p-n transistors and five resistors as shown in Fig 1 During suitably arranging the values of the five resistors we can obtain the I-V curve with NDR characteristics Figure 2 shows the simulated I-V characteristics by Hspice program The electrical parameters are R1=45kΩ R2=53kΩ R3=100kΩ R4=12kΩ and R5=6kΩ

VS

R1

R2

R3

R4

R5Q1

Q2

Fig 1 NDR device is composed of two transistors and five resistances

Fig 2 Simulated I-V characteristics by Hspice program

III CHAOS CIRCUIT

Figure 3 shows the configuration of a frequency divider This frequency divider consists of a R-BJT-NDR device an inductor and a capacitor This is a kind of van der Pol oscillator having an input terminal The differential equations determining the systemrsquos behavior are expressed as

LtVtV

dttdi outinL )()()( minus= (1)

out

outNDRLout

CViti

dttdV )()()( minus= (2)

When an external oscillating signal Vin=Vo+ Asin(2πft) is applied this circuit will generate the chaos phenomenon in such nonlinear system Where Vo 2A and f are input bias amplitude and frequency respectively This circuit can output various types of signal patterns including chaos as shown in Fig 4

Fig 3 Configuration of the chaos generator circuit

Fig 4 Simulated waveforms of Vout in a chaotic state

We can also observe the long-period behavior in some regions This is called the bifurcation phenomenon In the bifurcation region the systemrsquos output period is the integer-multiple of the input period It should be noted that the operation frequency range depends on the LC characteristic frequency determined as (12π LC ) Therefore a frequency range close to the cutoff frequency of the R-BJT-NDR device is expected if the appropriate values are chosen for L and C

Figure 5 shows the circuitrsquos output period as a function of the input frequency Figures 5(a)-(b) illustrate the waveforms obtained from the simulation for 2T and 3T under input frequency 15MHz and 18MHz respectively The waveforms show the results for 12 and 13 frequency dividing states respectively

(a)

(b)

Fig 5 (a) a 12 frequency dividing state (b) a 13 frequency dividing state

The frequency dividing operation is explained by the relationship between the charging time of the capacitance Cout and the input period At low input frequency charges are supplied to the output capacitance during a cycle of the input That will be sufficient to switch the R-BJT-NDR device However when the input frequency increases the charges supplied to the capacitance during a cycle decrease due to the shorter period and the increased impedance of the inductor Then the amount of charges supplied to the capacitance is not sufficient to switch the R-BJT-NDR device Therefore two or more cycles are necessary to switch the MOS-BJT-NDR device This causes the frequency dividing operations of 12 13 and so on The phenomena are called period-adding bifurcation Figure 6 shows the circuitrsquos output period as a function of the input frequency The output period increases discontinuously with increasing frequency There will

be a chaos phenomenon existed at the transition

Fig 6 The output period will be a function of input signal

The magnitude of the input bias will affect the results of frequency divider The values of L C and f are fixed at 1mH 10pF and 16MHz respectively Figure 7 shows the dividing ratio as a function of the bias voltage As seen stable 12 13 and 14 dividing operations can be obtained in the simulation results The results demonstrate the dividing ratio can be selected by changing the input bias Figure 8 illustrates the bias regions for the frequency divider Black areas denote the chaos regions

(a)

(b)

(c)

Fig 7 (a) a 12 frequency dividing state (b) a 13 frequency dividing state (b) a 14 frequency dividing state

Fig 8 The dividing ratio as a function of the input bias

IV CONCLUSIONS

We have proposed a NDR-based chaos circuit and its application to a novel frequency divider This chaos circuit is based on the strong nonlinearity of an R-BJT-NDR device We have studied the operation of the frequency divider circuit with respect to the input signal frequency and input bias The frequency dividing operation is based on the bifurcation phenomenon which appears in the chaotic system The dividing ration can be selected by changing the input frequency and input bias

ACKNOWLEDGMENTS


References


[8] A F Gonzalez and P Mazumder ldquoMultiple-valued signed-digit adder using negative differential-resistance devicesrdquo IEEE Trans Comput vol 47 pp 947-959 1998


[10] M J Ogorzalek Chaos amp Complexity in Nonlinear Electron Circuit World Scientific 1997

increases but total current Idd decreases It creates a

NDR phenomenon Fig 2 shows the I-V

characteristics of the MOS-NDR device by H-spice

simulation

Fig 2 The simulated I-V curve of Fig 1

3 MOS-NDR Inverter

In this work we demonstrate an inverter gate

design that is based on the monostable-bistable

transition logic element (MOBILE) theory A

MOBILE cell is consisted of two NDR devices in

cascade structure as shown in Fig 3 During a period

when the input signal rises the voltage at the output

node between the two NDR devices goes to one of

the two stable states (low and high corresponding to

ldquo0rdquo and ldquo1rdquo in binary logic) depending on which

NDR devices is reached the second positive

differential resistance (PDR) region first The

controlled process obeys a rule the MOS-NDR

device with the smaller peak current is always

reached the second PDR region first Based on the

MOBILE theory and control rule the measured result

of inverter logic is implemented

In Fig 3 when input (Vin) is in high state then

NMOS is on The summation of driver current and

NMOS current is larger than load current the

operating point will be located at point Stable1 and

output state is in low state as Fig 4 shows

Fig 3 Configuration of an inverter by MOS-NDR

circuit

Vin=High Vout=Low Fig 4 When IDriver+VingtILoad operating point at

stable1 and output is in low State

On the contrary in Fig 3 when input (Vin) is in

low state then NMOS is off The driver current is

smaller than load current the operating point will be

located at point Stable2 and output state is in high

state as Fig 5 shows Such an operation just likes an

inverter

Vin=Low Vout=High

stable2 Fig 5 When IDriver ltILoad operating point at stable2

and output is in high state

VS V

I Load Driver

Out(H)

V

I

VS

Driver + VinLoad

Out(L)

stable1























measure it


circuit





circuit of Fig 3






swing









NDR1

NDR2

Vs

(Load)

(Driver)

OUT

mn1

R1 R2

mn2

NMOS

Vin






is 21 Volts


supply voltage





characteristics







006 (=152512) Vp-p






frequency signal


6 Conclusions













in design items

Acknowledgements







References
















17 pp 309-311 1996














vol 41 pp 148-153 1994








2004






ABSTRACT






2 CIRCUIT ANALYSIS




VS

R1

R2

R3

R4

R5Q1

Q2








3 MESURED RESULTS




0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References



























measure it


circuit





circuit of Fig 3






swing









NDR1

NDR2

Vs

(Load)

(Driver)

OUT

mn1

R1 R2

mn2

NMOS

Vin






is 21 Volts


supply voltage





characteristics







006 (=152512) Vp-p






frequency signal


6 Conclusions













in design items

Acknowledgements







References
















17 pp 309-311 1996














vol 41 pp 148-153 1994








2004






ABSTRACT






2 CIRCUIT ANALYSIS




VS

R1

R2

R3

R4

R5Q1

Q2








3 MESURED RESULTS




0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References










is 21 Volts


supply voltage





characteristics







006 (=152512) Vp-p






frequency signal


6 Conclusions













in design items

Acknowledgements







References
















17 pp 309-311 1996














vol 41 pp 148-153 1994








2004






ABSTRACT






2 CIRCUIT ANALYSIS




VS

R1

R2

R3

R4

R5Q1

Q2








3 MESURED RESULTS




0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





References
















17 pp 309-311 1996














vol 41 pp 148-153 1994








2004






ABSTRACT






2 CIRCUIT ANALYSIS




VS

R1

R2

R3

R4

R5Q1

Q2








3 MESURED RESULTS




0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References










ABSTRACT






2 CIRCUIT ANALYSIS




VS

R1

R2

R3

R4

R5Q1

Q2








3 MESURED RESULTS




0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






VS

R1

R2

R3

R4

R5Q1

Q2








3 MESURED RESULTS




0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References







0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16

Cur

rent

(mA

)

55K 75K65K


0 1 2 3 4 5

Voltage (V)

0

04

08

12

16C

urre

nt (m

A)

53K 33K43K



4 INVERTER DESIGN








5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References











5 CONCLUSIONS




ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






ACKNOWLEDGMENTS


REFERENCES












MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References











MOS-NDR1

MOS-NDR2 CS

INV

OUT

Vds1 Vds2






1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References










1 INTRODUCTION










mn1

mn2

mn3 mp4

Vgg

Vdd

0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR








0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V






T1

T2 T3

VS

Vout

NDR1 Load

NDR2 Driver

Driver + T2 or T3

Out(L) VS V

Load

Driver

Out(H)

Q Q

I







Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References











Inverter NOR NAND

VS 15V 15V 15V

T1 OFF 12V 33V


T3 OFF INPUT INPUT



5 CONCLUSIONS


ACKNOWLEDGMENTS


REFERENCES














I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References
















I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References











I Introduction








0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


(1) (2) (3) (4)












0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References













0

2

4

6

8

10

Pow

er D

issi

patio

n (m

W)


III VCO DESIGN










120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References














120

160

200

240

280

Freq

uenc

y (M

Hz)



0

10

20

30

40

Pow

er D

issi

patio

n (m

W)




ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






ACKNOWLEDGMENTS


REFERENCES















I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References












I INTRODUCTION





II MOS-NDR INVERTER





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V







III VCO Design








16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References











16 2 24 28Voltage (V)

0

50

100

150

200

250

Freq

uenc

y (M

Hz)


IV CONCLUSIONS



ACKNOWLEDGMENTS



REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






REFERENCES



















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References
















16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References







16 18 2 22 24Voltage (V)

0

40

80

120

160

200

Freq

uenc

y (M

Hz)


and the bias VS



















Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References









Abstract


















































0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References









0 04 08 12 16

Voltage (V)

00

10

20

30

Cur

rent

(mA

)

Vgg=33V

Vgg=2V

Vgg=15V

Vgg=25V

Vgg=3V

1st PDR NDR

2ndPDR




















circuit











0 04 08 12 16

Voltage (V)

00

20

40

60

Cur

rent

(mA

)


0V1V15V2V

25V3V

33V


voltages














operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References
















operation































NSC93-2218-E-168-002





34 pp 2185-2191 1987



145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






145-149 1991










127-129 1996




1094-1101 1979




Comput vol 47 pp 947-959 1998




Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References








Abstract











circuit





































mn1

mn2

mn3

Vdd

NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





NDR2(Driver)

NDR1(Load)

VS

Out

VG










0 04 08 12 16 2Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

)

5μm

1μm

10μm

modulation of mn1










ITotal





































the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References


















the MOBILE theory




shown in Figure 7


the MOS-NDR devices



































NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References



















NSC93-2218-E-168-002






2185-2191 1987




145-149 1991






127-129 1996




1979





Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References









Abstract














oscillator circuit
































mn1

mn2

mn3

Vdd

I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





I

V

IP

RP1

RN1

VV

RT

1

VP

IV

VT

IT






























I-V characteristics




shown in Fig 4


in series












is shown in Fig 6









0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References












0 1 2 3 4

Voltage (V)

0

05

1

15

2

25

Cur

rent

(mA

) Load Line (Rout)

Q1

Q2

Q3















shown in Fig 8(b)

-04 0 04 08Time (ms)

0

04

08

12

16

2

Vol

tage

(V)

(a)

-04 0 04 08Time (ms)

0

02

04

06

08

Vol

tage

(V)

(b)



resistor

IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





IV Conclusions
















process






NSC93-2218-E-168-002





34 pp 2185-2191 1987




145-149 1991




1094-1101 1979
























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References




























transistor







process

















0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2C

urre

nt(m

A)


(1) (2) (3) (4)


MOS-NDR device




by a step of 03V

0 05 1 15 2 25

Voltage(V)

0

04

08

12

16

2

Cur

rent

(mA

)


VGG=15V

VGG=33V











to 19V



















as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






as shown in Fig 7





shown in Figure 8



















circuit






16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References








16 2 24 28 32Voltage (V)

06

08

1

12

14

16

Freq

uenc

y (G

Hz)


bias Vds2








3V



NSC93-2218-E-168-002






34 pp 2185-2191 1987




145-149 1991




Comput vol 47 pp 947-959 1998




1094-1101 1979






127-129 1996






I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References










I Introduction











mn1

mn2

3mp4

VGG

VDD











currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References















currentsource

V1 V2V3

V4

R


V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






V CONCLUSIONS


Acknowledgments


References













I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References











I INTRODUCTION



II CIRCUIT THEOREM






M1 M2 OP1 OP2 G1 G2




Vcc

PM1 PM1

NM1

OP1 LH

OP2 HL

CMOS INV1 HL

CMOS INV2

M1 M2

CMOS INV3

HL

G1

HL

G2

LH

OUTPUT

Change State











1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References















1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

PM1

4u

10u




1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

NM1

20u

40u



08 12 16 2 24 28 32V

0

400

800

1200

1600

MHZ

M1(M2)

7u

15u





DD [6]

05 1 15 2 25 3 35V

0

400

800

1200

1600

MHZ

VCO


05 1 15 2 25 3 35V

0

5

10

15

20

25

mW

Pdd




IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





IV CONCLUSIONS






ACKNOWLEDGEMENTS









Circuitsrdquo 5








frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References












frequency divider

I INTRODUCTION




II R-BJT-NDR DEVICE


VS

R1

R2

R3

R4

R5Q1

Q2



III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References






III CHAOS CIRCUIT


LtVtV


out

outNDRLout

CViti







(a)

(b)






(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References








(a)

(b)

(c)



IV CONCLUSIONS


ACKNOWLEDGMENTS


References





Documents

An Oscillator Design Based on MOS-NDR Inverter...vol 41, pp. 148-153, 1994 8. Tomoyuki Akeyoshi, Koichi Maezawa, and Takashi Mizutani, “Weighted sum threshold logic operation of