Analysis and Synthesis of Boolean Networks871622/FULLTEXT01.pdf · Analysis and Synthesis of Boolean Networks MING LIU Licentiate Thesis in Electronic and Computer Systems Stockholm,

Analysis and Synthesis of Boolean Networks

MING LIU

Licentiate Thesis in Electronic and Computer SystemsStockholm, Sweden 2015

TRITA-ICT 2015:23ISBN 978-91-7595-770-8

KTH School of Information andCommunication TechnologySE-164 40 Kista, Stockholm

SWEDEN

Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framläggestill offentlig granskning för avläggande av licentiatexamen i ämnet Elektronik ochdatorsystem fredag den 18 december 2015 klockan 09.00 i Sal B, Electrum, KunglTekniska högskolan, Kista 16440, Stockholm.

© Ming Liu, November 2015

Tryck: Universitetsservice US AB

iii

Abstract

In this thesis, we present techniques and algorithms for analysis and syn-thesis of synchronous Boolean and multiple-valued networks.

Synchronous Boolean and multiple-valued networks are a discrete-spacediscrete-time model of gene regulatory networks. Their cycle of states, calledattractors, are believed to give a good indication of the possible functionalmodes of the system. This motivates research on algorithms for finding at-tractors. Existing decision diagram-based approaches have limited capacitydue to the excessive memory requirements of decision diagrams. Simulation-based approaches can be applied to large networks, however, their results areincomplete. In the first part of this thesis, we present an algorithm, whichuses a SAT-based bounded model checking approach to find all attractorsin a multiple-valued network. The efficiency of the presented algorithm isevaluated by analysing 30 network models of real biological processes as wellas 35 000 randomly generated 4-valued networks. The results show that ouralgorithm has a potential to handle an order of magnitude larger models thancurrently possible.

One of the characteristic features of genetic regulatory networks is theirinherent robustness, that is, their ability to retain functionality in spite of theintroduction of random faults. In the second part of this thesis, we focus onthe robustness of a special kind of Boolean networks called Balanced BooleanNetworks (BBNs). We formalize the notion of robustness and introduce amethod to construct BBNs for 2-singleton attractors Boolean networks. Theexperiment results show that BBNs are capable of tolerating single stuck-atfaults. Our method improves the robustness of random Boolean networks byat least 13% on average, and in some special case, up to 61%.

In the third part of this thesis, we focus on a special type of synchronousBoolean networks, namely Feedback Shift Registers (FSRs). FSR-based filtergenerators are used as a basic building block in many cryptographic systems,e.g. stream ciphers. Filter generators are popular because their well-definedmathematical description enables a detailed formal security analysis. We showhow to modify a filter generator into a nonlinear FSR, which is faster, butslightly larger, than the original filter generator. For example, the propagationdelay can be reduced 1.54 times at the expense of 1.27% extra area. Thepresented method might be important for applications, which require veryhigh data rates, e.g. 5G mobile communication technology.

In the fourth part of this thesis, we present a new method for detect-ing and correcting transient faults in FSRs based on duplication and paritychecking. Periodic fault detection of functional circuits is very importantfor cryptographic systems because a random hardware fault can compromisetheir security. The presented method is more reliable than Triple ModularRedundancy (TMR) for large FSRs, while the area overhead of the two ap-proaches are comparable. The presented approach might be important forcryptographic systems using large FSRs.

iv

Sammanfattning

I denna avhandling presenterar vi metoder och algoritmer för analys ochsyntes av synkrona Booleska och flervärda nätverk.

Synkrona Booleska och flervärda nätverk är rums-och tidsdiskret modellav regulatoriskt gennätverk. Deras fillständscykler, som kallas attractorer, trosge en god indikation på möjliga funktionssätt i systemet. Detta motiverarforskning om algoritmer för att hitta attraktorer. Befintliga beslutsdiagrambaserade metoder har begränsad kapacitet på grund av orimliga minneskrav.Simuleringsbaserade metoder kan tillämpas på stora nätverk, men ger ofull-ständiga resultat. I den första delen av denna avhandling presenterar vi enalgoritm som använder en SAT-baserad modell för gränsvärdes kontroll för atthitta alla attraktorer i flervärda nätverk. Effektiviteten av den presenteradealgoritmen utvärderas genom att analysera 30 nätverksmodeller av verkligabiologiska processer samt 35 000 slumpmässigt genererade 4-värda nätverk.Resultaten visar att vår algoritm har potential att hantera en storleksordningstörre modeller än vad som nu är möjligt.

En karakteristisk egenskap hos regulatoriskt gennätverk är dess innebo-ende robusthet, det vill säga dess förmåga att bibehålla funktionalitet trotsinförandet av slumpmässiga fel. I den andra delen av denna uppsats fokuserarvi på robustheten hos en speciell typ av Booleska nätverk som kallas Balanse-rade Booleska Nätverk (BBN). Vi formaliserar begreppet robusthet och infören metod för att bygga BBN för 2 -singleton attraktorer Booleska nätverk.Experimentets resultat visar att BBN har förmåga att tolerera enstaka fel.Vår metod förbättrar robustheten läsnings slumpmässigt genererade Booleskanätverk med minst 13% i genomsnitt och i vissa specialfall upp till 61%.

I den tredje delen av denna uppsats fokuserar vi på en speciell typ avsynkrona Booleska nätverk, nämligen Feedback Shift Register (FSR). FSR-baserade filtergeneratorer används som en grundläggande byggsten i mångakryptografiska system, t.ex. strömchiffer. Filtergeneratorer är populära ef-tersom deras väldefinierade matematiska beskrivning möjliggör en detalje-rad formell säkerhetsanalys. Vi visar hur blir en filter generator i modifieradicke-linjärt FSR, snabbare, men något större, än den ursprungliga filterge-neratorn. Exempelvis kan utbredningsfördröjningen minskas 1,54 gånger påbekostnad av 1,27 % extra yta. De presenterade metoderna kan vara viktigaför tillämpningar som kräver mycket höga datahastigheter, t.ex. 5G mobilkommunikationsteknik.

I den fjärde delen av denna avhandling presenterar vi en ny metod för attdetektera och korrigera transienta fel i FSRer med hjälp av duplicering ochparitetskontroll. Periodiskt fel-detektering av funktionella kretsar är mycketviktigt för krypteringssystem eftersom slumpmässiga hårdvarufel kan äventy-ra dess säkerhet. Denna metod är mer pålitlig än Triple Modular Redundancy(TMR) för stora FSRer, men med jämförbar area. Det presenterade tillväga-gångssättet kan vara viktigt för kryptografiska system som använder storaFSRer.

Acknowledgements

First of all, I would like to thank my supervisor, Professor Elena Dubrova, forinspiring me with so many topics and ideas, and especially, for all the patience andencouragement she offered me when I was in trouble.

I would like to thank Professor Zhonghai Lu for reviewing this thesis. I wouldlike to thank Professor Fredrik Jonsson for his help on the Swedish abstract. Iwould like to thank Ms. Alina Munteanu for her help on everything in school. Iwould like to thank all the professors and scholars who teach me, encourage me andenlighten my own research.

I would like to thank all my colleagues and friends, Shaoteng Liu, Li Xie, JueShen, Pei Liu, Shuo Li, Yuan Yao, Xueqian Zhao, Fan Pan, Shao Tao, Nan Liand Shohreh Sharif Mansouri, for the discussions as well as happiness we sharedtogether.

Finally, I would like to thank my parents for their love and support.

Thank you!

Ming LiuStockholm, November, 2015

v

Contents

Contents vii

List of Figures ix

List of Tables x

List of Abbreviations xi

1 Introduction 11.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Overview and Contributions of the Author. . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Background 72.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Boolean Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 Feedback Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4 Relationship between Boolean Networks and FSRs . . . . . . . . . . . . . . . . . 13

3 Multiple-valued Networks 153.1 Multiple-valued Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2 Computation of Attractors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.3 Converting GINML Format to CNET Format . . . . . . . . . . . . . . . . . . . . . . 183.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Balanced Boolean Networks 214.1 Computational Scheme Based on Boolean Networks . . . . . . . . . . . . . . . 214.2 Single Stuck-at Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.3 Robustness Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.4 Balanced Boolean Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Design of Secure FSRs 275.1 Filter Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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viii CONTENTS

5.2 Main Ideas of the Presented Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.3 The Fibonacci to Galois Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305.4 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6 Design of Reliable FSRs 376.1 Stream Ciphers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.2 Transient Faults and Triple Modular Redundancy. . . . . . . . . . . . . . . . . . 386.3 The Duplication and Parity Checking Approach. . . . . . . . . . . . . . . . . . . . 406.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7 Conclusion and Future Work 49

Bibliography 51

Publications

A Finding Attractors in Synchronous Multiple-Valued Networks 59

B The Robustness of Balanced Boolean Networks 61

C A Faster Shift Register Alternative to Filter Generators 63

D A New Approach to Reliable FSRs Design 65

List of Figures

1.1 The structure of the thesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 An example of a direct graph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 An example of a 3-node Boolean network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3 The general structure of an n-stage FSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.4 The relationship between a Boolean network and an FSR. . . . . . . . . . . . . 14

3.1 A 2-node 3-valued network and its STG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2 The flowchart for the conversion procedure.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 An example of a 2-input Boolean logic OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.2 Examples of stuck-at faults in a Boolean network. . . . . . . . . . . . . . . . . . . . . . 234.3 An example of constructing a balanced Boolean network. . . . . . . . . . . . . . 25

5.1 A filter generator composed of an LFSR and a filtering function. . . . . . 285.2 An n-stage NLFSR constructing based on a filter generator. . . . . . . . . . . 295.3 A 4-stage NLFSR in the Fibonacci configuration. . . . . . . . . . . . . . . . . . . . . . . 305.4 An example of the shifting operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.5 An NLFSR constructed from a 256-stage LFSR with fL(x) and fN (x). 33

6.1 Encryption and decryption using a stream cipher. . . . . . . . . . . . . . . . . . . . . . 386.2 The pseudo-random sequence generator of stream ciphers A5/1, E0,

WG-7 and Grain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396.3 The basic configuration of TMR.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.4 The block diagram for an n-stage FSR using TMR.. . . . . . . . . . . . . . . . . . . . 406.5 The block diagram of the duplication and parity checking approach. . 416.6 An example of error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.7 An example of error correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.8 The error-correcting circuit Cec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.9 The reliability of our approach and TMR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456.10 The area overhead of our approach and TMR.. . . . . . . . . . . . . . . . . . . . . . . . . . 47

ix

List of Tables

2.1 The truth table of a Boolean function f(x) = x1 · x2. . . . . . . . . . . . . . . . . . . 8

3.1 A description of the GINML format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2 An example of a multiple-valued network in CNET format. . . . . . . . . . . . 19

4.1 Evaluation of robustness of GRNs and (16, 4)-random Boolean net-works. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1 The statistical tests report for the output sequence OutN . . . . . . . . . . . . . 34

6.1 Area approximation of gates and flip-flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

x

List of Abbreviations

AES Advanced Encryption Standard.ANF Algebraic Normal Form.

BBN Balanced Boolean Network.BLIF Berkeley Logic Interchange Format.

DD Decision Diagram.DNA Deoxyribonucleic Acid.

FSR Feedback Shift Register.

GRN Gene Regulatory Network.

IC Integrated Circuit.

LFSR Linear Feedback Shift Register.

NLFSR Non-Linear Feedback Shift Register.

PRNG Pseudo-Random Number Generator.PRSG Pseudo-Random Sequence Generator.

RAM Random Access Memory.RBN Random Boolean Network.RFID Radio-Frequency Identification.RNA Ribonucleic Acid.

STG State Transition Graph.

TMR Triple Modular Redundancy.

XML eXtensible Markup Language.

xi

Chapter 1

Introduction

Studying biological systems is important for natural sciences. Biological systemsare created by a complex evolutionary process of nature. The unique propertiesof biological systems, such as robustness and adaptability, give us tremendous op-portunities for mimicking the mechanisms of natural evolution in an attempt togenerate software and hardware systems with characteristics comparable to thoseof biological systems. More than 40 years ago, systems biologists began to focustheir research on genetic and cellular systems [10, 26]. This research not only pro-moted the understanding and development of biological systems, but also resultedin many fundamental algorithms and tools for analysis and synthesis of complex net-works in many areas, including Kauffman’s NK model for evolutionary biology [53],self-organization for social networks and computer networks [9, 63], etc.

1.1 Previous Work

In the late 1960s, Boolean networks were proposed by Kauffman as a model ofGene Regulatory Networks (GRNs) [52]. Since then, this model attracted a lotof attention in systems biology [49], evolution [7] and self-organization of complexsystems [53].

Gene regulatory networks represent the fundamental cellular processes in molec-ular entities of living systems, such as proliferation, differentiation and apoptosis,which are controlled by a great amount of molecular actors interacting through avariety of regulatory mechanisms. A GRN is a collection of DNA segments in a cell,called genes, which interact with each other [5]. Each gene contains informationthat determines what the gene does and when the gene is active, or expressed. Whena gene is active a process called transcription takes place, producing a RiboNucleicAcid (RNA) copy of the gene’s information. This piece of RNA then directs thesynthesis of proteins. RNA or protein molecules resulting from the transcriptionprocess are known as gene products. In a Boolean network model, a GRN is rep-resented by a graph composed of nodes (corresponding to genes, proteins and/or

1

2 CHAPTER 1. INTRODUCTION

metabolites) and edges (representing molecular interactions such as protein-DNAand protein-protein, or indirect relationships between genes).

In single-celled organisms, GRNs respond to the external environment, optimis-ing the cell at a given time for survival in this environment. For example, a yeastcell, finding itself in a sugar solution, will turn on genes to make enzymes that pro-cess the sugar to alcohol. By modelling this process using a Boolean network [55],researchers were able to find that a yeast cell makes its living by gaining energy tomultiply, which under normal circumstances enhances its survival prospects. Differ-ent Boolean networks of a yeast cell have been built based on experiments [24, 40].For multi-cellular insects and animals, the same principle has been applied to genecascades that control body-shape [25]. By modelling the gene segmentations andcell cycles using Boolean networks, researchers were able to get a better under-standing of the mechanism of epigenetics [11] by which chromatin modification mayprovide cellular memory by blocking or allowing transcription and finally resultingin a specific type of cells.

Some evidences [51] suggest that cell types (or cell fates) in a GRN of humansand other organisms can be modelled by attractors 1 of a Boolean network. Asa consequence, the analysis of Boolean networks became popular in the researchrelated to genetic diseases [4, 22, 42]. Several tools for Boolean network analy-sis, including GINsim [47], random Boolean networks toolbox [71] for Matlab andDDLab [79] have been developed.

The Boolean networks have also been used to investigate the behaviour of com-plex systems and self-organization phenomenon. Instead of exploring a specific generegulatory system, the study of complex systems explores high-level properties ofrandom Boolean networks. A complex system is defined as a system composedof multiple elements that interact to produce the system’s characteristics and be-haviour [53, 20]. For example, a system may have long attractors (with a largenumber of states), long transients 2 and be unstable, or it may have short attrac-tors, short transients and be stable. Such regimes are known as behavioural regimes.It was demonstrated [78] that the behaviour of any complex system falls into oneof the following three regimes:

• Ordered: In this behavioural regime, a system tends to have single-point orvery short-length attractors, short transients, and dynamic behaviour whichis insensitive to the initial states;

• Complex: In this behavioural regime, a system tends to have short or medium-length attractors, medium length transients, and dynamic behaviour which isrelatively insensitive to the initial states;

1In a Boolean network, an attractor is a cycle in the state transition graph of the network.The formal definition of attractors will be given in Chapter 2.

2The transient length is the time (number of steps) a system needs to reach an attractor.

1.2. OVERVIEW AND CONTRIBUTIONS OF THE AUTHOR 3

• Chaotic: In this behavioural regime, a system tends to have infinite-lengthattractors, long transients, and dynamic behaviour which is very sensitive tothe initial states.

Apart from the number and length of attractors, several other parameters havebeen found to have influence on the system dynamics, including system connectivity,properties of functions associated to the network’s nodes and the structure of thenetwork [6, 61].

Kauffman has analysed the influence of the number of immediate predecessorsk and the type of Boolean functions associated to the nodes on the dynamics ofrandom Boolean networks [52, 54]. He has shown that if Boolean functions areassociated to the nodes at random from the set of all possible Boolean functions ofk variables, then if k ∼ 2, the network is at the borderline between chaos and order;if k is large (of the order of the total number of network’s nodes), the system fallsinto chaotic regime. Kauffman made a hypothesis that the regulatory structuresat the edge of chaos (k ∼ 2) ensure both stability and evolutionary improvements,and these provide the background conditions for an evolution of genetic systems.

1.2 Overview and Contributions of the Author

This thesis is a collection of papers focusing on topics related to Boolean networks.The following papers are included in this thesis:

Paper A Elena Dubrova, Ming Liu, and Maxim Teslenko. Finding attractors in syn-chronous multiple-valued networks using SAT-based bounded model checking.Journal of Multiple-Valued Logic and Soft Computing, 19(1-3):109–131, 2012.

Paper B Ming Liu and Elena Dubrova. The robustness of balanced Boolean net-works. In Ronaldo Menezes, Alexandre Evsukoff, and Marta C. González, edi-tors, Complex Networks, volume 424 of Studies in Computational Intelligence,pages 19–30. Springer Berlin Heidelberg, 2013. ISBN 978-3-642-30286-2.

Paper C Ming Liu, S.S. Mansouri, and E. Dubrova. A faster shift register alter-native to filter generators. In Proceedings of 2013 Euromicro Conference onDigital System Design (DSD), pages 713–718, Sept 2013.

Paper D Ming Liu and Elena Dubrova. A new approach to reliable FSRs design.In Proceedings of 32nd Nordic Microelectronics Conference NORCHIP, Oct2014.

The structure of the thesis is shown in Figure 1.1. The results can be dividedinto two parts.

The first part is about Boolean network analysis. It includes Chapter 3 andChapter 4. In Chapter 3, we calculate and analyse attractors in multiple-valuednetworks. In Chapter 4, we analyse the robustness of a special type of Booleannetworks, called balanced Boolean networks.

4 CHAPTER 1. INTRODUCTION

The second part is about synthesis of a special class of Boolean networks, namelyFeedback Shift Registers (FSRs). It includes Chapter 5 and Chapter 6. In Chapter 5,we address the problem of generating cryptographically strong pseudo-random se-quences using FSRs. In Chapter 6, we show how to design reliable FSRs based ona duplication and parity checking approach.

Boolean networks

Ch. 3 Multiple-valued Networks Ch. 4 Balanced Boolean Networks

Ch. 5 Design of Secure FSRs Ch. 6 Design of Reliable FSRs

Network analysis

Network synthesis

Figure 1.1: The structure of the thesis.

The rest of the thesis is organized as follows.Chapter 2 provides the necessary background on Boolean networks and feedback

shift registers.Chapters 3-6 introduce Paper A, B, C and D, respectively.Chapter 3 introduces Paper A. In Paper A, we present a SAT-based bounded

model checking [13] algorithm for computing attractors in multiple-valued networks.We first extend the SAT-based bounded model checking to the multiple-valued case.Then, we convert network models from GINML format (used as an input to GINsimtool [47]) to CNET format (used as an input in our tool) and run the experimentson multiple-valued network models of real cells. The author’s contribution to thispaper includes the format conversion, experiments and analysis of results.

Chapter 4 introduces Paper B. In Paper B, we introduce a special type ofBoolean networks, called balanced Boolean networks. We first propose a newmeasure of robustness of Boolean networks. Then, we run the robustness testfor random Boolean networks and Boolean networks modelling GRNs of some realcells. Finally, we present an algorithm to transform an arbitrary Boolean networkinto a balanced Boolean network. The author’s contribution to this paper includes

1.2. OVERVIEW AND CONTRIBUTIONS OF THE AUTHOR 5

the definition of robustness, algorithm, the implementation, experiments, analysisof results and writing the paper.

Chapter 5 introduces Paper C. In Paper C, we present a method to transforma structure commonly used in cryptographic applications for generating pseudo-random sequences called filter generator into a Non-Linear Feedback Shift Register(NLFSR). We then use the Fibonacci to Galois transformation of FSRs to reducethe propagation delay. We show that the output sequences are statistically randomvia the NIST tests [69]. The author’s contribution to this paper includes NLFSRsimulation, experiments, analysis of results and writing the paper.

Chapter 6 introduces Paper D and complements it with new results of reliabilityevaluation. In Paper D, we show how to design reliable FSRs using duplication andparity checking. We demonstrate that the presented approach is more reliablethan Triple Modular Redundancy (TMR) for large FSRs, while its area overheadis smaller compared to TMR. The author’s contribution to this paper includesthe duplication and parity checking approach, experiments, analysis of results andwriting the paper.

Chapter 7 summarizes the thesis and suggests the directions for the future work.

Chapter 2

Background

This chapter presents the basic definitions and properties of Boolean networks andfeedback shift registers.

2.1 Notation

Throughout the thesis we use “·” and “∧” for the minimum operation (also calledMIN or, for the two-valued case, AND); “+” and “∨” for the maximum operation(MAX or, for the two-valued case, OR); “⊕” for the addition modulo m operation(XOR for the two-valued case); “ ′” and “ ” for the complement operation (NOT);“↔” for the logic equivalence operation.

We let M := {0, 1, . . . ,m − 1} be a finite set of values. We use lower-caseletters a, b, c, etc to denote elements over M, and lower-case letters f, g, h, etc todenote functions. We use x1, x2, . . . , xn to denote variables of the functions anduse N = {1, 2, . . . , n} to denote the set of indices of these variables. We use boldlower-case letters a,b,x,y, etc for vectors.

Boolean FunctionLet B denote the Boolean domain:

B := {0, 1}.

Definition 1 A Boolean function is a mapping of the form f : Bn → B, where nis the number of the variables.

Let x := (x1, x2, . . . , xn) be a vector of n Boolean variables.

Definition 2 A Boolean function f(x) is linear if there is a vector w ∈ Bn suchthat

f(x) = (w,x) = x1w1 ⊕ x2w2 ⊕ . . .⊕ xnwn.

7

8 CHAPTER 2. BACKGROUND

The set of all linear functions on Bn is denoted by Ln.

Definition 3 The truth table of a Boolean function f(x) is an exhaustive list ofpairs (x, f(x)).

Table 2.1: The truth table of a Boolean function f(x) = x1 · x2.

x1 x2 f(x)0 0 00 1 01 0 01 1 1

Boolean Functions in Algebraic Normal Form

Throughout the thesis, the Boolean functions Bn → B are often represented usingthe Algebraic Normal Form (ANF) which is a polynomial of type

f(x) =2n−1∑i=0

ci · xi11 · xi22 · . . . · xinn ,

where ci ∈ {0, 1} and (i1i2 . . . in) is the binary expansion of i [57].We treat all Boolean functions as n-variable functions of the same variables

x1, x2, . . . , xn. Some functions may not depend on all n variables.

Definition 4 The dependency set of a function f(x), denoted by dep(f), containsall variables on which the function actually depends, i.e.

dep(f) = {i | f(x)|xi=0 6= f(x)|xi=1},

where f(x)|xi=j = f(x1, . . . , xi−1, j, xi+1, . . . , xn) for j ∈ {0, 1}.

Graphs

Definition 5 The pairs (a1, b1) and (a2, b2) are ordered pairs, if

(a1, b1) = (a2, b2) if and only if a1 = a2 and b1 = b2.

Definition 6 A graph is an ordered pair G = (V,E), where V denotes a set ofvertices and E denotes a set of edges. An edge represents a connection between apair of vertices. A graph is directed if its edges are ordered pairs.

2.2. BOOLEAN NETWORKS 9

Definition 7 The immediate predecessor and immediate successor sets of a vertexv ∈ V in a directed graph are defined as ipred(v) = {u | (u, v) ∈ E} and isucc(v) ={u | (v, u) ∈ E}, respectively.

Definition 8 The predecessor set pred(v) of a vertex v ∈ V is a subset of V con-taining all vertices from which v in reachable. Similarly, the successor set succ(v)of a vertex v ∈ V is a subset of V containing all vertices reachable from v.

b

a

c

d e f

g

h

Figure 2.1: An example of a direct graph. The predecessor and successor sets of ver-tex e are pred(e) = {a, b, c, d} and succ(e) = {f, g, h}. The immediate predecessorand immediate successor sets of vertex e are ipred(e) = {d} and isucc(e) = {f}.

2.2 Boolean Networks

Boolean networks were proposed by Kauffman in the late 1960s as a network modelof genetic regulatory networks [52]. In this model, genes are represented by nodesand the regulatory relationships between the genes are represented by edges. Thegene activation is Boolean and other regulatory elements are assumed to be eitheractive or inactive at a given point in time.

Definition 9 A Boolean network is a directed graph consisting of n vertices vi,i ∈ {1, 2, . . . , n}. Each vi has a state variable xi ∈ B which represents the currentstate of vi. The value of each xi is updated according to the updating function oftype fi : Bki → B, where ki is the number of immediate predecessors of vi.

Boolean networks can be updated synchronously or asynchronously [43]. In thisthesis, we only deal with synchronous Boolean networks.


State Transition GraphAt any given point of time t, the state s of a Boolean network is a vector of values ofits state variables x1, x2, . . . , xn. Time is viewed as proceeding in discrete steps. Forthe synchronous type of update, at every time step, the next state of a network,s+, is determined from the current state, s, by updating the values of the statevariables of all vertices simultaneously to the value of the corresponding updatingfunctions fi:

x+i = fi(xi1 , xi2 , . . . , xiki

),

where x+i stands for the next value of xi and xi1 , xi2 , . . . , xiki

are the state variablesassociated with the immediate predecessors of vi.

For all 2n states of an n-node network, there are 2n transitions s→ s+ definedby the updating functions. The State Transition Graph (STG) can be used toillustrate these state transitions. In an STG, vertices represent 2n possible networkstates and edges represent the transitions s→ s+ between the states.

A state transition graph can be described by a transition relation. The charac-teristic formula for the transition relation of a Boolean network is given by [19]:

T (s, s+) =n∧i=1

(x+i ↔ fi(xi1 , xi2 , . . . , xiki

)),

where fi is the updating function associated with vi and xi1 , xi2 , . . . , xikiare state

variables associated with the immediate predecessors of vi.

AttractorsSince a Boolean network is deterministic and finite, any sequence of its consecutivestates eventually converges to either a single state, or a cycle of states, called anattractor.

Definition 10 An attractor is a set of states of a cycle in the STG of a Booleannetwork.

The length of an attractor is the number of states in an attractor. Attractorsof length one are called single-point attractors.

A set of states that will, over time, converge to an attractor is called basins ofattraction of this attractor 1. The larger are the basins, the more likely it is that anetwork starting at a randomly chosen state will end up in the associated attractor.

Definition 11 The basins of attraction of an attractor are the predecessor set ofthe attractor states.

1In some papers, basins of attraction is defined as a set including the attractor states aswell [6, 28].

2.3. FEEDBACK SHIFT REGISTERS 11

x2 + x3 x1x2 + x3

x1x2v1

v2 v3

(a) A 3-node Boolean network.

100

000

111 011

001 101 110

010

A1 A2

(b) Its STG. The states are ordered as(x1x2x3).

Figure 2.2: An example of a 3-node Boolean network.

An example of a 3-node Boolean network and its STG are shown in Figure 2.2(a)and Figure 2.2(b), respectively. In Figure 2.2(a), the 3 nodes of the Boolean networkare v1, v2 and v3; and the updating functions of the 3 nodes are f1 = x1x2, f2 =x2 + x3 and f3 = x1x2 + x3. The arrows indicate the predecessor and successorrelations. Figure 2.2(b) shows its STG, where the 8 vertices represent all 23 networkstates and the edges show the state transitions. Two attractors A1 and A2 for thisBoolean network are shown in yellow (also filled with slashes in a light color) andthe corresponding basins are shown in blue. The attractor A1 = {100} is a singlepoint attractor and its basins are {000}. A2 = {111, 011} is a cyclic attractor oflength 2 and the basins are {001, 101, 010, 110}. The transition relation of thisnetwork is given by:

T (s, s+) = (x+1 ↔ x1x2)(x+

2 ↔ x2 + x3)(x+3 ↔ x1x2 + x3).

2.3 Feedback Shift Registers

An n-stage FSR is a synchronous device consisting of n binary registers, calledstages, connected in a chain [46]. Each stage has a single input and a single output,and it is able to store one bit of information. There are two configurations of FSRs:the Fibonacci configuration and the Galois configuration.

Let xi, xi ∈ B, i ∈ {1, 2, . . . , n} be the state variable representing the value ofthe ith stage in an FSR and fi(x) be the updating function of the ith stage.

Definition 12 An n-stage FSR in the Fibonacci configuration is defined by:


xn xn−1 x2 x1. . .output

g(x1, x2, . . . , xn)

(a) An FSR in the Fibonacci configuration.

gn xn gn−1 xn−1 g1 x1. . .output

. . .. . .

(b) An FSR in the Galois configuration.

Figure 2.3: The general structure of an n-stage FSR in the Fibonacci and the Galoisconfigurations.

f1(x) = x2,f2(x) = x3,

...fn−1(x) = xn,fn(x) = g(x1, ..., xn),

where g is the updating function (also called feedback function).

Definition 13 An n-stage FSR in the Galois configuration is defined by:

f1(x) = g1(x1, x2),f2(x) = g2(x1, x2, x3),

...fn−1(x) = gn−1(x1, x2, . . . , xn),fn(x) = gn(x1, ..., xn),

where gi, i ∈ {1, 2, . . . , n} is the updating function for the ith stage.

Definition 14 If functions f1(x), f2(x), . . . , fn(x) are linear functions, fi(x) ∈Ln, the FSR is called a Linear Feedback Shift Register (LFSR); otherwise, it iscalled an NLFSR.

2.4. RELATIONSHIP BETWEEN BOOLEAN NETWORKS AND FSRS 13

Properties of FSRsLet an FSR consist of n stage registers. Each stage i, i ∈ {1, . . . , n} has a statevariable xi and an updating function fi : Bn → B.

A state of an FSR is a vector of values of its state variables. At each clock cycle,the next state of an FSR is determined from its current state by simultaneouslyupdating the value of each stage i to the value of the corresponding updatingfunction fi, ∀i ∈ {1, . . . , n}.

The period of an FSR is the length of the longest cyclic output sequence itproduces.

The updating functions on a Galois FSR induce the mapping F : Bn → Bn oftype

(x1, x2, . . . , xn)→ (f1(x), f2(x), . . . , fn(x)).

where dep(f1) = {1, 2}, dep(f2) = {1, 2, 3}, . . . , dep(fn) = {1, . . . , n}. If an FSR isbranchless, i.e. its state transition graph consists of pure loops, then the mappingF is invertible [41]. Note that a branchless FSR can be considered as a special caseof invertible multivariate transformations [73].

2.4 Relationship between Boolean Networks and FSRs

We can see a clear similarity between synchronous Boolean networks and FSRs inFigure 2.4. Figure 2.4(a) shows an n-node Boolean network and its correspondingn-stage FSR in the Galois configuration. Figure 2.4(b) shows an example of a 4-node Boolean network and a 4-stage FSR. They have the same STG, which showsin Figure 2.4(c).


g1

x1

g2

x2

g3

x3

gn

xn

. . .

. . . x1 x2 . . . xn

g1(x1, x2). . .gi(x1, . . . , xi, xi+1). . .gn(x1, . . . , xn)

. . .

. . .

(a) A Boolean Network and its corresponding FSR in the Galois configuration.

x2 ⊕ x1 x3

x1x4

x1 x2

x3 x4

x1+x2x3x4output

(b) An example of a 4-node Boolean network and an FSR with the same STG.

0000

0001

1001

110111111110

0111

1010

0101

1011

11000110 0011

1000

0100

0010

(c) The common STG (x1x2x3x4) of the example in (b).

Figure 2.4: The relationship between a Boolean network and an FSR.

Chapter 3

Multiple-valued Networks

Boolean network model is useful in the context of molecular networks [47], thechaos and order analysis of random Boolean networks [14], robustness analysis ofcanalizing Boolean functions for random Boolean networks [54]. However, a Booleannetwork is not sufficient for describing some more complex biological problems. Ifwe use a Boolean network to model a GRN, this Boolean network can only modelgene expressions with two levels: active (logic 1) or repressive (logic 0). In somecases, using more than two values for modelling gene interactions can be moreappropriate [25, 47].

In this chapter, we present a SAT-based bounded model checking algorithmfor finding all attractors in synchronous multiple-valued networks. We first give aformal definition of multiple-valued networks; then a brief explanation of the SAT-based bounded model checking algorithm; and finally, a procedure for convertingnetwork models from GINML format to CNET format. More details about thecomputation of attractors and experimental results can be found in Paper A.

3.1 Multiple-valued Networks

There are many mathematical models of GRNs including Boolean and multiple-valued networks, ordinary and partial differential equations, Petri nets, Bayesiannetworks, stochastic equations, and process calculi [70]. The Boolean and multiple-valued network models have been shown useful for exploring the GRN in the contextof cellular differentiation, cell cycle regulation, immune response, and evolution [8].

A multiple-valued network is a directed graph in which each vertex vi has anassociated state variable xi and an associated multiple-valued function fi [31]. Thestate variable xi ∈ M, M = {0, 1, . . . ,m − 1}, represents the current value of vi.The multiple-valued function fi : Mki → M, where ki is the number of immediatepredecessors of vi, determines how the value of vi is updated.

Similarly to the Boolean case, the state s of a multiple-valued network is avector of values of its state variables x1, x2, . . . , xn. Time is viewed as proceeding

15

16 CHAPTER 3. MULTIPLE-VALUED NETWORKS

in discrete steps. For the synchronous type of update, at every time step, thenext state of a network, s+, is determined from the current state, s, by updatingthe values of the state variables of all vertices simultaneously to the values of thecorresponding updating function fi:

x+i = fi(xi1 , xi2 , . . . , xiki

), (3.1)

where x+i stands for the next value of xi and xi1 , xi2 , . . . , xiki

are the state variablesassociated to the immediate predecessors of vi.

Figure 3.1 shows an example of a 2-node 3-valued network and its STG. Thenode v1 is 3-valued and node v2 is Boolean. The updating functions are f1 = x1 + x2and f2 = x2. As it shows in the STG in Figure 3.1(b), this network has threeattractors A1 = {10}, A2 = {00, 20} and A3 = {11}.

x1 + x2

x2

v1

v2

(a) A 2-node 3-valued network.

00 20 11

01

2110

A1

A3A2

(b) Its STG (x1x2).

Figure 3.1: A 2-node 3-valued network and its STG.

3.2 Computation of Attractors Using SAT-based BoundedModel Checking

Synchronous multiple-valued networks can be considered as a class of deterministicfinite state machines. Any sequence of consecutive states of a network eventuallyconverges to an attractor. Attractors represent the pattern of gene expressions inthe corresponding cell types of the organism being modelled [53, 51]. When theeffect of a disease or a mutation on an organism is studied, attractors have to berecomputed every time a fault is injected in a model.

All algorithms for finding attractors in Boolean and multiple-valued networksface a state-space explosion problem that must be addressed to handle large net-works. Even if the length of attractors is restricted to one, the problem is NP-

3.2. COMPUTATION OF ATTRACTORS 17

hard [3]. The best known algorithm for finding all attractors of length one in aBoolean network with n vertices has the complexity O(1.757n) [76].

Decision Diagrams (DDs) have traditionally been used for representing and ma-nipulating Boolean and multiple-valued functions in network simulation and anal-ysis [2, 38, 33]. Once a DD is constructed for a network, calculations can be donevery efficiently. However, a well-known weakness of DDs is the unpredictability oftheir memory requirements. In the meantime, SAT-based bounded model check-ing [13] can avoid the exponential space blow-up problem by finding an attractorwithout searching through the entire state space.

The algorithm presented in Paper A performs a search within an STG of anetwork without explicitly representing the entire STG as a DD.

In SAT-based bounded model checking, we first generate a multiple-valuedpropositional formula F representing the transition relation T (s, s+) of the network.By applying a SAT-solver to the propositional formula F , a satisfying assignmentcan be found, which corresponds to a valid path in the STG.

Since each state of the STG of a multiple-valued network has a unique nextstate, once a path reaches a loop, it never leaves it. Therefore, we can determinethe presence of a loop simply by checking whether the last state of a path occursat least twice.

Clearly, all states between any two occurrences of the last state belong to aloop. A loop corresponds to an attractor. If a path of length k does exist and itis loop-free, we multiply k by m (m is the depth of the unfolding operation) andcontinue the search for a path of the length k ·m. This is called unfolding operationin Paper A.

For example, T (s, s+) and T (s+, s++) are transition relations representing twopaths of length k = 1. We can unfold the path to length k = 2 by:

T (s, s++) = T (s, s+)T (s+, s++),

where the depth of unfolding operation is m = 2.As an example, consider the 3-valued network in Figure 3.1. We have s =

(x1, x2) and s+ = (x+1 , x

+2 ). The transition relation is given by:

T (s, s+) = (x+1 ↔ x1 + x2)(x+

2 ↔ x2).

In the algorithm, transition relations are represented by multiple-valued propo-sitional formulas [30] using multiple-valued literals i

x, i ∈ {0, 1, . . . ,m − 1}. Forexample x+

1 ↔ x1 + x2 is represented as:

(1x+

1 ↔0x1

1x2 + 1

x10x2 + 1

x11x2)(2

x+1 ↔

0x1

0x2).

For instance, for the example in Figure 3.1, the unfolding by two steps is com-puted as follows:

T (s, s+) = (x+1 ↔ x1 + x2)(x+

2 ↔ x2)T (s+, s++) = (x++

1 ↔ x+1 + x+

2 )(x++2 ↔ x+

2 )


so, the unfolding T (s, s+)T (s+, s++) is:

(x+1 ↔ x1 + x2)(x+

2 ↔ x2)(x++1 ↔ x+

1 + x+2 )(x++

2 ↔ x+2 ).

A possible satisfying assignment for above expression is s = (00), s+ = (20),and s++ = (00). This assignment corresponds to the path 00 → 20 → 00. Asthe state 00 shows up twice, the loop represents the attractor A2 = {00, 20} inFigure 3.1(b).

3.3 Converting GINML Format to CNET Format

In order to test our tool on GRN models of real cells, we converted network modelsfrom GINML format (which is a common input format for specifying Boolean andmultiple-valued networks for GINsim [47]) to the CNET format of our tool.

In GINML format, a network is expressed in terms of node, edge and parame-ter using eXtensible Markup Language (XML) [17]. The element node representsthe vertex in the network, which includes several attributes and subelements suchas basevalue (corresponds to the “based level of expression” of the correspondingcomponent), maxvalue and parameter (corresponds to the user defined updatingrules). The element edge represents the interaction of nodes in the network and isrelated to the element parameter. All these are summarized in Table 3.1.

Table 3.1: A description of the GINML format.

Name Descriptionelement attributegraph nodeorder The vertex order for dis-

play and simulation

nodeid the name of the vertex

basevalue the base level of expres-sion without input, the de-fault value 0

maxvalue the maximum level of ex-pression

edgeid the name of the edge

from the external vertex of thisinteraction

to the affected vertex of thisinteraction

parameter idActiveInteractions the name of the parameterval the value of the parameter

On the other hand, our SAT-based bounded model checking tool reads a networkin CNET format similar to the Berkeley Logic Interchange Format (BLIF) [12] com-

3.4. CONCLUSION 19

monly used in synthesis and verification tools. In CNET format, the line startingwith “.v” specifies the total number of vertices; the line starting with “.n” describesthe vertex information and the updating function of this vertex follows this state-ment; and the line starting with “.f” and “.m” are used to specify the forbiddenstates and multiple-valued vertices for a multiple-valued network. An example ofnetwork in CNET format is showed in Table 3.2

Table 3.2: An example of a multiple-valued network in CNET format.

Example:.v 3.f 311.m 31 2

.n 1 3 1 2 3000 11– 0-1- 0–1 0. . .

Lable Description.v The model has 3 vertices..f The state “11” is forbid-

den for computation..m Vertices ‘1’ and ‘2’ en-

code and represent one 3-valued node.

.n Vertex ‘1’ has 3 imme-diate predecessors, whichare vertices ‘1’, ‘2’ and ‘3’.

The conversion of network model from GINML format to CNET format can bedone as follows:

• Step 1: Read the GINML format, include the vertices information and theupdating functions;

• Step 2: Explore the network vertex by vertex, if current vertex is Boolean,jump to step 4;

• Step 3: Encode the state variable of multiple-valued vertex using dlog2 mebinary bits;

• Step 4: Compute the updating functions and convert them into Booleanexpressions; if all vertices are processed, go to step 5; otherwise jump to step2 to process the next vertex;

• Step 5: Optimise the updating functions of every vertex;• Step 6: Write down the model in CNET format.As we can see, the conversion procedure works for both Boolean and multiple-

valued cases. Its flowchart shows in Figure 3.2.

3.4 Conclusion

This chapter presents an algorithm for finding all attractors in synchronous mul-tiple-valued networks using SAT-based bounded model checking. By analysing


readnetwork

processvertex i

vertex i isBoolean?

encode the stateof multiple-valued vertexusing dlog2 mebinary bits

computeupdatingfunction

optimiseupdatingfunctions

write toCNETformat

no

yes

next

Figure 3.2: The flowchart of the procedure for converting GINML format to CNETformat.

30 network models of real cells, as well as 35 000 randomly generated 4-valuednetworks of sizes between 50 to 300 vertices, we demonstrated that our approachhas a potential to handle an order of magnitude larger networks than the onespossible with existing DD based algorithms.

Chapter 4

Balanced Boolean Networks

Boolean networks have promoted some new concepts and methods related to cir-cuit design including circuits on-line adaptation, fault-tolerant and evolvable hard-ware, etc. Our interest in Boolean networks is due to their attractive fault-tolerantfeatures. The parameters of network can be tuned so that it exhibits a robustbehaviour, in which a minimal change in network’s connections, values of statevariables, or associated functions, typically cause no variation in the network’s dy-namics.

In this chapter, we describe a computational scheme based on Boolean networks.We also define robustness in the context of Boolean networks and apply singlestuck-at fault model for the robustness evaluation. Finally, we introduce BalancedBoolean Networks (BBNs), which are more robust compared to random Booleannetworks. More details about constructing BBNs and experiments can be found inPaper B.

4.1 Computational Scheme Based on Boolean Networks

The following computational scheme based on Boolean networks was introduced byDubrova in [39].

Suppose that we have a Boolean network G with n vertices v1, v2, . . . , vn and mattractors A0, A1, . . . , Am−1. The basins of attraction of Ai’s partition the Booleanspace Bn into m connected components via a dynamic process. Attractors consti-tute stable equilibrium points. We assign a value i, i ∈ {0, 1, . . . ,m − 1} to theattractor Ai and assume that the set of points of the Boolean space correspondingto the states in the basins of attraction of Ai is mapped to i.

Under these assumptions, G defines a function f : Bn → {0, 1, . . . ,m − 1} ofvariables x1, x2, . . . , xn, where the value of the variable xi corresponds to the statevariable of vertex vi. The mapping is unique up to the permutation of m valuesof f . If m = 2, then G represents a Boolean function; otherwise, it represents abinary-valued input m-valued output function.

21

22 CHAPTER 4. BALANCED BOOLEAN NETWORKS

A more formal definition is given below.Let B(Ai) denote the basins of attraction of Ai.

Definition 15 For a Boolean network G with n vertices and m single-point attrac-tors A0, A1, . . . , Am−1. The function fG : Bn → {0, 1, . . . ,m− 1} represented by Gis defined as follows:

fG(x1, . . . , xn) = i, if and only if (x1, . . . , xn) ∈ B(Ai) ∪Ai,

for all (x1, . . . , xn) ∈ Bn and all i ∈ {0, 1, . . . ,m− 1}.

An example of a Boolean network and its STG are shown in Figure 4.1(a) and4.1(b), respectively. This Boolean network has two vertices v1 and v2 with updatingfunctions f1 = x1x

′2 and f2 = x1 + x2, respectively. And there are two attractors

A0 = {00} and A1 = {01}. The initial state {00} terminates in the attractor A0and states {11, 01, 10} terminate in the attractor A1. If we associate A0 with logic 0and A1 with logic 1, the truth table of the resulting Boolean function represented bythis Boolean network is shown in Figure 4.1(c). We see that this Boolean functionis a 2-input Boolean logic OR.

x1x′2 x1 + x2

v1 v2

(a) A Boolean network.

00 01

11

10

A0 A1

(b) Its STG (x1x2).

StateAi function fG(x1, x2)

x1 x20 0 A0 00 1 A1 11 0 A1 11 1 A1 1

(c) The truth table of a function fG repre-sented by the network in (a).

Figure 4.1: An example of a Boolean network representing a 2-input Boolean logicOR.

As it can be seen in the above example, the computational scheme based onBoolean networks use attractors to represent the value of a logic function. As a

4.2. SINGLE STUCK-AT FAULT MODEL 23

result, such a computational scheme inherits the attractive fault-tolerant featuresof Boolean networks. Many experimental results confirm that Boolean networksmodels of real cells are tolerant to faults, i.e. typically the number and length ofattractors are not affected by small changes [8].

4.2 Single Stuck-at Fault Model

In this section, we introduce the single stuck-at fault model, which is the mostwidely used model in testing of digital circuits [48, 1].

Definition 16 A single stuck-at fault is a fault which results in a line in a logiccircuit being permanently stuck at a logic “0” or “1”.

The stuck-at faults are typically abbreviated as “s-a-0” or “s-a-1”.In a similar way, we can define a single stuck-at fault in a Boolean network as

a fault, which causes an edge in a Boolean network to be permanently stuck at alogic value of 0 or 1. It is assumed that the basic functionality of the functionsassociated to the nodes of the Boolean network is not changed by the fault.

x1x′2 x1 + x2

v1 v2

E

s-a-0

01

00 11

10

(a) A stuck-at-0 fault on edge e12.

x1x′2 x1 + x2

v1 v2s-a-0E

00 11

01 10

(b) A stuck-at-0 fault on edge e21.

Figure 4.2: Examples of stuck-at faults in a Boolean network.

For example, in Figure 4.2 the fault s-a-0 on edge e12 changes the state transitiongraph from Figure 4.1(b) to the state transition graph in Figure 4.2(a). The numberof attractors reduces from 2 to 1. As another example in Figure 4.2(b), the fault


s-a-0 on edge e21 just changes the structure of the basins, while the two attractorsremain the same. So, we can say that this fault is tolerated.

4.3 Robustness Evaluation

The capability of a Boolean network to keep the attractors same under the pertur-bations caused by single stuck-at faults can be quantitatively described as follows.

Let G be a Boolean network with n vertices v1, v2, . . . , vn and updating functionsfi : Bn → B, i ∈ {1, . . . , n}. In G, every edge eij carries the value of the statevariable xi of vertex vi, which is also one of the input variables of the Booleanfunction fj(x1, . . . , xi, . . . , xn) associated with vertex vj . Suppose that G has mattractors, A0, A1, . . . , Am−1.

Definition 17 If a single stuck-at fault s-a-0 or s-a-1 occurs on edge eij, it re-sults in xi ≡ 0 or xi ≡ 1 for the Boolean function fj(x1, . . . , xi, . . . , xn). IfA0, A1, . . . , Am−1 are still attractors of the Boolean network with this fault, wesay that Boolean network G tolerates the fault s-a-0 or s-a-1 on eij.

The robustness R of a Boolean network G can be defined as a ratio of toleratedfaults to the total number of faults:

R = NumFT

Numfault,

where NumFT is the number of faults tolerated by G and Numfault is the totalnumber of faults in G.

We run experiments to evaluate robustness of GRNs models of real cells andrandomly generated Boolean network models. The results are shown in Table 4.1.

Table 4.1: Evaluation of robustness of GRNs and (16, 4)-random Boolean networks.

GRNs (16, 4)-random modelsName nodes faults RST Name nodes faults RST

Ap-1 10 32 0.656 Rdm1 16 128 0.016Arabidopsis 15 88 0.352 Rdm2 16 128 0.016

MammalianCell 10 78 0.372 Rdm3 16 128 0BuddingYeast2009 18 120 0.375 Rdm4 16 128 0.078BuddingYeast2004 12 74 0.257 Rdm5 16 128 0.016BY2004Modified 11 58 0.603 Rdm6 16 128 0.023BuddingYeast2008 9 38 0.263 Rdm7 16 128 0DrosophilaCellCycle 14 84 0.655 Rdm8 16 128 0.336

ERBB2 20 102 0.784 Rdm9 16 128 0FissionYeast 10 54 0.167 Rdm10 16 128 0T-cellReceptor 10 78 0.372 Rdm11 16 128 0ThBoolean 40 116 0.379 Rdm12 16 128 0.25

All 12 GRNs are models of real cells taken from [36], and (16, 4)-random Booleannetworks are networks with 16 nodes and each having 4 immediate predecessors

4.4. BALANCED BOOLEAN NETWORKS 25

selected at random, which are generated by our program. As the results show,GRNs models of real cells are more robust than random Boolean networks. Nextwe show how to improve the robustness of random Boolean networks.

4.4 Balanced Boolean Networks

Balancedness is a useful and important feature of many systems. For example, incircuits, a balanced design means smaller power consumption, smaller propagationdelay and convenient circuit testing [21, 74, 77]. In a Boolean network, “balanced-ness” means that every attractor has nearly the same size of basins in its STG.

As it is presented in Paper B, an n-node Boolean network can be made balancedby adding one additional node vn+1. The updating functions fi, i ∈ {1, 2, . . . , n}of the original network are changed to f?i according to the equation:

f?i ={fi , if fi = 0 , or 1xn+1 ⊕ f?n+1 ⊕ fi , otherwise. (4.1)

where 0 and 1 mean constant 0 and constant 1, respectively, and f?n+1 is the updat-ing function of the additional node vn+1, selected from the set f?n+1 ∈ {0,1, xn+1⊕fG, x

′n+1 ⊕ fG}, where fG is the function represented by the original Boolean net-

work according to Definition 15.

x1x2 1

v1 v2

01 11

00 10

x1x2 ⊕ x3 1

0

v1 v2

v3

010 110

111000

100 101001

011

f?3 = 0

Figure 4.3: An example of constructing a balanced Boolean network.

A balanced Boolean network can be constructed as shown in Figure 4.3. Theupdating function of the additional node is f?3 = 0. The balancing of the basins im-


proves robustness from 0.25 to 0.333, i.e. by 33.3%. More results on the evaluationof robustness of balanced Boolean networks can be found in Paper B.

4.5 Conclusion

This chapter describes a computational scheme based on Boolean networks anddefines the robustness in the context of Boolean networks. We introduce a spe-cial type of Boolean networks, called balanced Boolean networks and present analgorithm to transform an arbitrary Boolean network into a BBN. The experimentresults show that balanced Boolean networks have higher robustness than randomBoolean networks.

Chapter 5

Design of CryptographicallyStrong FSR-based Pseudo-randomSequence Generators

Cryptographically strong pseudo-random sequences play important role in cryp-tography. FSR-based filter generators [23] are a popular primitive for generatingpseudo-random sequences, which are used as a basic building block in many streamciphers. Filter generators are popular because their well-defined mathematical de-scription enables a detailed formal security analysis.

In this chapter, we show how to reduce the propagation delay of a filter gen-erator without compromising its security by converting a filter generator into anNLFSR, which is faster, but slightly larger, than the original filter generator. Weshow that the NLFSR generates an equivalent set of output sequences as the filtergenerator and that its period is 2n − 1, where n is the size of the NLFSR state.The propagation delay is considerably reduced while the output sequence retainsthe required statistical properties.

5.1 Filter Generators

Filter generators became popular cryptographic primitive ever since the weaknessof LFSRs has been discovered in the 1970s [64]. As the name suggests, a filtergenerator uses a function to “filter” an LFSR sequence or several LFSR sequences,resulting in a cryptographically stronger pseudo-random sequence. Figure 5.1 showsa filter generator composed of an LFSR and a filtering function.

It is known how to make design choices for the size of internal state, the LFSRpolynomial, and the Boolean function (number and position of inputs, nonlinearity,resiliency, algebraic degree, etc) so that the resulting filter generator resists knownattacks (e.g. distinguishing, correlation, algebraic, etc) with a sufficient security

27

28 CHAPTER 5. DESIGN OF SECURE FSRS

LFSR fout

Figure 5.1: A filter generator composed of an LFSR and a filtering function.

margin [44, 16]. The filtering function is typically constructed as:

f = fN (x)⊕ fL(x),

where fN (x) is a nonlinear part, which adds resistance to linear approximationattacks and algebraic attacks and fL(x) is a linear part, which adds high resiliency.

Bent Functions

Bent functions, which have the highest nonlinearity 2n−1 − 2n/2−1, have been in-troduced by Rothaus in [68].

Definition 18 For an n-variable Boolean function f(x), the Walsh-Hadamard trans-formation Ff : Bn → R of f , is defined as

Ff (w) =∑

x∈Bn

f(x) · (−1)(w,x),

where R is the set of all real numbers and w is a vector w ∈ Bn.

Definition 19 A Boolean function f is called a bent function if∣∣∣Ff (w)∣∣∣ = 2 n

2

holds for any w ∈ Bn.

In the approach presented in Paper C, we use bent functions with dep(fB) =k = 2m, of type

fN (x) = xi1xim+1 ⊕ . . .⊕ ximxik ⊕ fA(xi1 , xi2 , . . . , xim), (5.1)

where ij ∈ {1, 2, . . . , n}, ∀j ∈ {1, 2, . . . , k} and fA is an AND of p arbitraryvariables from the set {xi1 , xi2 , . . . , xim} for 3 ≤ p ≤ m. A proof that functions oftype 5.1 are bent can be found in [65].

5.2. MAIN IDEAS OF THE PRESENTED APPROACH 29

Shift Register1+ + Shift Register2

fL

fsN

fN

output

Figure 5.2: An n-stage NLFSR generating the same set of output sequences as afilter generator based on an n-stage LFSR with the feedback function fL(X) andthe filtering function fN (X)⊕ fL(X); fsN (X) is a shifted copy of fN (X).

Linear Functions

A linear function fL(x) with dep(fL) = r is of type:

fL(x) = xj1 ⊕ xj2 ⊕ . . .⊕ xjr,

where ji ∈ {0, 1, . . . , n − 1},∀i ∈ {1, 2 . . . , r}, and dep(fL) = r, such that thepolynomial of degree n in GF (2) of type

g(x) = xj1 + xj2 + . . .+ xjr + xn

is primitive 1.To summarize, the filtering functions in our approach is in the form:

f(x) = xi1xim+1 ⊕ . . .⊕ ximxik ⊕ xj1 ⊕ xj2 ⊕ . . .⊕ xjr⊕ fA(xi1 , xi2 , . . . , xim).

5.2 Main Ideas of the Presented Approach

The main ideas behind the presented approach are:

• Structural change from LFSR to NLFSRInspired by [35], we construct an n-stage NLFSR with a guaranteed largeperiod of 2n − 1 by adding to a maximum period LFSR two copies of a non-linear function, fN and fsN , as shown in Figure 5.2.

1An irreducible polynomial of degree n is called primitive if the smallest m for which it dividesxm + 1 is equal to 2n − 1 [46].


• Reducing the propagation delayAs shown in Figure 5.2, the propagation delay of the NLFSR is determinedby the LFSR function fL and the two non-linear Boolean functions fN andfsN . To reduce the propagation delay, we apply the Fibonacci to Galois trans-formation [32].

• Cryptographic securitySeveral factors can influence the cryptographic strength of pseudo-randomsequences. We need to carefully select LFSR polynomial and parameters ofthe NLFSR updating function such as nonlinearity, resiliency and algebraicdegree [16]. The details are presented in Paper C.

5.3 The Fibonacci to Galois Transformation

As we mentioned in Chapter 2, there are two ways to implement a feedback shiftregister: in the Fibonacci configuration, or in the Galois configuration.

In the Fibonacci configuration, all updating functions except fn−1 are of typefi(x) = xi+1, for i ∈ {0, . . . , n− 2} 2. In other words, the feedback connections areonly applied to the input stage of the shift register. In the Galois configuration,the feedback connections are potentially applied to every stage. The difference isobvious; the Galois configuration is faster than the Fibonacci configuration, as thefeedback computations are performed in parallel. Figure 5.3 shows a 4-stage NLFSRin the Fibonacci configuration with the feedback function f3 = x0⊕x1⊕x2⊕x1x2.

x0x1x2x3output

AND

+++

Figure 5.3: A 4-stage NLFSR in the Fibonacci configuration.

The transformation of an FSR from the Fibonacci to an equivalent Galois con-figuration can be done by subsequently applying shifting operations [32]. Theupdating function f should be in the algebraic normal form (see in Chapter 2 forthe definition of Boolean functions in ANF).

An n-stage NLFSR is called uniform [32] if, for some 0 ≤ τ ≤ n− 1:

∀i ∈ {0, 1, . . . , τ − 1} : fi(x) = xi+1

∀i ∈ {τ, τ + 1, . . . , n− 1} : fi(x) = xi⊕1 + hi(x)

2In this chapter, the indices of stages of FSRs start from 0 to keep agreement with the notationsand definitions in paper [32].

5.4. EXAMPLE 31

where dep(hi) ⊆ {0, 1, . . . , τ} − {xi⊕1} and “⊕” denotes addition modulo n. Thestage τ is called the terminal stage of the NLFSR.

Two NLFSRs are considered equivalent if sets of their output sequences areequal.

Theorem 1 Given a uniform NLFSR with the terminal stage τ , a shifting fτM→ fτ ′

results in an equivalent NLFSR if the transformed NLFSR is uniform as well.

Let fa(x) and fb(x) be the updating functions of the stages a and b of an n-stageNLFSR, respectively, such that a > b.

Definition 20 The operation shifting, denoted by faP−→ fb, moves a set of product-

terms P from the ANF of fa to the ANF of fb. The index of each variable xi ofeach product-term in P is changed to x(i−a+b) mod n.

An example of the shifting operation of f3x1x2−−−→ f2 for the 4-stage NLFSR in

the Galois configuration is shown in Figure 5.4.

x0x1x2x3output

AND

+++

f3 = x0 ⊕ x1 ⊕ x2 ⊕ x1x2f2 = x3

x0x1x2+x3output

AND

++

f3 = x0 ⊕ x1 ⊕ x2f2 = x3 ⊕ x0x1

shifting operation: f3 f2{x1x2}

Figure 5.4: An example of the shifting operation.

5.4 Example

Consider an NLFSR constructed from a 256-stage LFSR and a bent function. Fol-lowing recommendations of [16], we select k = 12, p = 3 and r = 6. A possible


choice of fL(x) and fN (x) which stasifies the above parameters is:

fL(x) = x0 + x12 + x48 + x115 + x133 + x213

corresponding to the primitive polynomial of 256 [81]:

g(x) = 1 + x12 + x48 + x115 + x133 + x213 + x256

and

fN = x30x70 ⊕ x31x71 ⊕ x32x72 ⊕ x34x74 ⊕ x36x76 ⊕ x40x80 ⊕ x30x32x36.

By using the approach presented in Paper C, we obtain the Galois NLFSRshown in Figure 5.5. As it shows, the FSR partitions into three parts: FSR1, FSR2and FSR3.

The NLFSR in Figure 5.5 can generate two output sequences OutN and OutL.OutN comes from the output of the stage 244 (which is a non-linear sequence) andOutL comes from the output of the stage 0 (which is a linear sequence.)

Since the period of the NLFSR is very large, 2256 − 1, we can only evaluateits output sequences for a limited number of sample data. In our experiment, wegenerate 1 000 000 samples from the NLFSR and these samples are divided into 20sub-sequences in the NIST statistical tests [69]. Every test is based on 1 000 000samples and each test is repeated 20 times to complete the final result. Table 5.1shows the statistical test report generated by the NIST test suite for the outputsequence OutN . As we can see from the table, the NLFSR-based filter generatorhas excellent statistical properties.

NIST TestThe NIST test suite [69] was developed by the National Institute of Standards andTechnology of US. It was used for choosing today’s Advanced Encryption Standard(AES) [66]. It is a helpful tool to evaluate statistical properties of Pseudo-RandomNumber Generators (PRNGs). In this section, we describe statistical tests that weused for evaluating our approach.

The statistical package sts-2.1.1 includes 15 statistical tests. For each test, thesuite first applies a procedure to find the statistical value of chi-square variation χ2,a particular parameter for the given sequence, which is obtained from the theoreticalstudies of an identical sequence under the assumption of randomness. Then, thetest suite transforms the χ2 data to a randomness probability data, called “P-value”.

The theoretical models of each test are documented in the manual and specifi-cation [69]. The following is a brief list of the 15 statistic tests:

• The Frequency (Monobit) Test can determine whether the number of onesand zeroes in a sequence are approximately the same as in a truly randomsequence;

• Frequency Test within a Block can determine whether the frequency ofones in an M -bit block is approximately M/2;

5.4. EXAMPLE 33

FSR

1FS

R2

FSR

3OutL

OutN

+

+

+

+

+

+

x25

5

x24

4

x25

4x

253 x25

2x

251

x24

6x

245

x25

0...

x24

7

AN

D

AN

Dx

0

x11

x45

x11

0

x12

4

x20

2x

30

x70

x30

x32x

36+

+

+

+

+

+

x24

3

x23

2

x24

2x

241 x24

0x

239

x23

4x

233

x23

8...

x23

5

AN

D

AN

Dx

244

x18

x58

x18

x20x

24

Figu

re5.5:

AnNLF

SRconstruc

tedfrom

a25

6-stageLF

SRwith

f L(x

)an

df N

(x).


Table 5.1: The statistical tests report for the output sequence OutN .

P-VALUE PROPORTION STATISTICAL TEST0.534146 20/20 Frequency0.213309 20/20 BlockFrequency0.911413 19/20 CumulativeSums0.122325 20/20 Runs0.534146 20/20 LongestRun0.048716 20/20 Rank0.437274 20/20 FFT0.911413 20/20 NonOverlappingTemplate0.275709 20/20 OverlappingTemplate0.637119 20/20 Universal0.437274 20/20 ApproximateEntropy0.534146 12/12 RandomExcursions0.350485 12/12 RandomExcursionsVariant0.739918 20/20 Serial0.437274 20/20 LinearComplexity

• The Runs Test can determine whether the oscillation between various zeroesand ones is too fast or too slow;

• Tests for the Longest-Run-of-Ones in a Block can determine whetherthe length of the longest run of ones within the tested sequence is consistentwith a random sequence;

• The Binary Matrix Rank Test can check for linear dependence amongfixed length sub-strings of the original sequence;

• The Discrete Fourier Transform (Spectral) Test detects periodic fea-tures (i.e., repetitive patterns that are near each other) in the tested sequence;

• The Non-overlapping Template Matching Test checks the occurrencesof a given non-periodic (aperiodic) pattern;

• The Overlapping Template Matching Test checks the occurrences ofpre-specified target strings;

• Maurer’s “Universal Statistical” Test detects whether or not the se-quence can be significantly compressed without loss of information;

• The Linear Complexity Test determines whether or not the sequence iscomplex enough to be considered random;

• The Serial Test checks if the occurrences of the 2m m-bit overlapping pat-terns are approximately the same as a random sequence;

• The Approximate Entropy Test compares the frequency of overlappingblocks of two consecutive/adjacent lengths (m andm+1) against the expectedresult for a random sequence;

• The Cumulative Sums (Cusums) Test determines whether the cumula-

5.5. CONCLUSION 35

tive sum of the partial sequences occurring in the tested sequence is too largeor too small relative to the expected behaviour of that cumulative sum forrandom sequences;

• The Random Excursions Test determines if the number of visits to aparticular state within a cycle deviates from what one would expect for arandom sequence;

• The Random Excursions Variant Test detects deviations from the ex-pected number of visits to various states in the random walk.

5.5 Conclusion

This chapter presents a new technique for increasing the throughout of filter genera-tors. We first convert a filter generator into an NLFSR that generates an equivalentset of output sequences as the filter generator. Then, we reduce the propagationdelay of the NLFSR by redistributing monomials of its feedback functions. The pre-sented approach might be useful for applications that require very high data rates,e.g. 5G mobile communication technology. Some cryptographic systems based onthe presented approach have been already designed, e.g. Espresso stream cipherpresented in [29].

Chapter 6

Design of Reliable FSRs

The continuing rising of circuit density and the reduction of device sizes cause alot of new constraints and problems in Integrated Circuit (IC) design. One of theserious consequences of these changes is the reduction of circuit reliability.

In this chapter, we introduce a new approach for reliability improvement ofFSRs, which are the key component of stream ciphers. We present a methodfor detecting and correcting transient faults in FSRs based on duplication andparity checking. Periodic fault detection of functional circuits is very importantfor cryptographic systems because a random hardware fault can compromise theirsecurity. For example, if the output of a Pseudo-Random Sequence Generator(PRSG) contained in a stream cipher gets stuck to 0, then the stream cipher will besending messages unencrypted. The presented method is more reliable than TMRfor large FSRs, while the area overhead of the two approaches are comparable.The presented approach might be important for cryptographic systems using largeFSRs.

6.1 Stream Ciphers

Stream ciphers are widely used in modern cryptographic systems. The block dia-gram of a stream cipher is shown in Figure 6.1.

The main building block of a stream cipher is a cryptographically strong pseudo-random sequence generator. Key and IV represent the secret key and the initial-ization value for the PRSG, which are used to make the initial conditions of thePRSG more difficult for an attacker to guess. To encrypt, the plain text is added(typically using a bitwise XOR) with the key stream generated by the PRSG. Todecrypt, the reverse operation is performed.

The pseudo-random sequence generator is usually based on LFSRs or NLFSRs,not only for the good statistical properties of sequences they produce, but alsofor the simplicity and speed of their hardware implementation. Figure 6.2 showsthe block diagrams of PRSG used in several stream ciphers: A5/1 (used for global

37

38 CHAPTER 6. DESIGN OF RELIABLE FSRS

Plain text Cipher text+

PRSG

Key Stream

KeyIV

(a) Encryption

Cipher text Plain text+

PRSG

Key Stream

KeyIV

(b) Decryption

Figure 6.1: Encryption and decryption using a stream cipher.

system for mobile communications [67, 45]), E0 (used for Bluetooth communica-tions [15]), WG-7 stream cipher (used for RFID [62]) and Grain cipher [50].

6.2 Transient Faults and Triple Modular Redundancy

Hardware faults can be classified into two major classes [34]:

• A permanent fault remains active until a corrective action is taken. Thesefaults are usually caused by physical defects in the hardware such as shortsin the circuit, broken interconnections, or stuck cells in a memory;

• A transient fault (also called soft-error [80]) remains active for a short periodof time, which can only be detected by online detection or concurrent checkingand not by off-line testing.

Transient faults are the dominant type of faults in today’s ICs. For example,about 98% of Random Access Memories (RAM) faults are transient faults [75].

For reliable circuit design, TMR is a common form of hardware redundancy. Thebasic configuration shows in Figure 6.3. The modules are triplicated to performthe same computation in parallel. Majority voting is used to determine the correctresult. If one of the modules fails, the majority voter masks the fault by recognizingas correct the result of the remaining two fault-free modules. It is well known thatthe reliability of TMR can be calculated as [34]:

RTMR = (3R2m − 2R3

m)Rv,

where Rm is the reliability of a module and Rv is the reliability of the voter.We apply TMR to an n-stage FSR as shown in Figure 6.4. we triplicate register

stages and the feedback function.Suppose every register stage has the reliability Rm = p and the voter is 100%

reliable, then, the reliability of FSR in Figure 6.4 is

Rtmr = (3p2 − 2p3)n. (6.1)

6.2. TRANSIENT FAULTS AND TRIPLE MODULAR REDUNDANCY 39

0125. . .10. . .18

+++

01. . .11. . .21

+

012. . .12. . .15. . .22

+++

+

(a) A5/1 stream cipher

LFSR1

LFSR2

LFSR3

LFSR4

Add

Blender +

MSB LSB

(b) E0 stream cipher

01. . .11. . .2122

β+

WG

(c) WG-7 stream cipher

+NFSR LFSR

h(x)

+

g(x) f(x)

(d) Grain cipher

Figure 6.2: The pseudo-random sequence generator of stream ciphers A5/1, E0,WG-7 and Grain.


Module 1

Module 2

Module 3

Voter

input 1

input 2

input 3

output

Figure 6.3: The basic configuration of TMR.

VoterVoterVoterVoter y1

x1

z1

yn−1

xn−1

zn−1

yn

xn

zn

. . .

ffb(z1, z2, . . . , zn)

ffb(y1, y2, . . . , yn)

ffb(x1, x2, . . . , xn)

out

Figure 6.4: The block diagram for an n-stage FSR using TMR.

The area overhead of TMR in Figure 6.4 is

Atmr = 3(n-stage FSR + ffb) + n×Voter. (6.2)

6.3 The Duplication and Parity Checking Approach

Our approach is based on an observation that storage elements (e.g. registers, mem-ory) are more sensitive to transient faults than combinational logic elements [56, 27].In our reliability evaluation, we assume that the transient faults in combinationallogic circuits will propagate to one of the register stages within one clock cycle, i.e.they will manifest themselves as errors in the values of register stages. Therefore,in our evaluation we consider transient faults in register stages only. Voters anderror correcting circuits are assumed to be perfect.

The block diagram of the presented duplication and parity checking approachshows in Figure 6.5. The output Out represents the output sequence and theoutput Error indicates the working status of the circuit (Error = 1 means circuit

6.3. THE DUPLICATION AND PARITY CHECKING APPROACH 41

has failed). In Figure 6.5, we duplicate the FSRs (Fx and Fy) and, when an erroris detected, the error-correcting circuit (Cec) is activated to correct it.

FSR Fx

Cec

FSR Fy

Out

Error

ex

outx

ey

outy

Figure 6.5: The block diagram of the duplication and parity checking approach.

Error DetectionWe use even parity code to detect faults in the FSRs Fx and Fy. The even paritycode of length n consists of all binary n-tuples that contain an even number of 1’s.Typically, the first n − 1 bits of a codeword are data carrying information, whilethe last bit is the check bit, determining the parity of the codeword [34].

Let us consider a 5-stage FSR with feedback function ffb as an example toexplain how to detect an error by the parity checking method. In Figure 6.6, xi,i ∈ {1, 2, . . . , 5} represents the state of the ith stage and xpc represents the checkbit.

At any time t, the check for errors is done by using equation

ex = x1(t)⊕ x2(t)⊕ x3(t)⊕ x4(t)⊕ x5(t)⊕ xpc(t), (6.3)

where ex is the error checking result (ex = 1 represents that an odd number ofstages in the FSR are affected by faults).

Since FSRs in the Fibonacci configuration has the property that

xi(t+ 1) = xi+1(t), i ∈ {1, 2, . . . , n− 1},

the parity bit xpc(t+ 1) can be predicted at time t using the equation

xpc(t+ 1) = x2(t)⊕ x3(t)⊕ x4(t)⊕ x5(t)⊕ ffb(t). (6.4)

As the above equations show, we can check for errors and predict the parity bitat the same time. We also see that the error-checking Equation (6.3) and parity-predicting Equation (6.4) share parts of XOR terms. At any time t, if an oddnumber of stages in the FSR are affected by faults, the error checking signal ex willbe 1 to indicate the presence of this error.


x1x2x3x4x5

++++

+ xpc

ffb

+ex

Outx

(a) A 5-stage FSR with error detection.

0x1

1x2

1x3

0x4

1x5

1

xpc

ex = x1 ⊕ x2 ⊕ x3 ⊕ x4 ⊕ x5 ⊕ xpc = 0Correct case:

0x1

0x2

1x3

0x4

1x5

1

xpc

ex = x1 ⊕ x2 ⊕ x3 ⊕ x4 ⊕ x5 ⊕ xpc = 1Error case: 0(b) Error detection.

Figure 6.6: An example of error detection.

Error Correction

When an error is detected by the error-detecting circuit, the error signals ex and eyactivate the error-correcting circuit Cec. In Figure 6.7, a fault in y2 can be detectedand corrected to the value of x2.

0x1

1x2

1x3

0x4

1x5

1

xpc

ex = x1 ⊕ x2 ⊕ x3 ⊕ x4 ⊕ x5 ⊕ xpc = 0

0y1

0y2

1y3

0y4

1y5

1ypc

ey = y1 ⊕ y2 ⊕ y3 ⊕ y4 ⊕ y5 ⊕ ypc = 10

Figure 6.7: An example of error correction.

The error-correcting circuit works as shown in Table 6.8(a). After simplification,the circuit Cec for every register stage is shown in Figure 6.8(b). It should be noticedthat when Fx and Fy are both in error condition, the error signal Error will beactivated to prevent the propagation of errors.


Error detection Function of circuit Cecex ey0 0 no error0 1 correcting value of Fy to Fx1 0 correcting value of Fx to Fy1 1 error signal Error = 1

(a) The function of the error-correcting circuit Cec.

1

MUX

0

AND

AND

xi

yi

xi−1

yi−1

Error

ex

ey

(b) The error-correcting circuit for everyregister stage.

Figure 6.8: The error-correcting circuit Cec.

Reliability EvaluationIn our duplication and parity checking approach, we use parity checking for errordetection to indicate the working status of the circuit in real-time. We define thework of FSR as reliable if one of the following conditions holds:

• Case 1: Both Fx and Fy have no error. The output sequence is correct;

• Case 2: An odd number of stages in Fx are affected by faults and Fy has noerror. The faults in Fx will be corrected by the error-correcting circuit andthe output sequence will be correct;

• Case 3: An odd number of stages in Fy are affected by faults and Fx has noerror. The faults in Fy will be corrected by the error-correcting circuit andthe output sequence will be correct;

• Case 4: Both Fx and Fy have an odd number of stages affected by faults.The faults will be detected by the error-correcting circuit.

In the traditional dependability evaluation, the last case is called a “failed safe”state [34]. In this state, the circuit is not capable of producing a correct output any


longer, but the error is detected and reported, so corrective actions can be takento recover from the error.

Theorem 2 The reliability of the duplication and parity checking approach for ann-stage FSR is

Rdpc = (pn+1 + 1− (2p− 1)n+1

2 )2, (6.5)

where p is the reliability of every register stage in the FSR.

Proof: The reliability of the duplication and parity checking approach for an n-stage FSR is calculated by equation

Rdpc = P 2correct + 2PcorrectPodd + P 2

odd = (Pcorrect + Podd)2,

where P 2correct is the probability that both FSRs work correctly, PcorrectPodd is the

probability that one FSR works correctly and another one has an odd number offaults (two cases), and P 2

odd is the probability that both FSRs have an odd numberof faults.

Since Pcorrect is the probability that one FSR works correctly, which means n+1registers are reliable, it is given by pn+1. Since Podd is the probability that one FSRencounters an odd number of faults, which means an odd number of stages in theFSR are affected by faults, it is given by

Podd =bn/2c∑m=0

(n+ 1

2m+ 1

)pn−2m(1− p)2m+1. (6.6)

Next we derive a closed formula for Equation (6.6). According to the binomialtheorem [18], it is possible to expand (x+ y)n into a sum of the form

(x+ y)n =(n

0

)xny0 +

(n

1

)xn−1y1 + . . .+

(n

n

)x0yn =

n∑k=0

(n

k

)xn−kyk (6.7)

where each(nk

)is a specific positive integer known as a binomial coefficient.

Similarly, (x− y)n expands into

(x− y)n =(n

0

)xny0 −

(n

1

)xn−1y1 + . . .+

(n

n

)x0(−y)n =

n∑k=0

(n

k

)xn−k(−y)k.

(6.8)By subtracting Equation (6.8) from Equation (6.7), we get

(x+ y)n − (x− y)n = 2b(n−1)/2c∑m=0

(n

2m+ 1

)xn−2m−1y2m+1.


The sum of the odd index terms in Equation (6.7) is

b(n−1)/2c∑m=0

(n

2m+ 1

)xn−2m−1y2m+1 = (x+ y)n − (x− y)n

2 . (6.9)

The probability of Podd is calculated by Podd = 1−(2p−1)n+1

2 .Therefore,

Rdpc = (pn+1 + 1− (2p− 1)n+1

2 )2.

�

According to Equation (6.1) and Equation (6.5), Figure 6.9 shows the reliabilitycomparison for our approach and TMR. We see that our duplication and paritychecking approach is more reliable than TMR for large FSRs.

ReliabilityR

-0.2

0

0.2

0.4

0.6

0.8

1

Number of stages of an FSR0 200 400 600 800

Original n-stage FSRFSR using TMRFSR using parity

Figure 6.9: The reliability of our approach and TMR, where the reliability of everyregister stage is p = 0.968 [72].

Area Overhead EvaluationThe area overhead is calculated based on the area approximation of gates andflip-flops shown in Table 6.1.


Table 6.1: Area approximation of gates and flip-flops.

Gate Area2-input AND 12-input XOR 2

flip-flop 4

The area overhead of the duplication and parity checking approach for an n-stage FSR is

Adpc = 2(n-stage FSR + ffb + parity bit) +Adetection +Acorrection,

where Adetection is the area overhead of the error-detecting circuit and Acorrectionis the area overhead of the error-correcting circuit.

In error-detecting circuit, error-checking needs n × 2-input XOR and parity-predicting needs (n−1)×2-input XOR. However, if we take into account the n−1overlap XOR terms, the area overhead of the error-detecting circuit reduces to

Adetection = (n+ 1)× 2-input XOR = (2n+ 2)× 2-input AND.

In error-correcting circuit, every stage needs a 2-input MUX (6×2-input AND),the area overhead of error-correcting circuit is

Acorrection = (n+ 1)×MUX + 2× 2-input AND = (6n+ 8)× 2-input AND.

The feedback function is usually small, less than n gates, which we approximateas n× 2-input AND.

Finally, the area overhead of the duplication and parity checking approach foran n-stage FSR is

Adpc = (18n+ 18)× 2-input AND.

Similarly, one voter needs 5× 2-input AND.The area overhead for an FSR using TMR according to Equation (6.2) is

Atmr = 20n× 2-input AND.

Our approach has a smaller area overhead compared to TMR, as it shows inFigure 6.10, which is about 10% smaller than TMR on average.

6.4 Conclusion

In this chapter, we present an approach for designing reliable FSRs using the dupli-cation and parity checking. We demonstrate that the presented approach is morereliable than TMR for large FSRs, while its area overhead is smaller than TMR.

6.4. CONCLUSION 47

Areaoverhe

ad(2-inp

utAND)

0

5,000

1e+04

1.5e+04

2e+04

Number of stages of an FSR0 200 400 600 800

FSR using parityFSR using TMR

Figure 6.10: The area overhead of our approach and TMR.

Chapter 7

Conclusion and Future Work

The contributions of this thesis can be partitioned into two parts.

• In network analysis, we calculated and analysed the number of attractors inmultiple-valued networks using a SAT-based bounded model checking algo-rithm. The presented algorithm can handle larger networks and computeattractors much faster than other tools based on DDs. We also analysedthe robustness of Boolean networks based on the stuck-at fault model andshowed how to construct balanced Boolean networks, which are more robustthan random Boolean networks.

• In network synthesis, we transformed a filter generator to an NLFSR usingGalois shifting operation. The results showed that the propagation delay islargely reduced and the output sequence has good statistical properties. Wealso presented an approach for designing reliable FSRs. The results showedthat our duplication and parity checking approach is more reliable than TMRfor large FSRs, while having a smaller area overhead.

The results presented so far lead to several directions for the future work.

• During our research, we found that there is a lot of similarities betweenBoolean networks and FSRs, which are key components for many crypto-graphic systems. One interesting idea is to make use of the accumulatedknowledge about network dynamics of Boolean networks in the chaotic regimeto construct NLFSRs with full-length cyclic attractors.

• As we known, in many random Boolean networks, a minor discrepancy ofnetwork parameters or functions may result in a totally different networkcharacteristics, such as changes of attractor states, network dynamics and be-havioural regime. However, there are some Boolean networks that can keepnetwork characteristics stable under these small changes. In our research, we

49

50 CHAPTER 7. CONCLUSION AND FUTURE WORK

found that balanced Boolean networks are capable to preserve attractors un-der functional changes. More work needs to be done to make use of interestingpotential of Boolean networks to tolerate faults.

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Appendix A

Finding Attractors in SynchronousMultiple-Valued Networks UsingSAT-based Bounded ModelChecking

• Elena Dubrova, Maxim Teslenko, and Ming Liu. Finding attractors in syn-chronous multiple-valued networks using SAT-based bounded model checking.In 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL2010, Barcelona, Spain, 26-28 May 2010, pages 144–149, 2010

• Elena Dubrova, Ming Liu, and Maxim Teslenko. Finding attractors in syn-chronous multiple-valued networks using SAT-based bounded model checking.Journal of Multiple-Valued Logic and Soft Computing, 19(1-3):109–131, 2012

59

Appendix B

The Robustness of BalancedBoolean Networks

• Ming Liu and Elena Dubrova. The robustness of balanced Boolean net-works. In Ronaldo Menezes, Alexandre Evsukoff, and Marta C. González,editors, Complex Networks, volume 424 of Studies in Computational Intelli-gence, pages 19–30. Springer Berlin Heidelberg, 2013. ISBN 978-3-642-30286-2

61

Appendix C

A Faster Shift Register Alternativeto Filter Generators

• Ming Liu, S.S. Mansouri, and E. Dubrova. A faster shift register alternativeto filter generators. In Proceedings of 2013 Euromicro Conference on DigitalSystem Design (DSD), pages 713–718, Sept 2013

63

Appendix D

A New Approach to Reliable FSRsDesign

• Ming Liu and Elena Dubrova. A new approach to reliable FSRs design. InProceedings of 32nd Nordic Microelectronics Conference NORCHIP, Oct 2014

65

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