ARCHITECTURE OF TMS320C54XX DIGITAL SIGNAL PROCESSORS

TMS320C54X INTERNAL BLOCK DIAGRAM

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1. ARCHITECTURE

• Architecture of the TMS320C54XX comprises of: CPU Memory ON-chip peripherals

• This DSP uses modified Harvard Architecture• Provides a high degree parallelism due to

separate program and data spaces which allows simultaneous access to program instructions and data.

• They have 1 program and 3 data memory spaces

1. CPU

• Contains:40-bit ALUTwo 40-bit accumulatorsBarrel shifter17× 17-bit multiplier40-bit adderCompare, select and store unit(CSSU)Data address generation unit(DAGEN)Program address generation unit(PAGEN)

1.1 ARITHMETIC LOGIC UNIT(ALU)

ALU performs 2’s complement arithmetic operations and bit level Boolean operations on 16-, 32-, and 40-bit words.

Also function as 2 separate 16-bit ALUs and perform two 16-bit operations simultaneously.

1.2 ACCUMULATORS• Accumulators A,B store output from the ALU or

the multiplier/adder block.• They also provide second input to ALU and

accumulator A can be an input to the multiplier block.

• Either of the accumulators can be used as temporary storage for the other.

• Accumulator divides into:– Guard bits(bits 39-32)– High-order word(bits 31-16)– Low-order word(bits 15-0)

1.3 BARREL SHIFTER• It provides the capability to scale the data during

an operand write or read.• It has a 40-bit input connected to the

accumulators or to data memory (using CB or DB) and a 40-bit output connected to the ALU or to data memory(using EB)

• It produces a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data.

• The shift requirements are defined in the shift count field of the instruction, shift count field of status register ST1 or in the temporary register T.

The barrel shifter and exponent encoder normalize the values in an accumulator in a single cycle.

The LSBs of the output are filled with 0s and the MSBs can either zero filled or sign extended, depending on the state of the sign-extension bit(SXM) in ST1.

Additional shift capabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention operations.

1.4 MULTIPLIER/ADDER UNITIt performs 17× 17-bit

2s-complement multiplication with a 40-bit addition in a single cycle.

Consists of several elements:A multiplierAn adderSigned/unsigned input

control logicFractional control logicA zero detectorA rounder(2s

complement)Overflow/saturation

logicA 16-bit temporary

storage register(T)

Multiplier has 2 inputs: Selected from T, a data memory operand, or

Accumulator ASelected from program memory, data

memory, Accumulator A or an intermediate value

Fast on-chip multiplier allows convolution, correlation and filtering

Multiplier + ALU together execute MAC computations & ALU operations in parallel in a single instruction cycle.

This function is used in determining the Euclidian distance and in implementing symmetrical and LMS filters which are required for complex algorithms

1.5 COMPARE, SELECT AND STORE UNIT(CSSU)CSSU accelerates

Viterbi-type Butterfly computations with optimized onchip hardware.

Performs:maximum comparison

between accumulator’s high and low word

allows both the test/control flag bit(TC) in the status register ST0 & the transition register(TRN) to keep their transition histories

Selects the larger word in the accumulator to store into the data memory

1.6 DATA ADDRESS GENERATION UNIT

DSP offers 7 basic data addressing modes:Immediate addressingAbsolute addressingAccumulator addressingDirect addressingIndirect addressingMemory-mapped register addressingStack addressing

During the execution of direct, indirect or memory mapped register addressing, the DAGEN computes the addresses of data-memory operands.

1.7 PROGRAM MEMORY ADDRESSING UNIT

Program memory usually addressed with Program counter

PC is loaded by PAGEN. PAGEN increments the PC as sequential instructions are fetched.

PAGEN may load the PC with a non-sequential value as a result of some instructions or other operations(branches, calls, returns, conditional operations, single/multiple instruction repeats, reset, & interrupts)

For calls & interrupts:The current PC is saved onto stack, which is

referenced by the stack pointer(SP).When interrupt service routine is finished, the PC

value in the stack is restored via return instruction

2. BUS STRUCTURE8 major 16- bit buses(4program/data buses and 4

address buses)Program bus(PB)- carries the instruction code &

immediate operands from program memoryData buses CB & DB- carry the operands that are

read from data memoryData bus EB- carries the data to be written to

memory4 Address buses(PAB, CAB, DAB, EAB)-carry the

addresses needed for the instruction executionDSP can generate up to 2 data-memory addresses

per cycle using the 2 auxiliary register arithmetic units(ARAU0 ARAU1) – enables accessing 2 operands simultaneously .

For accessing on-chip peripherals, C54X DSP also has an on-chip bidirectional busThis bus is connected to DB & EB through a bus exchanger in the CPU interface.

3. INTERNAL MEMORY ORGANIZATION

Memory organized into 3 individually selectable spaces:ProgramDataI/O space

DSP can contain RAM & ROMROM:

Is part of program memory space & sometimes data memory space.

Contains a bootloader that is useful for booting to faster on-chip or external RAM

RAM:Dual-access type(DARAM)Single-access type(SARAM)Two-way shared RAM

Can configure the DARAM & SARAM as data memory or program/ data memory.

DSP has 26 CPU registers+ peripheral registers that are mapped in data-memory space

Memory-Mapped Registers Data memory space contains memory-mapped

registers for the CPU and the on-chip peripherals.

The memory-mapped access provides a convenient way to save and restore the registers for context switches and to transfer information between the accumulators and the other registers.

ON-CHIP PERIPHERALS

All the C54xE devices have a common CPU, but different on-chip peripherals

On-chip peripheral options:1. General-purpose I/O pins2. Software-programmable wait-state generator3. Programmable bank-switching logic4. Clock generator5. Timer6. Direct memory access (DMA) controller7. Standard serial port8. Time-division multiplexed (TDM) serial port9. Buffered serial port (BSP)10. Multichannel buffered serial port (McBSP)11. Host-port interface (8-bit standard (HPI), 8-bit

enhanced (HPI8), 16-bit enhanced (HPI16))

ADDRESSING MODESImmediate addressing-uses the instruction to encode a fixed

value.

Absolute addressing-uses the instruction to encode a fixed address.

Accumulator addressing-uses an accumulator to access a location in program memory as data.

Direct addressing-uses seven bits of the instruction to encode an offset relative to DP or to SP. The offset plus DP or SP determine the actual address in data memory.

Indirect addressing-uses the auxiliary registers to access memory.

Memory-mapped register addressing modifies the memory-mapped registers without affecting either the current DP value or the current SP value.

Stack addressing-manages adding and removing items from the system stack.