ARM7TDMI Processor

ARM7TDMI Processor

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• The ARM7TDMI processor : 32-bit 범용 microprocessor 중 Advanced RISC machine 계열 중 하나

• ARM7TDMI 가 뭐냐 ?ARM7 - 32-bit Advanced RISC Machine

T - Thumb architecture extension• Two separate instruction sets, 32-bit ARM instructions and 16-bit Thumb

instructions

D - Debug extension

M - Enhanced multiplier

I - Embedded ICE macrocell extension

• ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{-S}x: 제품군 , y:MMU/MPU z: 캐시 D:JTAG debug M: 곱셈기I: embeddedICE Macrocell E: dsp 확장 J: jazelle

F: VFP S: synthesizible 버전

ARM7TDMI processorARM7TDMI processor

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ARM7TDMI Block DiagramARM7TDMI Block Diagram

• 폰 노이만 아키텍쳐

• 3- 단 파이프라인 – fetch, decode, execute

• 32-bit 데이터 버스 (core)

• 32-bit 어드레스 버스 (core)

• 37 32-bit 레지스터

• 32-bit ARM instruction set

• 16-bit THUMB instruction set

• 32x8 Multiplier( 곱셈기 )

• Barrel Shifter( 배럴 시프트 )

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• ARM7TDMI 프로세서 2 가지 동작 상태 ( 모드 ):– ARM 모드 : executes 32-bit, word aligned ARM instructions

– THUMB 모드 : execute 16-bit, halfword aligned THUMB instructions

• Switching state

– THUMB 모드 진입• BX 명령어에서 operand register 0 번 bit 의 상태로 구분 (set)• Automatically on return from an exception (IRQ, FIQ, ABORT, SWI,…),

if the exception was entered with the processor in THUMB state.

– ARM 모드 진입• BX 명령어에서 operand register 0 번 bit 의 상태 (clear) • Automatically on the processor taking an exception. In this case, the PC

is placed in the exception mode’s link register.

ARM7TDMI ARM7TDMI 동작 모드동작 모드 (1)(1)

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메모리에서 명령어 읽기메모리에서 명령어 읽기

명령어 길이 8bit

메모리(bus width)

16bit


32bit


ARM 32bit 4 사이클 2 사이클 1 사이클

Thumb 16bit 2 사이클 1 사이클 1 사이클

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• ARM7TDMI 7 가지 모드 지원 :– User (usr): 일반적인 ARM 프로그램 실행상태– FIQ (fiq): 고속 인터럽트 처리– IRQ (irq): 일반 인터럽트 처리– Supervisor (svc): 운영체제를 위한 보호 모드– Abort mode (abt): 가상메모리와 메모리 보호 처리– System (sys): 운영체제를 위한 user 모드– Undefined (und): 하드웨어 코프로세서의 소프트웨어 에뮬레이션

• 모드 전환은 외부 인터럽트나 익셉션 처리를 위해 사용됨– 대부분의 어플리케이션은 user mode 에서 실행– 그 밖에는 인터럽트 , exception, protect 된 리소스의 접근을 위해

system 모드가 사용됨 .

ARM7TDMI ARM7TDMI 동작동작 모드모드 (2)(2)

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ARM7TDMI RegistersARM7TDMI Registers

• ARM7TDMI 총 37 개 register:– 31 general-purpose 32-bit registers

– 6 status registers(CPSR, SPSR_SVC, SPSR_adt, …)

• 이 37 개 register 들은 한번 볼 수는 없다 .(visible 16 개 )– The processor state and operating mode dictate which registers are

available to the programmer.

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ARM State Registers SetARM State Registers Set

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THUMB State Registers SetTHUMB State Registers Set

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Relationship between ARM and Relationship between ARM and THUMB state registersTHUMB state registers

• The THUMB state registers relate to the ARM state registers in the following way:

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• ARM7TDMI 한 개의 Current Program Status Register (CPSR), 과 5 개의 exception handler 를 위해 Saved Program Status Registers (SPSRs)

• These register's functions are:– 가장 최근에 실행된 ALU 동작에 대한 정보를 저장– interrupt enable/disable 제어– 프로세서의 동작모드 설정

Program Status Registers (1/3)Program Status Registers (1/3)

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• Condition Code Flags– N : negative/less than flag 연산 결과가 마이너스인 경우 셋– Z : zero flag 연산결과가 0 이 되었을 때 셋– C : carry/borrow/extend flag 자리올림 / 내림발생 및 shift 연산에

사용– V : overflow 발생 시 사용

• In ARM state, all instructions may be executed conditionally.• In THUMB state, only the Branch instruction is capable of conditional

execution.

• Control Bits– The I, F, T and M[4:0]) bits will be changed when an exception arises.

If the processor is operating in a privileged mode, they can also be manipulated by software.

– T bit:• 동작모드상태 , 셋 되면 thumb 모드 동작 , 외부 signal 에 의해서도 발생• CPSR 에 강제로 이 bit 를 바꾸면 예측하지 못하는 상태로 들어갈 수 있다 .


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• Control Bits– Interrupt disable bits:

• I 와 F bit Interrupt disable bit 다 . Set 되었을 때 IRQ/ FIQ interrupt 를 disable 시킨다 .

– Mode bits:• The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits.• processor's operating mode 를 결정한다 . • 잘못된 값을 설정하면 , processor 가 reset 되거나 복구 불능상태에

빠진다 .


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• Exception program 이 halt 되었을 때 일반적으로 발생한다 . – For example to service an interrupt from a peripheral.

• ARM 7 가지의 exception 과 각각의 processor mode 마다 exception 을 가진다 .

• ARM Exception vectors

Exceptions (1/5)Exceptions (1/5)

Address Exception Mode in Entry

0x00000000 Reset Supervisor

0x00000004 Undefined instruction Undefined

0x00000008 Software Interrupt Supervisor

0x0000000C Abort (prefetch) Abort

0x00000010 Abort (data) Abort

0x00000014 Reserved Reserved

0x00000018 IRQ IRQ

0x0000001C FIQ FIQ

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• When handling an exception, the ARM7TDMI:– Link Register 에 다음 수행될 명령어의 주소를 저장한다 .

– SPSR 에 현재의 CPSR 값을 복사한다 .

– Exception 에 따른 값을 CPSR 로 가져온다 .

– Exception verctor 로부터 fetch 된 다음명령어를 PC 로 가져온다 .

– 여러가지 다른 exception 들로 부터 방해를 막기위해 인터럽트 disable flag 을 set 해야 한다 .

– THUMB 모드에서 exception 이 발생하면 , pc 가 exception vector를 읽어 올때 ARM mode 로 자동적으로 바뀌게 된다 .

– 저장된 Link Register 에서 – offset(exception vector) 만큼 뺀값을 pc 에 저장 .

– 저장된 SPSR 을 CPSR 에 복사– 인트럽트 disable flag 를 clear 한다 .( 인트럽트가 set 되어

있었다면 )


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• Reset– When the processor’s Reset input is asserted

• CPSR Supervisor + I + F• PC 0x00000000

• Undefined Instruction– If an attempt is made to execute an instruction that is undefined

• LR_undef Undefined Instruction Address + #4• PC 0x00000004, CPSR Undefined + I• Return with : MOVS pc, lr

• Prefetch Abort– Instruction fetch memory abort, invalid fetched instruction

• LR_abt Aborted Instruction Address + #4, SPSR_abt CPSR• PC 0x0000000C, CPSR Abort + I• Return with : SUBS pc, lr, #4


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• Data Abort– Data access memory abort, invalid data

• LR_abt Aborted Instruction + #8, SPSR_abt CPSR• PC 0x00000010, CPSR Abort + I• Return with : SUBS pc, lr, #4 or SUBS pc, lr, #8

• Software Interrupt– Enters Supervisor mode

• LR_svc SWI Address + #4, SPSR_svc CPSR• PC 0x00000008, CPSR Supervisor + I• Return with : MOV pc, lr


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• Interrupt Request– Externally generated by asserting the processor’s IRQ input

• LR_irq PC - #4, SPSR_irq CPSR• PC 0x00000018, CPSR Interrupt + I• Return with : SUBS pc, lr, #4

• Fast Interrupt Request– Externally generated by asserting the processor’s FIQ input

• LR_fiq PC - #4, SPSR_fiq CPSR• PC 0x0000001C, CPSR Fast Interrupt + I + F• Return with : SUBS pc, lr, #4 • Handler @0x1C speeds up the response time


ARM Instruction Set

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SummarySummary

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• All ARM instructions can be conditionally executed, which means that their execution may or may not take place depending on the values of values of the N, C, C and V flags in the CPSR

• Every instruction contains a 4-bit condition code field in bits

31 to 28

Condition Field (1/2)Condition Field (1/2)

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Condition Field (2/2)Condition Field (2/2)

• 15 개의 condition 이 있고 , 명령어의 mnemonic 에 2 개의 접미사가 붙는다 .

• Assembley 에서 Branch 명령의 경우 z-flag 가 set 되면 , BEQ 가 된다 .

• B initReset• 0xEA00000F

Code Suffix Flags Meaning

0000 EQ Z set Equal0001 NE Z clear Not equal0010 CS C set Unsigned higher or same0011 CC C clear Unsigned lower0100 MI N set Negative0101 PL N clear Positive or zero0110 VS V set Overflow0111 VC V clear No overflow1000 HI C set and Z clear Unsigned higher1001 LS C clear or Z set Unsigned lower or same1010 GE N equals V Greater or equal1011 LT N not equal to V Less than1100 GT Z clear AND (N equals V) Greater than1101 LE Z set OR (N not equal to V) Less than or equal1110 AL (ignored) always

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• 모든 ARM Processors branch 명령어의 condition 을 가질 수 있고 , 최대 앞 뒤로 32Mbyte 만큼 분기 할 수 있다 . (0-24bit: 25 개 0x1ffffff)

– As the Program Counter (PC) is one of the general-purpose registers (register 15), a branch or jump can also be generated by writing a value to register 15.

• subroutine call 도 표준 branch 중 한 변형이다 . Branch 후에는 항상 r14(lr) 에 명령어의 어드레스를 항상 저장해야 한다 .

• load 명령어는 4Gbyte 어드레스 영역의 어떤 곳이라도 분기할 수 있다 .

메모리로 부터 로드 된 32bit 값은 pc 에 들어가 branch 을 일으킨다 .

• The ARM7TDMI processor that support the Thumb instruction set also support a branch instruction (BX) that jumps to a given address, and optionally switches executing Thumb instructions.

Branch Instructions (1/2)Branch Instructions (1/2)

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• List of branch instructionsB, BL Branch, and branch with link BX Branch and exchange instruction set (ARM 모드에서 Thumb 모드로

전환 )

• ExamplesB label ; branch unconditionally to labelBCC label ; branch to label if carry flag is clear

BEQ label ; branch to label if zero flag is set

MOV PC, #0 ; R15 = 0, branch to location zero

BL func ; subroutine call to function

func MOV PC, LR ; R15=R14, return to instruction after the BLMOV LR, PC ; store the address of the instruction after the next one into R14

LDR PC, =func ; load a 32-bit value into the program counter

Branch Instructions (2/2)Branch Instructions (2/2)

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• ARM 은 16 개의 data processing instructions. 대부분의 data processing instruction 은 2 개의 operand 를 가진다 . (Move 와 and Move 은 하나의 operand 만 가진다 .)

• 하나의 register 에 하나의 결과값을 저장한다 . ( Compare 와 Test명령은 제외 -condition code 로 업데이트함 . 결과를 저장하지 않는다 .)

– 두개의 operand 중 하나는 항상 register 고 , 나머지는 shitfer operand 다 .( 그밖에 즉치나 register 값이다 . 가 올 수도 있다 .)

– ALU 가 operand2 로 사용하기 전에 shifter 후에 operand 로 사용할 수 있다 .

Data Processing (1/2)Data Processing (1/2)

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• List of data processing instructions

Data Processing (2/2)Data Processing (2/2)

Assembler Mnemonic OP Code Action

AND 0000 Operand1 AND operand2EOR 0001 Operand1 EOR operand2WUB 0010 Operand1 – operand2RSB 0011 Operand2 operand1ADD 0100 Operand1 + operand2ADC 0101 Operand1 + operand2 + carrySBC 0110 Operand1 – operand2 + carry –1RSC 0111 Operand2 – operand1 + carry –1TST 1000 As AND, but results is not writtenTEQ 1001 As EOR, but result is not writtenCMP 1010 As SUB, but result is not writtenCMN 1011 As ADD, but result is not writtenORR 1100 Operand1 OR operand2MOV 1101 Operand2 (operand1 is ignored)BIC 1110 Operand1 AND NOT operand2 (Bit clear)

MVN 1111 NOT operand2 (operand1 is ignored)

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곱셈 명령어들곱셈 명령어들 (1/2)(1/2)

• ARM 은 2 가지 형식의 곱셈명령어가 있다 .

– normal, 32-bit result

– long, 64-bit result

• 곱셈명령어는 항상 입력으로 두개의 operand register 를 가진다 .

• For example)

MUL R4, R2, R1 ; Set R4 to value of R2 multiplied by R1 MULS R4, R2, R1 ; R4 = R2xR1, set N and Z flags MLA R7, R8, R9, R3 ; R7 = R8xR9 + R3

일반적으로 normal 연산에서 결과값은 항상 하위 값만 가진다 .

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곱셈 명령어들곱셈 명령어들 (2/2)(2/2)

• 64bit 의 결과를 위해서는 4 개의 곱셈 명령이 있다 . (long 곱셈 )

– 2 개의 값을 곱해서 상위와 하위로 나누어서 각각 저장한다 .

SMULL R4, R8, R2, R3 ; R4 = bits 0 to 31 of R2xR3; R8 = bits 32 to 63 of R2 x R3

UMULL R6, R8, R0, R1 ; R6, R8 = R0 x R1UMLAL R5, R8, R0, R1 ; R5, R8 = R0 x R1 + R5, R8

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Load / Store Load / Store 명령어명령어 (1/2)(1/2)

• Load/ store 명령어는 3 가지 타입이 있다 . – load / store 하나의 register 값을 갖는다 .

– load / store multiple register values

– swap a register value with the value of a memory location

• load / store 하나의 register 값을 갖는다– LDR/STR, Load/Store word

– LDRB/STRB, Load/Store byte

– LDRH/STRH, Load/Store unsigned halfword

– LDRSB, Load signed byte

– LDRSH, Load signed halfword

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Load / Store Load / Store 명령어들명령어들 (2/2)(2/2)

• Load and Store multiple registers– List of load and store multiple instructions

• LDM, Load multiple• STM, Store multiple

– STMDB SP!, {R0,R4,R5,R6,LR}

• Swap a register value with the value of a memory location– List of semaphore instructions

• SWP, Swap

• SWPB, Swap Byte – SWP R12, R10, [R9] ; load R12 from address R9 and

; store R10 to address R9

– SWPB R3, R4, [R8] ; load byte to R3 from address R8 and

;store byte from R4 to address R8

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• The Software Interrupt instruction enters supervisor mode

– ARM 에서는 swi 를 거의 사용하지 않는다 . 대표적으로 사용하는 것은 JTAG 에뮬레이터를 사용하기 위해서 사용된다 .

• Semihosting library 호출시

SWI : Software InterruptSWI : Software Interrupt

THUMB Instruction Set

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SummarySummary

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• Thumb 명령어는 ARM 명령어의 파생 계열이다 . – Optimized for code density.

• 대부분의 Thumb instruction 은 ARM instruction:– ADD Rd, #Offset8 <> ADDS Rd, Rd, #Offset8

• Inline expansion of Thumb Instruction to ARM Instruction– Real time decompression– Thumb instructions are not actually executed on the core

• The core needs to know whether it is reading Thumb instructions or ARM instructions.

– Core has two execution states - ARM and Thumb– Core does not have a mixed 16 and 32 bit instruction set.

Thumb Thumb 어떻게 동작할까어떻게 동작할까 ??

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Thumb Instruction Set DecompressionThumb Instruction Set Decompression

0 0 11 1 1 0

31 0

Rd Rd

0 0 1 Rd Constant

15 0

Alwayscondition

1 0

0 1 0 0 1 0 0 0 00 0

THUMB: ADD Rd,#Constant

ARM: ADDS Rd, Rd, #Constant

Major opcode

Constant

Destination &source register

Zero extendedconstant

78111215161920212428

II SSop1+op2op1+op2

Minoropcode

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Branch Branch 명령어들명령어들

• Thumb supports four types of branch instruction:– unconditional branch => 전후 2Kbytes(2^11)

– conditional branch => 전후 256 bytes (2^8)

• List of branch instructions– B conditional branch

– B unconditional branch

– BL Branch with link

– BX Branch and exchange instruction set

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Data Processing Data Processing 명령어들명령어들

• Thumb data-processing instruction 은 ARM data-processing instruction 의 축약이다 .– 모든 Thumb data-processing instructions set the condition codes

• List of data-processing instructions – ADC, Add with Carry– ADD, Add – AND, Logical AND – ASR, Arithmetic shift right – BIC, Bit clear – CMN, Compare negative– CMP, Compare – EOR, Exclusive OR – LSL, Logical shift left – LSR, Logical shift right

– MOV, Move– MUL, Multiply – MVN, Move NOT– NEG, Negate– ORR, Logical OR– ROR, Rotate Right– SBC, Subtract with Carry– SUB, Subtract– TST, Test

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Load / Store Register Load / Store Register 명령어들명령어들

• Thumb 에서는 8 가지의 load / store register 명령어들

• List of load and store register instructions– LDR Load word

– LDRB Load unsigned byte

– LDRH Load unsigned halfword

– LDRSB Load signed byte

– LDRSH Load signed halfword

– STR Store word

– STRB Store byte

– STRH Store halfword

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Load / Store Load / Store 곱셈 명령어들곱셈 명령어들

• Thumb 에서는 4 가지 load / store 곱셈 명령어

• 2 개의 block copy (a load and store) • 나머지 2 개는 스택명령어인 PUSH / POP 이다 . • 스택명령어는 full descending stack 동작만 지원한다 .

stack pointer 는 base register 로 사용된다 .

• List of load and store multiple instructions– LDM Load multiple

– POP Pop multiple

– PUSH Push multiple

– STM Store multiple

ARM vs THUMB

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Code sizeCode size

• Generally, routines in THUMB code are between 65 and 70% the size of the equivalent ARM code.

65% 70% 75%60%% of ARM code size

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Code performances vs Memory widthCode performances vs Memory width

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• All instructions are 32 bits long.

• Most instructions are executed in one single cycle.

• Every instructions can be conditionally executed.

• A load/store architecture– Data processing instructions act only on registers

• Three operand format• Combined ALU and shifter for high speed bit manipulation

– Specific memory access instructions with powerful auto-indexing addressing modes

– 32 bit ,16 bit and 8 bit data types

– Flexible multiple register load and store instructions

Arm Instruction Set AdvantagesArm Instruction Set Advantages

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• All instructions are exactly 16 bits long to improve code density over other 32-bit architectures

• The Thumb architecture still uses a 32-bit core, with:– 32-bit address space

– 32-bit registers

– 32-bit shifter and ALU

– 32-bit memory transfer

• Gives.... – Long branch range

– Powerful arithmetic operations

– Large address space

Thumb Instruction Set AdvantagesThumb Instruction Set Advantages

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ARM7TDMI Processor