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Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 1
Single Single DatapathDatapathArquitectura de ComputadorasArquitectura de Computadoras
Arturo DArturo Dííaz Paz PéérezrezCentro de InvestigaciCentro de Investigacióón y de Estudios Avanzados del IPNn y de Estudios Avanzados del IPN
Laboratorio de TecnologLaboratorio de Tecnologíías de Informacias de Informacióó[email protected]@cinvestav.mx
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 2
The Big Picture: The Performance The Big Picture: The Performance PerspectivePerspective
♦
Performance of a machine is determined by:■
Instruction count
■
Clock cycle time■
Clock cycles per instruction
♦
Processor design (datapath and control) will determine:■
Clock cycle time
■
Clock cycles per instruction
♦
Today:■
Single cycle processor:
» Advantage: One clock cycle per instruction» Disadvantage: long cycle time
CPI
Inst. Count Cycle Time
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 3
5 5 StepsSteps ofof DLX DLX DatapathDatapath
PCInst.
Memory
Add
Registers
SignExtend
Add
Mux
Mux
Zero ?
Mux
DataMemory
Mux
NPC
IR
16
A
B
SMD
ALUOutput
LMD
Instruction Fetch Instruction Decode/Register Fetch
ExecuteAddr. Calc.
MemoryAccess
WriteBack
32
4
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 4
How to Design a Processor: stepHow to Design a Processor: step--byby-- stepstep
1.
Analyze instruction set => datapath requirements■
the meaning of each instruction is given by the register transfers
■
datapath must include storage element for ISA registers» possibly more
■
datapath must support each register transfer
2.
Select set of datapath components and establish clocking methodology
3.
Assemble datapath meeting the requirements4.
Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
5.
Assemble the control logic
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 5
The MIPS Instruction FormatsThe MIPS Instruction Formats
♦
All MIPS instructions are 32 bits long. The three instruction formats:
■
R-type
■
I-type
■
J-type
♦
The different fields are:■
op: operation of the instruction
■
rs, rt, rd: the source and destination register specifiers■
shamt: shift amount
■
funct: selects the variant of the operation in the “op”
field■
address / immediate: address offset or immediate value
■
target address: target address of the jump instruction
op target address02631
6 bits 26 bits
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 6
Step 1a: The MIPSStep 1a: The MIPS--litelite Subset for Subset for todaytoday
♦
ADD and SUB■
addU
rd, rs, rt
■
subU
rd, rs, rt
♦
OR Immediate:■
ori
rt, rs, imm16
♦
LOAD and STORE Word■
lw
rt, rs, imm16
■
sw
rt, rs, imm16
♦
BRANCH:■
beq
rs, rt, imm16
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 7
Logical Register TransfersLogical Register Transfers
♦
RTL gives the meaning
of the instructions
♦
All start by fetching the instructionop | rs | rt | rd | shamt | funct = MEM[ PC ]
op | rs | rt | Imm16 = MEM[ PC ]
inst Register Transfers
ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4
SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ORi R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4
BEQ if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(Imm16)] || 00 else PC <– PC + 4
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 8
Step 1: Requirements of the Step 1: Requirements of the Instruction SetInstruction Set
♦
Memory■
instruction & data
♦
Registers (32 x 32)■
read RS
■
read RT■
Write RT or RD
♦
PC♦
Extender
♦
Add and Sub register or extended immediate♦
Add 4 or extended immediate to PC
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 9
Step 2: Components of the DatapathStep 2: Components of the Datapath
♦
Combinational Elements♦
Storage Elements■
Clocking methodology
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 10
Combinational Logic Elements (Basic Combinational Logic Elements (Basic Building Blocks)Building Blocks)
32
32
32
A
B32 Sum
Carry
Adder
CarryIn
Adder
32A
B 32
Y32
Select
MU
X
MUX
32A
B32 Result
OPA
LU
ALU
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 11
Storage Element: Register (Basic Storage Element: Register (Basic Building Block)Building Block)
♦
Register■
Similar to the D Flip Flop except
» N-bit input and output» Write Enable input
■
Write Enable:» negated (0): Data Out will not change» asserted (1): Data Out will become Data In
Clk
Data In
Write Enable
N NData Out
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 12
Storage Element: Register FileStorage Element: Register File
♦
Register File consists of 32 registers:■
Two 32-bit output busses:
» busA
and busB■
One 32-bit input bus: busW
♦
Register is selected by:■
RA (number) selects the register to put on busA
(data)
■
RB (number) selects the register to put on busB
(data)■
RW (number) selects the register to be written
via busW
(data) when Write Enable is 1
♦
Clock input (CLK) ■
The CLK input is a factor ONLY during write operation
■
During read operation, behaves as a combinational logic block:» RA or RB valid => busA
or busB
valid after “access time.”
Clk
busW
Write Enable
3232
busA
32busB
5 5 5RWRA RB
32 32-bitRegisters
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 13
Storage Element: Idealized MemoryStorage Element: Idealized Memory
♦
Memory (idealized)■
One input bus: Data In
■
One output bus: Data Out
♦
Memory word is selected by:■
Address selects the word to put on Data Out
■
Write Enable = 1: address selects the memory word to be written via the Data In bus
♦
Clock input (CLK) ■
The CLK input is a factor ONLY during write operation
■
During read operation, behaves as a combinational logic block:» Address valid => Data Out valid after “access time.”
Clk
Data In
Write Enable
32 32DataOut
Address
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 14
Clocking MethodologyClocking Methodology
♦
All storage elements are clocked by the same clock edge♦
Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew
♦
(CLK-to-Q + Shortest Delay Path -
Clock Skew) > Hold Time
Clk
Don’t Care
Setup Hold
.
.
.
.
.
.
.
.
.
.
.
.
Setup Hold
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 15
Step 3: Assemble DataPath meeting Step 3: Assemble DataPath meeting our requirementsour requirements
♦
Register Transfer Requirements ⇒
Datapath Assembly
♦
Instruction Fetch♦
Read Operands and Execute Operation
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 16
3a: Overview of the Instruction Fetch 3a: Overview of the Instruction Fetch UnitUnit
♦
The common RTL operations■
Fetch the Instruction: mem[PC]
■
Update the program counter:» Sequential Code: PC <-
PC + 4
» Branch and Jump: PC <-
“something else”
32
Instruction WordAddress
InstructionMemory
PCClk
Next AddressLogic
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 17
3b: Add & Subtract3b: Add & Subtract
♦
R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt■
Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields
■
ALUctr and RegWr: control logic after decoding the instruction
32Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 18
RegisterRegister--Register Timing: One Register Timing: One complete cyclecomplete cycle
Clk
PC
Rs, Rt, Rd,Op, Func
Clk-to-Q
ALUctr
Instruction Memory Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busA, BRegister File Access Time
Old Value New Value
busWALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
Register WriteOccurs Here
3 2
Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 19
3c: Logical Operations with 3c: Logical Operations with ImmediateImmediate
♦
R[rt] <-
R[rs] op ZeroExt[imm16] ]
32
Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs
ZeroE
xt
Mux
RtRdRegDst Mux
3216imm16
ALUSrc
AL
U
11op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd?
immediate016 1531
16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rt?
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 20
3d: Load Operations3d: Load Operations
♦
R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
11op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs
RtRdRegDst
Extender
Mux
Mux
3216
imm16
ALUSrc
ExtOp
Clk
Data InWrEn
32
AdrData
Memory32
AL
U
MemWr Mux
W_Src
??
Rt?
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 21
3e: Store Operations3e: Store Operations
♦
Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrcExtOp
Clk
Data InWrEn
32Adr
DataMemory
MemWr
AL
U
32
Mux
W_Src
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 22
3f: The Branch Instruction3f: The Branch Instruction
♦
beq
rs, rt, imm16
■
mem[PC]
Fetch the instruction from memory
■
Equal <-
R[rs] == R[rt]
Calculate the branch condition
■
if (Equal)
Calculate the next instruction’s address
» PC <-
PC + 4 + ( SignExt(imm16) x 4 )■
else» PC <-
PC + 4
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 23
Datapath for Branch OperationsDatapath for Branch Operations
♦
beq rs, rt, imm16 Datapath generates condition (equal)
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
32
imm16PC
Clk
00
Adder
Mux
Adder
4nPC_sel
Clk
busW
RegWr
32
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs Rt
Equ
al?
Cond
PC E
xt
Inst Address
Putting it All Together: A Single Cycle Putting it All Together: A Single Cycle DatapathDatapath
imm
16
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
3216imm16
ALUSrcExtOp
Mux
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
Adder
Adder
PC
Clk
00Mux
4
nPC_sel
PC E
xt
Adr
InstMemory
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 25
An Abstract View of the An Abstract View of the Critical PathCritical Path♦
Register file and ideal memory:■
The CLK input is a factor ONLY during write operation
■
During read operation, behave as combinational logic:» Address valid => Output valid after “access time.”
Critical Path (Load Operation) = PC’s Clk-to-Q +Instruction Memory’s Access Time +Register File’s Access Time +ALU to Perform a 32-bit Add +Data Memory Access Time +Setup Time for Register File Write +Clock Skew
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
16Imm
32
323232
A
B
Nex
t Add
ress
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 26
An Abstract View of the An Abstract View of the ImplementationImplementation
DataOut
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t Add
ress
Control
Datapath
Control Signals Conditions
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 27
Step 4: Given Datapath: RTL Step 4: Given Datapath: RTL --> > ControlControl
ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<21:25>
Fun
RegWr
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 28
Adr
InstMemory
Meaning of the Control SignalsMeaning of the Control Signals
♦
Rs, Rt, Rd and Imed16 hardwired into datapath♦
nPC_sel: 0 => PC <–
PC + 4; 1 => PC <–
PC + 4 + SignExt(Im16) || 00
Adder
Adder
PC
Clk
00Mux
4
nPC_selPC
Extim
m16
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 29
Meaning of the Control SignalsMeaning of the Control Signals
♦
ExtOp:■
“zero”, “sign”♦
ALUsrc:■
0 => regB; 1 => immed
♦
ALUctr:■
“add”, “sub”, “or”
♦
MemWr:■
write memory♦
MemtoReg:■
1 => Mem♦
RegDst:■
0 => “rt”; 1 => “rd”
♦
RegWr:■
write dest register
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
3216imm16
ALUSrcExtOp
Mux
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWr
AL
U
Equal
0
1
0
1
01
=
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 30
Control SignalsControl Signals
inst Register Transfer
ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4
ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”
SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 31
Control Signals (Answer)Control Signals (Answer)
inst Register Transfer
ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4
ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”
SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”
ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4
ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”
STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”
BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4
nPC_sel = EQUAL, ALUctr = “sub”
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 32
Step 5: Logic for each control signalStep 5: Logic for each control signal
♦
nPC_sel <= if (OP == BEQ) then EQUAL else 0♦
ALUsrc <= if (OP == “000000”) then “regB” else “immed”
♦
ALUctr <= if (OP == “000000”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub”
else “add”♦
ExtOp <= _____________
♦
MemWr <= _____________♦
MemtoReg <= _____________
♦
RegWr: <= _____________♦
RegDst: <= _____________
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 33
Step 5: Logic for each control Step 5: Logic for each control signal (Answer)signal (Answer)
♦
nPC_sel <= if (OP == BEQ) then EQUAL else 0♦
ALUsrc <= if (OP == “000000”) then “regB” else “immed”
♦
ALUctr <= if (OP == “000000”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub”
else “add”♦
ExtOp <= if (OP == ORi) then “zero” else “sign”
♦
MemWr <= (OP == Store)♦
MemtoReg <= (OP == Load)
♦
RegWr: <= if ((OP == Store) || (OP == BEQ)) then 0 else 1♦
RegDst: <= if ((OP == Load) || (OP == ORi)) then 0 else 1
Example: Load InstructionExample: Load Instruction
32
ALUctr
Clk
busW
RegWr
32
32
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
3216Imm16
ALUSrcExtOp
Mux
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
imm
16
Adder
Adder
PC
Clk
00Mux
4
nPC_sel
PC E
xt
Adr
InstMemory
sign ext
addrt+4
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 35
An Abstract View of the An Abstract View of the ImplementationImplementation
♦
Logical vs. Physical Structure
DataOut
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t Add
ress
Control
Datapath
Control Signals Conditions
Laboratorio deTecnologías de Información
Arquitectura de Computadoras Datapath- 36
SummarySummary
♦
5 steps to design a processor■
1. Analyze instruction set => datapath requirements
■
2. Select set of datapath components & establish clock methodology■
3. Assemble datapath meeting the requirements
■
4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
■
5. Assemble the control logic♦
MIPS makes it easier■
Instructions same size
■
Source registers always in same place■
Immediates
same size, location
■
Operations always on registers/immediates♦
Single cycle datapath => CPI=1, CCT => long
♦
Implementing control?