Controlling Linewidth Roughness in Step and Flash Imprint LithographyGerard M. Schmid, Niyaz Khusnatdinov, Cynthia B. Brooks, Dwayne LaBrake, Ecron Thompson, and Douglas J. Resnick, Molecular Imprints, Inc., 1807C West Braker Lane, Austin TX 78758, USA

Jordan Owens and Arnie Ford, Sematech ATDF, 2706 Montopolis Drive, Austin, Texas 78741-6499, USA

Shiho Sasaki, Nobuhito Toyama, Masaaki Kurihara, and Naoya Hayashi, Electronic Device Laboratory, Dai Nippon Printing Co., Ltd., 2-2-1, Fukuoka, Fujimino-shi, Saitama 356-8507, Japan

Hideo Kobayashi, Takashi Sato, and Osamu Nagarekawa, HOYA Corporation R&D Center 3-3-1 Musashino,Akishima-shi,Tokyo 196-8510 Japan

Mark W. Hart, Kailash Gopalakrishnan, Rohit Shenoy, and Ron Jih, IBM Almaden Research Center, 650 Harry Road San Jose, CA 95120-6099, USA

Ying Zhang, Edmund Sikorski, and Mary Beth Rothwell, IBM Thomas J. Watson Research Center, 1101 Kitchawan Road, Route 134Yorktown Heights, NY 10598-0218, USA

Shusuke Yoshitake, Hitoshi Sunaoshi, and Kenichi Yasui, NuFlare Technology, Inc., 8, Shinsugita-cho, Isogo-ku, Yokohama 235-0032, Japan

ABSTRACTDespite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be suffi cient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly chal-

Continues on page 3.

Figure 1. Linewidth roughness (LWR) for 90nm half pitch imprinted lines. The template used to imprint these features was fabricated using a fast chemically amplifi ed resist.

PHOTOMASKPHOTOMASKBACUS—The international technical group of SPIE dedicated to the advancement of photomask technology.

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MAY 2008VOLUME 24, ISSUE 5

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BACUS News is published monthly by SPIE for BACUS, the international technical group of SPIE dedicated to the advancement of photomask technology. Circulation 2600.

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The Weakest LinkBen Eynon, SEMATECHPicture the complete EUV lithography infrastructure integration as a chain comprised of many interdependent links. In a perfect world, each link would have the same strength such that it would not break due to a single weak one. The industry seems to have fi nally grabbed the end of the EUV infrastructure chain and is tugging harder than ever before in the interest of implementing a cost-effective lithographic solution to its anticipated future resolution needs. The strain on this chain has brought to light a few areas that are not strong enough yet to be considered ready for implementation even at the pre-production stage.

Probably the most talked-about issue centers around the EUV exposure tool; specifi cally, the EUV source-collector module (SoCoMo). Right behind that topic usually follows the exposure tool’s debris mitigation system to keep the expensive optics clean. Then resist performance usually crops up as it has done in the past when stepper/scanner source wavelengths changed. And when it comes to masks, the changes are equally as sig-nifi cant, and affect several areas in totally new ways.

Starting with the blank itself, the fused silica substrate is no longer a transmissive element in EUV lithography. Instead, the substrate’s sole purpose is to provide a rigid, fl at, low expansion coeffi cient foundation for the 80-layered mirror, capping layer, and absorber layer. The substrate polishing process must be near perfect because even a <5nm pit or bump can turn into an amplitude-type defect 10-20x larger. Slight “dishing” in the glass can also cause catastrophic printing errors due to the phase errors that result. Neither of these situations caused printing errors in DUV lithography. If the polishing process cannot be made to produce perfect surfaces, it will become incumbent upon the blank industry to utilize pit/defect mitigation strategies currently in development.

Also, since the mask is a refl ective element in the optical system, the 80-layered mirror as well as the capping and absorber layers must be deposited defect-free. The process yield on a single or double-layered DUV mask is not 100%, so defect control on 80-plus layers presents an even bigger challenge!

Another departure from DUV lithography that affects the mask industry is the absence of a pellicle, thanks to the EUV photon’s proclivity to be absorbed by virtually every material. Since the fi nished mask has to be shipped, unpackaged, pre-inspected, loaded into the scanner, exposed, and unloaded – all without any protection – it is imperative that the reticle carrier keeps all defects from falling on the patterned surface. It is also hoped that this carrier can assist in minimizing haze formation in the mask’s lifetime.

SEMATECH has prioritized both mask blank and mask carrier activities (among other categories) in the aforementioned problem areas in order to ensure that the mask portion of EUV lithography infrastructure is robust enough to be ready for beta scanner introduction timing. Great progress has been made over the last fi ve years in spite of the complexity and uniqueness of the problems encountered in each area. Through continued effort and innovation at the Albany, NY facility, the mask industry will benefi t by having the blanks and defect control infrastructure it needs at the right time. Anyone who says it is easy though is just pulling your chain.

Editorial

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lenging for electron and photon based NGL technologies, where fast chemically amplifi ed resists are used to defi ne the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fi del-ity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions.

Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Nonchemically amplifi ed resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the fi nal patterned substrate.

Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.

1. IntroductionDespite the remarkable progress made in the past decade in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be suffi cient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining rea-sonable process throughput. This limitation is particularly chal-lenging for electron and photon based NGL technologies, where fast chemically amplifi ed resists are used to defi ne the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. LWR guidelines for the industry are very aggressive. Table 1 depicts the ITRS 2006 roadmap for LWR as a function of both year and DRAM half pitch.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22nm nodes. Step and Flash Imprint Lithography (S-FIL®) operates in a step-and-repeat fashion: the processes of deposition of imprint material, imprint, alignment, photocuring and release all occur sequentially as each die on a wafer is patterned.1,2 S-FIL utilizes UV-curable liquids that are dispensed in a drop-wise fashion to meet the local pattern density requirements of the template structures, thus enabling imprint patterning with a uniform residual layer. This technol-ogy has been shown to be an effective method for replication of nanometer-scale structures from a template mold. As a high fi delity replication process, the resolution of imprint lithography

Figure 2. 30nm semi-dense structure: a) Template, b) imprinted features, c) etched SOI fi ns, and d) cross-section of etched fi ns after additional processing.

Table 1. ITRS roadmap for linewidth roughness (LWR), starting at the 65nm half pitch and extending out to 16nm.

Continued from cover.

Continues on page 4.

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is determined by the ability to create a master template having the required dimensions.

Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing any linewidth roughness falls to the template fabrication process. Increasing the sensitivity of chemically amplifi ed resists has been shown to cause increased LWR in both EUV and electron beam exposure processes. Non chemically amplifi ed resists, such as ZEP520A, have excellent resolution but are not nearly as sensi-tive and can produce features with very low LWR. Nonchemically amplifi ed resists are therefore much better candidates for high resolution imprint templates. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the fi nal patterned substrate.

2. Experimental DetailsTemplates used for analysis in this work were supplied by both Dai Nippon Printing (DNP) and Hoya. The basic process used to fabricate the templates is briefl y described. Exposures were performed with either 50 kV variable shaped beam (VSB) pattern generators or 100 kV Gaussian beam (GB) pattern generators. Both a positive tone fast chemically amplifi ed resist and a slower nonchemically amplifi ed resist were employed on the VSB writers. ZEP520A was used in all cases when writing on GB systems. After exposure and development of the resists, the chromium and fused silica were etched using Cl2/O2 and fl uorine-based chemistry, re-spectively. The details of the process are discussed in References 3 and 4. Mesa lithography and a mesa etch process, followed by a dice and polish step were employed to create a fi nished 65mm x 65mm template.5

Imprinting of the template pattern was performed by using a Molecular Imprints Imprio 250 imprint tool. A Drop-On-Demand method was employed to dispense the photo-polymerizable acrylate based imprint solution in fi eld locations across a 200mm silicon wafer. The template was then lowered into liquid-contact with the substrate, displacing the solution and fi lling the imprint

fi eld. UV irradiation through the backside of the template cured the acrylate monomer. The process was then repeated to completely populate the substrate. Details of the imprint process have previ-ously been reported.6 SOI wafers were etched using an Applied Materials capacitively-coupled etch chamber. Oxide wafers were etched in a Trion reactive ion etch chamber.

LWR measurements were performed two different ways. In the fi rst case, high resolution SEM images were taken with a JEOL JSM-6340F fi eld emission cold cathode SEM equipped with a tungsten emitter. The accelerating voltage can be varied from 0.5 to 30 kV. The system has intrinsic 1.2nm resolution capability at 15 kV accelerating voltage, and 2.5nm at 1 kV. Critical dimension (CD), linewidth roughness, and line edge roughness (LER) data were then extracted offl ine using the SIMAGIS® automated image metrology software suite from Smart Imaging Technologies. For the analysis of some of the etch work, an AMAT NanoSEM was used to collect information on CD. LWR and LER. The beam ac-celerating voltage was 500V. 1200 pixels were used per scan line and 256 lines were scanned for each feature.

3. ResultsLWR was analyzed using eight different templates. Five different studies were performed: a) LWR from imprints obtained with a template fabricated using a VSB pattern generator and a fast CA resist, b) CD and LWR for 30nm and 40nm semi-dense structures, evaluated after imprint, and after SOI etch, c) CD and LWR analysis for dense 42nm lines, starting at imprint, and ending after a clean process following an oxide etch, and d) an analysis of CD and LWR of the template and the imprinted images for features sizes ranging from half pitches of 32nm to 44nm. A 100 KV Gaussian beam pattern generator was used for cases b, c, and d. e) LWR from templates and imprints fabricated using a VSB pattern gen-erator and a slower high resolution resist

a. Imprints from a VSB TemplateFast chemically amplifi ed resists are typically used in the fabrica-

Continued from page 3.

Figure 3. LWR and LER measurements of the 30nm and 40nm semi-dense features after etch.

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tion of 4X photomasks and have also been employed when writing full fi eld 1X templates. Previous publications have noted that reso-lution is typically limited to 60nm with this type of processing.7,8

LWR is also impacted, and Figure 1 shows an example of the LWR obtained from 90nm dense lines using a template fabricated with a fast CA resist. SIMAGIS software was used to analyze CD, LWR and LER. Four lines were measured, with a sampling step of 3.79nm. The mean LWR was 11.27nm, with a 3σ variation of 1.37nm. The large LWR is primarily attributed to shot noise limi-tations during the exposure process.9,10 Other templates created with somewhat slower CA resists have yielded somewhat better

LWR results (< 8nm, 3σ), but nothing approaching the values suggested by the ITRS roadmap.

b. 30nm and 40nm Semi-dense FeaturesThe templates evaluated in the next three sections were all writ-ten using ZEP520A, a high resolution positive electron beam resist from Nippon Zeon. Depending on the amount of biasing employed and developer used, the dose required at 100 kV can vary from 100 μC/cm2 to over 300 μC/cm2.4 Given the improved electron statistics, it is expected that the LWR would be signifi -

Figure 4. Critical dimension (CD) and LWR for the 30nm and 40nm features after etch for two different wafers. Note the good correlation for both CD and LWR.

Continues on page 6.

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cantly reduced. The fi rst samples that were analyzed consisted of 30nm and 40nm semi-dense patterns that are being used to test addressing schemes for ultra-high density memory.11,12 Por-tions of a typical test structure are shown in Figure 2. Figure 2a shows a SEM image of the template for the 30nm test structures. Figure 2b shows the corresponding imprint of the test structure. The etched SOI fi ns, with apparently very smooth sidewalls, are shown in Figure 2c, and Figure 2d shows a cross section TEM image of the SOI fi ns after additional processing.

SIMAGIS measurements of the imprinted 30nm lines revealed an LWR of 2.43nm, 3σ. After imprinting, wafers were etched. Wafers 1 and 25 were analyzed via CD-SEM, to obtain a more complete statistical view of the variations within a fi eld, from fi eld to fi eld, and from wafer to wafer. Figure 3 shows the LWR and LER results for a single set of 30nm and 40nm lines. LWR was comparable to the starting imprinted LWR, and LER was much less than 2.0nm. Fifteen lines across fi ve fi elds were also measured on wafers 1 and 25, and the results are shown in Figure 4. It is interesting to note that not only does the CD track from line to line, but so does the LWR. At 30nm, the correlation between wafer 1 and 25 is 0.928 for CD and 0.528 for LWR. At 40nm, the correlation between wafer 1 and 25 is 0.907 for CD and 0.954 for LWR. These results lead us to believe that the imprint process yields both highly reproducible CD and LWR from fi eld-to-fi eld.

c. 42nm Dense linesA 42nm design template (supplied by DNP) provided a fi rst op-portunity to track CD and LWR for dense features through etch. Process steps examined included imprint, descum, oxide etch and wet clean. The results of this study are shown in Figure 5. The center eight lines of a ten line pattern were analyzed with respect to CD, LWR and LER. The outer lines were not included

to avoid possible asymmetric etch effects. After imprint, the mean LWR measured 2.8nm. The statistics for the imprinted features are shown in the bottom right hand corner of the image. It is in-teresting to observe that lines 1 and 2 have a difference in LWR of approximately 1nm, yet the scanned image (bottom left) gives no indication of any obvious difference in line roughness. The conclusion drawn is that for these values of LWR, it is not pos-sible to distinguish differences between 2nm and 3nm of LWR, and that better methodologies will be necessary to characterize LWR values less than 2nm, 3σ. As the wafer was processed, LWR remained low, and to within measurement error, no discernable difference in LWR could be detected.

d. 32nm Dense LinesA template containing both dense and semi-dense features rang-ing in size from 32nm to 44nm provided an opportunity to compare LWR between the starting template and the imprinted images. SEM images of the template, provided by DNP, are shown in Figure 6. The graph, to the right of the images, plots CD and LWR as a function of coded CD. CD remained linear (to within 5%) across all feature sizes, and LWR measured 3.1nm and was nominally independent of feature size. Imprint results with this template are shown in Figure 7a. Three imprints of the 32nm patterns had a mean LWR of 2.73nm, closely tracking what was observed in the template. The mean CD for all fi fteen lines was 34.72nm, with a 3σ variation of only 1.62nm.

Two additional templates with minimum CDs of 28nm and 26nm were also imprinted to observe if low values of LWR were maintained. One example is shown in shown in Figure 7b. LWR from the 28nm and 26nm features measured 3.60nm and 3.15nm, respectively.

Figure 5. CD and LWR for 42nm dense lines starting with the imprint process and ending with a clean process after etch. LWR is less than 3nm, and is nearly constant throughout the process.

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Figure 7. a) 32nm imprints from the template shown in Figure 6. LWR of the imprint is comparable to that seen in the template. b) An imprint at 26nm (right image. Image courtesy of Toshiba.). LWR remains low.

e. Analysis of all GB dataFigure 8 shows a plot of LWR versus CD from all of the high resolution features in this study and includes all of the data from templates, imprints, and etched wafers. The data set consisted of one hundred and thirty measurements, and the mean LWR was 2.87nm. The lowest observed LWR was 1.70nm, which is the target value for LWR 32nm DRAM half pitch in 2013. To first order, LWR is independent of both feature size and process step, for the processes em-ployed in this study.

f. VSB Pattern Generation using ZEP520AThe resist processes devel-oped for sections b, c and d were then applied to VSB writers, in order to understand the effect on LWR. For these experiments, an EBM-5000 and the EBM-6000 variable shape beam pattern genera-tors from NuFlare Technology were used to pattern the im-

For the fi rst plate, an EBM-5000 was used to expose the ZEP520A resist. Finished template features are shown in Figure 9. Lines as small as 32nm were resolved. In attempt to improve LWR, an improved resist process was then applied, along with a

ages on the substrates. Sev-eral key specifi cations of the EBM-6000, resulting in improved performance over the EBM-5000 include higher current density (70 A/cm2), astigmatism correction in the subfi elds, optimized variable stage speed control, and improved data handling to increase the maximum shot count limitation.

Figure 6. a) Template SEMs for CDs ranging from 32nm to 44nm. b) CD and LWR as a function of coded CD. CD response is linear, while LWR is independent of feature size.

Continues on page 8.

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thinner (50nm) layer of ZEP520A, and exposed on an EBM-6000. The resist features are shown in Figure 10.13

The LWR from lines defi ned in Figures 9 and 10 was measured and included with the data shown in Figure 8. The result is shown in Figure 11. For the case when the EBM-5000 was used, the LWR varied between 4 and 7nm, which is a signifi cant reduction relative to the LWR obtained using a chemically amplifi ed resist (see Figure 1). It was noted that LWR did increase as feature size approached 32nm. When the improved resist process was applied on the EBM-6000, an additional improvement (of about 2nm) in LWR was obtained for the smallest features measured. The LWR is still higher than what was obtained on Gaussian beam writers, and the process continues to be refi ned in order to further reduce LWR.

4. ConclusionLWR, a critical parameter for determining device performance, has been characterized for the S-FIL process. Advantages of using low sensitivity electron beam resists, such as ZEP520A, and Gaussian beam pattern generators were observed. LWR was characterized on the template, after imprint, and after etch into two different substrates. In the case where Gaussian beam pattern generators were used, LWR was independent of feature size (measured down to 20nm) and process step. Extremely low values were noted: 2.87nm on average, with a minimum of 1.70nm. Improvements in LWR were also noted when using ZEP520A on NuFlare VSB systems. Future work will determine if these low values can be achieved when writing full fi eld templates with high resolution resists on VSB pattern generators.

Figure 9. Dense lines on a template fabricated with a NuFlare EBM-5000 and ZEP520A resist.

Figure 8. LWR as a function of feature size for all lines measured. To fi rst order, LWR is independent of feature size and process step.

Continued from page 7.

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5. AcknowledgmentsThe authors appreciate the support of S. V. Sreenivasan and Mark Melliar-Smith. This work was partially funded by DARPA (AP2C Grant H$001-06-1-0005) and NIST-ATP.

6. References1. M. Colburn, S. Johnson,

M. Stewart, S. Damle, T. Bailey, B. Choi, M. Wedlake, T. Michaelson, S. V. Sreenivasan, J. Ekerdt, and C. G. Willson, Proc. SPIE, Emerging Lithographic Technologies III, 379 (1999).

2. T. C. Bailey, D. J. Resnick, D. Mancini, K. J. Nordquist, W. J.

Figure 10. 33nm and 39nm dense lines imaged using an EBM-6000 and ZEP520A resist. The resist thickness was 50nm. A negative bias of -12nm was also applied in order to improve resolution and reduce LWR.

Figure 11. LWR for all templates exposed using ZEP520A. The LWR obtained from exposures on VSB systems is improved relative to the results obtained on VSB systems using a chemically amplifi ed resist.

Dauksher, E. Ainley, A. Talin, K. Gehoski, J. H. Baker, B. J. Choi, S. Johnson, M. Colburn, S. V. Sreenivasan, J. G. Ekerdt, and C. G. Willson, Microelectronic Engineering 61-62 (2002) 461-467.

3. D. J. Resnick, W. J. Dauksher, D. P. Mancini, K. J. Nordquist, E. S. Ainley, K. A. Gehoski, J. H. Baker, T. C. Bailey, B. J. Choi, S. C. Johnson; S. V. Sreenivasan, J. G. Ekerdt; C. Grant Willson, Proc. SPIE, 4688, 205 (2002).

4. G. M. Schmid, E. Thompson, N. Stacey, D. J. Resnick, D. L. Olynick, E. H. Anderson, Proc. SPIE, 6517, (2007).

5. L. Jeff Myron, E. Thompson, I. McMackin, D. J. Resnick, T. Kitamura, T. Hasebe, S. Nakazawa, T. Tokumoto, E. Ainley, K. Nordquist, and W. J. Dauksher, Proc. SPIE 6151, (2006).

6. M. Colburn, T. Bailey, B. J. Choi, J. G. Ekerdt, S. V. Sreenivasan, Solid State Technology, 67, June 2001.

7. M. Irmscher, J. Butschke, G. Hess; C. Koepernik, F. Letzkus, M. Renno, H. Sailer, H. Schulz, A. Schwersenz, E. Thompson, Proc. SPIE, 6151, (2006).

8. D. J. Resnick, E. Thompson, L. Jeff Myron, G. M. Schmid, Microlithography World, Feb. 2006.

9. A. R. Neureuther, R. F. W. Pease, L. Yuan, K. Baghbani Parizi, H. Esfandyarpour, W. J. Poppe, J. A. Liddle, E. H. Anderson, J. Vac. Sci. Technol. B 24, 1902, Jul/Aug 2006.

12. R. Shenoy, K. Gopalakrishnan, C. Rettner, L. Bozano, R. King, B. Kurdi, and H. Wickramasinghe, Proc. Symp. VLSI Technology, June 2006, pp.140-141.

13. S. Yoshitake , H. Sunaoshi, K. Yasui, H. Kobayashi, T. Sato, O. Nagarekawa , E. Thompson, G. Schmid, D. J. Resnick, to be published in the 27th Annual SPIE Photomask Proceedings, 2007.

10. G. M. Gallatin, Proc. SPIE 5754, 38 (2005).11. K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, R. S. King, Y.

Zhang, B. Kurdi, L. D. Bozano, J. J. Welser, M. E. Rothwell, M. Jurich, M. I. Sanchez, M. Hernandez, P. M. Rice, W. P. Risk, and H. K. Wickramasinghe, IEDM Tech. Dig., 2005, pp. 471-474.

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Industry Briefs

Sponsorship OpportunitiesSign up now for the best Photomask 2008 sponsorship opportunities. Contact:

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BACUS Technical Meetings

BACUS holds technical meetings in the Bay Area approximately every quarter, from 8:30 to 11:30 am. If you are interested in presenting a paper at this meeting, contact Robert (Bob) Naber, Cadence Design Systems, Inc., Tel: 510 814 0972; Email: naber@cadence.com

BACUS Corporate Members

Aprio Technologies, Inc.ASML US, Inc.Brion Technologies, Inc.Coherent, Inc.Corning Inc.Gudeng Precision Industrial Co., Ltd.Hamatech USA Inc.Inko Industrial Corp.JEOL USA Inc.KLA-Tencor Corp.Lasertec USA Inc.Micronic Laser Systems ABRSoft Design Group, Inc.Synopsys, Inc.Toppan Photomasks, Inc.

■ Sometimes Studying the Future Helps in the Present: EUV Research Helps a CNSE Researcher Resolve 193nm Resist Problems

Semiconductor International

Research into the requirements for extreme ultraviolet (EUV) photoresists has helped to solve some of the problems encountered by 193nm lithography technology as it moves into increasingly smaller CDs. Robert Brainard, an associate professor at the College of Nanoscale Science and Engineering (CNSE) at the University at Albany in New York, has investigated a number of new materials for use in EUV and 193nm lithography. The majority of the work that he and his group are conducting is focused on EUV photoresists, the group has also dealt with some of the problems encountered at 193nm; the problems are becoming very similar to those for EUV. “The EUV resist challenges can be summed up succinctly,” Brainard said. “They are the three basic properties—resolution, line-edge roughness and sensitivity. My colleagues and I call it the RLS trade-off. You need all three properties for EUV (and EUV resists) to be successful, and when you improve one, you make another one worse.” Large advances in resist performance will require the pursuit of discontinuous variables, such as synthesis of new materials. Resist performance must then be optimized within the new multidimensional performance surface. (Source: CNSE, University at Albany) “In both cases you want a lower number—you want lower LER and a lower dose (sensitivity is measured in millijoules per square centimeter). This means that the resist is sensitive,” Brainard said. “There are trade-offs for all three different properties. This, in my thinking, is EUV resist’s principal challenge—beating the trade-offs. “We’re learning from EUV technology things that are directly applicable to 193nm. At the 22nm node, whether it is 193nm that gets there or EUV, there are fundamental problems in the understanding of things like acid diffusion that have to be solved by whichever resist technology is used.”

■ Intel is Blazing the Trail When it Comes to EUV Mask Cleans

Semiconductor International

One of the main challenges for EUV lithography is the mask. Since EUV lithography utilizes a mask made up of a multilayer refl ective stack; as opposed to quartz masks which are used for the current imaging nodes (up through 193nm). Sematech’s Surface Preparation and Cleaning Conference in Austin, Texas, provided a forum for Ted Liang of Intel Corp (Santa Clara, CA) to discuss the many challenges that face EUV mask makers. Intel has been working with Dai Nippon Printing Co. Ltd. (DNP, Tokyo) to increase their knowledge of EUV mask cleaning challenges. Intel, Ted Liang, showed that it is possible to clean a ruthenium/multilayer (Ru/ML) surface, but it’s nearly impossible to achieve zero process adders. DNP showed that the adder levels are highly correlated with the type of surface under consideration and its particular adhesion characteristics. Quartz surfaces used in current lithography environments seem to be less sensitive to adders because of its lower tendency to accumulate adders.

Volume 24, Issue 5 Page 11

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2008

Photomask Technology

6-10 October Monterey, California, USAspie.org/photomask

2009

Advanced Lithography

22-27 FebruarySan Jose, California, USAwww.spie.org/al

C a l e n d a r

About the BACUS GroupFounded in 1980 by a group of chrome blank users wanting a single voice to interact with suppliers, BACUS has grown to become the largest and most widely known forum for the exchange of technical information of interest to photomask and reticle makers. BACUS joined SPIE in January of 1991 to expand the exchange of information with mask makers around the world.The group sponsors an informative monthly meeting and newsletter, BACUS News. The BACUS annual Photomask Tech-nology Symposium covers photomask technology, photomask processes, lithography, materials and resists, phase shift masks, inspection and repair, metrology, and quality and manufacturing management.

Join the premier professional organization for mask makers and mask users!

Corporate Membership Benefi ts include: One Voting Member in the SPIE General Membership

Subscription to BACUS News (monthly)

One online SPIE Journal Subscription

Exhibit Space discount of 8% at either the Photomask or Advanced Lithography Symposium

Listed as a Corporate Member in the BACUS Monthly Newsletterspie.org/bacushome

Individual Membership Benefi ts include: Subscription to BACUS News (monthly)

Quarterly technical meetings in the Bay Area

Reduced registration rates at BACUS Photomask Technology annual meeting

Eligibility to hold offi ce on BACUS Steering Committee

spie.org/bacushome

You are invited to submit events of interest for this calendar. Please send to lindad@spie.

org; alternatively, email or fax to SPIE.

SPIE is an international society advancing light-based technologies.

International HeadquartersP.O. Box 10, Bellingham, WA 98227-0010 USATel: +1 888 504 8171 or +1 360 676 3290Fax: +1 360 647 1445customerservice@spie.org • SPIE.org

Shipping Address1000 20th St., Bellingham, WA 98225-6705 USA

2 Alexandra Gate, Ffordd Pengam, Cardi�, CF24 2SA, UKTel: +44 29 20 89 4747Fax: +44 29 20 89 4750spieeurope@spieeurope.org • www.spieeurope.org

SPIE Lithography Asia - Taiwan

4-6 November Taipei,Taiwanwww.spie.org/tlAbstracts due: 26 May 2008

SPIE TV presents:

Optical Microlithography Webcast - SPIE Advanced Lithography 2008