Basic Concept of HDL - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_92second/ppt/20040305_Basic Concept... · Graduate Institute of Electronics Engineering, NTU Basic Concept

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Graduate Institute of Electronics Engineering, NTU

Basic Concept of HDLBasic Concept of HDL

Lecturer: Huai-Yi Hsu (許槐益)Date: 2004.03.05


pp. 2Huai-Yi HsuBasic Concept 2004.03.05

OutlineOutlineHierarchical Design MethodologyBasic Concept of Verilog HDLSwitch Level Modeling Gate Level ModelingSimulation & Verification Tools



What is What is VerilogVerilog HDL ?HDL ?Hardware Description LanguageMixed level modeling

BehavioralAlgorithmic ( like high level language)Register transfer (Synthesizable)

StructuralGate (AND, OR ……)Switch (PMOS, NOMS, JFET ……)

Single language for design and simulationBuilt-in primitives and logic functionsUser-defined primitivesBuilt-in data typesHigh-level programming constructs



Hierarchical Modeling ConceptHierarchical Modeling ConceptUnderstand top-down and bottom-up design methodologiesExplain differences between modules and module instances in VerilogDescribe four levels of abstraction



TopTop--down Design Methodologydown Design MethodologyWe define the top-level block and identify the sub-blocks necessary to build the top-level block.We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided.

Top levelblock

subblock 2

subblock 3

subblock 4

subblock 1

leafcell

leafcell

leafcell

leafcell

leafcell

leafcell

leafcell

leafcell



BottomBottom--up Design Methodologyup Design MethodologyWe first identify the building block that are available to us.We build bigger cells, using these building blocks.These cells are then used for higher-level blocks until we build the top-level block in the design.

Top levelblock

macrocell 2

macrocell 3

macrocell 4

macrocell 1

leafcell

leafcell

leafcell

leafcell

leafcell

leafcell

leafcell

leafcell



Example: 16Example: 16--bit Adderbit Adder

Add_full

Add_half norf201 invf101

M1 M2

xor nand notnotnandxor

M3 M4

Add_rca_16

Add_rca_4Add_rca_4Add_rca_4 Add_rca_4

M1

Add_fullAdd_fullAdd_full

M2 M3 M4

M1 M2 M3 M4

Add_half

[HW]



Design EncapsulationDesign EncapsulationEncapsulate structural and functional details in a module

Encapsulation makes the model available for instantiation in other modules

module <Module Name> (<PortName List>);// Structural part

<List of Ports><Lists of Nets and Registers><SubModule List> <SubModule Connections>

// Behavior part<Timing Control Statements>

<Parameter/Value Assignments><Stimuli><System Task>

endmodule



InstancesInstancesA module provides a template from which you can create actual objects.When a module is invoked, Verilog creates a unique object from the template.Each object has its own name, variables, parameters and I/O interface.



Hierarchical Design ExampleHierarchical Design ExampleModel complex structural detail by instantiating modules within modules

a

b c_out

sumAdd_half_0_delay

a

b c_out

sumAdd_half_0_delay

(a⊕ b)⊕ c_in

(a + b) c_in + ab

(a⊕ b) c_ina

b

c_in sum

c_out

ab

(a⊕b)

Add_full_0_delay

w1

w2

w3

MODELING TIP

Use nested module instantiations to create a top-downdesign hierarchy.

module Add_full_0_delay (sum, c_out, a, b, c_in); input a, b, c_in; output c_out, sum; wire w1, w2, w3;

Add_half_0_delay M1 (w1, w2, a, b); Add_half_0_delay M2 (sum, w3, c_in, w1); or (c_out, w2, w3);

endmodule

module instancename

MODELING TIP

The ports of a module may be listed in any order.The instance name of a module is required.



VerilogVerilog Language RulesLanguage RulesVerilog is a case sensitive language (with a few exceptions)Identifiers (space-free sequence of symbols)

upper and lower case letters from the alphabetdigits (0, 1, ..., 9)underscore ( _ )$ symbol (only for system tasks and functions)Max length of 1024 symbols

Terminate lines with semicolon ;Single line comments:

// A single-line comment goes hereMulti-line comments:

/* Do not /* nest multi-line comments*/ like this */



Language ConventionsLanguage ConventionsCase-sensitivity

Verilog is case-sensitive.Some simulators are case-insensitiveAdvice: - Don’t use case-sensitive feature!Keywords are lower case

Different names must be used for different items within the same scopeIdentifier alphabet:

Upper and lower case alphabeticalsdecimal digitsunderscore



Language Conventions (contLanguage Conventions (cont’’d)d)Maximum of 1024 characters in identifierFirst character not a digitStatement terminated by ;Free format within statement except for within quotesComments:

All characters after // in a line are treated as a commentMulti-line comments begin with /* and end with */

Compiler directives begin with // synopsysBuilt-in system tasks or functions begin with $Strings enclosed in double quotes and must be on a single line



VerilogVerilog Basis CellBasis CellVerilog Basis Components

parameter declarationsnets or reg declarationsport declarationsContinuous assignmentsModule instantiationsGate instantiationsFunction definitionsalways blockstask statements



Port DeclarationPort DeclarationThree port types

Input portinput a;

Output portoutput b;

Bi-direction portinout c;

net

net

netnet

input output

inoutreg or net reg or net

module



Data TypesData Typesnets are further divided into several net types

wire, wand, wor, tri, triand, trior, supply0, supply1registers - stores a logic value - reginteger - supports computation 32-bits signedtime - stores time 64-bit unsignedreal - stores values as real numbersrealtime - stores time values as real numbersevent – an event data type

Wires and registers can be bits, vectors, and arrays



Integer, Real, & Time Integer, Real, & Time integer counter;

initial counter = -1;real delta;

initial delta = 4e10;time sim_time;

initial sim_time = $time;



Data TypesData TypesNets ( wire or reg (in combinational always block)

Connects between structural elementsMust be continuously driven by

Continuous assignment (assign)Module or gate instantiation (output ports)

Default initial value for a wire is “Z”

Registers ( reg (in sequential always block) )Represent abstract data storage elementsUpdated at an edge trigger event and holds its value until another edge trigger event happensDefault initial value for a wire is “X”



Net TypesNet TypesThe most common and important net types

wire and trifor standard interconnection wires

supply 1 and supply 0

Other wire typeswand, wor, triand, and trior

for multiple drivers that are wired-anded and wired-oredtri0 and tri1

pull down and pull uptrireg

for net with capacitive storageIf all drivers at z, previous value is retained



Register TypesRegister Typesreg

any size, unsignedinteger (not synthesizable)

integet a,b; // declaration32-bit signed (2’s complement)

time (not synthesizable)64-bit unsigned, behaves like a 64-bit reg$display(“At %t, value=%d”,$time,val_now)

real, realtime (not synthesizable)real c,d; //declaration64-bit real numberDefaults to an initial value of 0



Wire & Wire & RegRegwire(wand, wor, tri)

Physical wires in a circuitCannot assign a value to a wire within a function or a begin…..end block

A wire does not store its value, it must be driven byby connecting the wire to the output of a gate or moduleby assigning a value to the wire in a continuous assignment

An un-driven wire defaults to a value of Z (high impedance).Input, output, inout port declaration -- wire data type (default)



Wire & Wire & RegRegreg

A variable in VerilogUse of “reg” data type is not exactly synthesized to a really register.Use of wire & reg

When use “wire” usually use “assign” and “assign” does not appear in “always” blockWhen use “reg” only use “a=b” , always appear in “always” block

module test(a,b,c,d);input a,b;output c,d;reg d;assign c=a;always @(b)

d=b;endmodule

module test(a,b,c,d);input a,b;output c,d;reg d;assign c=a;always @(b)

d=b;endmodule



Wired LogicWired LogicThe family of nets includes the types wand and wor

A wand net type resolves multiple driver as wired-and logic A wor net type resolves multiple drivers as wired-or logic

The family of nets includes supply0 and supply1supply0 has a fixed logic value of 0 to model a ground connection supply1 has a fixed logic value of 1 to model a power connection



Data Type Data Type -- ExamplesExamplesreg a; // scalar registerwand b; // scalar net of type “wand”reg [3:0] c; // 4-bit registertri [7:0] bus; // tri-state 8-bit busreg [1:4] d; // 4-bittrireg (small) store; // specify logical strength (rare used)

a

b

c

ZX10Z

XXXXX

1X1X1

0XX00

ZX10

ZX10Z

XXX0X

1X101

00000

ZX10

ZX10Z

XX1XX

11111

0X100

ZX10

wire/tri truth table wand/triand wor/trior



VectorVectorwire and reg can be defined vector, default is 1bitvector is multi-bits elementFormat: [High#:Low#] or [Low#:High#]Using range specify part signals

wire a; // scalar net variable, defaultwire [7:0] bus; // 8-bit busreg clock; // scalar register, defaultreg [0:23] addr; // Vector register, virtual address 24 bits wide

bus[7] // bit #7 of vector busbus[2:0] // Three least significant bits of vector bus

// using bus[0:2] is illegal because the significant bit should// always be on the left of a range specification

addr[0:1] // Two most significant bits of vector addr



ArrayArrayArrays are allowed in Verilog for reg, integer, time, and vector register data types.Multidimensional array are not permitted in Verilog.

integer count[0:7]; // An array of 8 count variablesreg bool[31:0]; // Array of 32 one-bit Boolean register variablestime chk_ptr[1:100]; // Array of 100 time checkpoint variablesreg [4:0] port_id[0:7]; // Array of 8 port_id, each port_id is 5 bits wideinteger matrix[4:0][4:0] // Illegal declaration

count[5] // 5th element of array of count variableschk_ptr[100] // 100th time check point valueport_id[3] // 3rd element of port_id array. This is a 5-bit value



MemoriesMemoriesIn digital simulation, one often needs to model register files, RAMs, and ROMs.Memories are modeled in Verilog simply as an array of registers.Each element of the array is known as a word, each word can be one or more bits.It is important to differentiate between

n 1-bit registersOne n-bit register

reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit wordsreg [7:0] mem1byte[0:1023]; // Memory mem1byte with 1K 8-bit words

mem1bit[255] // Fetches 1 bit word whose address is 255Mem1byte[511] // Fetches 1 byte word whose address is 511



StringsStringsString: a sequence of 8-bits ASCII values

Special characters\n newline \t tab character\\ \ character \” “ character%% % character \abc ASCII code

module string;reg [8*14:1] strvar;initial

beginstrvar = “Hello World”; // stored as 000000486561…726c64strvar = “Hello World!!”; // stored as 00486561…726c642121

endendmodule



FourFour--valued Logicvalued LogicVerilog’s nets and registers hold four-valued data

0 represent a logic zero or false condition1 represent a logic zero or false conditionz

Output of an undriven tri-state driver –high-impedance valueModels case where nothing is setting a wire’s value

xModels when the simulator can’t decide the value – uninitialized or unknown logic value

Initial state of registersWhen a wire is being driven to 0 and 1 simultaneouslyOutput of a gate with z inputs



Logic SystemLogic SystemFour values: 0, 1, x or X, z or Z // Not case sensitive here

The logic value x denotes an unknown (ambiguous) valueThe logic value z denotes a high impedance

Primitives have built-in logicSimulators describe 4-value logic (see Appendix A in text)

ab

y

0 1

x

a

b

y

x

xx

z

z z z zx x x x

0 1 X Z0 0 0 0 01 0 1 X XX 0 X X XZ 0 X X X



Resolution of Contention Between DriversResolution of Contention Between Drivers

The value on a wire with multiple drivers in contention may be x



Logic Strength LevelsLogic Strength LevelsTypes of strengths

Charge strength: trireg (large>medium>small)Drive strength: <Net> (supply>strong>pull>weak)

Syntax

Strength level

<NetType> <Strength> <Range> <Delay> <Variables>;trireg (large) [1:4] #5 c1;

weakest strongest

highz small medium weak large pull strong supply



Number RepresentationNumber RepresentationFormat: <size>’<base_format><number>

<size> - decimal specification of number of bitsdefault is unsized and machine-dependent but at least 32 bits

<base format> - ' followed by arithmetic base of number<d> <D> - decimal - default base if no <base_format> given<h> <H> - hexadecimal<o> <O> - octal<b> <B> - binary

<number> - value given in base of <base_format>_ can be used for reading clarityIf first character of sized, binary number 0, 1, x or z, will extend 0, 1, x or z (defined later!)



Number RepresentationNumber RepresentationExamples:

6’b010_111 gives 0101118’b0110 gives 000001104’bx01 gives xx0116’H3AB gives 000000111010101124 gives 0…00110005’O36 gives 1110016’Hx gives xxxxxxxxxxxxxxxx8’hz gives zzzzzzzz



Net ConcatenationsNet ConcatenationsA easy way to group nets

Sign extension{{8{byte[7]}},byte}

8‘b01010101{4{2‘b01}}

{a, b[3], b[2], b[1], c, 1’b1, 1’b0}{a,b[3:1],c,2’b10}

{b[7], b[6], b[5], b[4], c[3], c[2], c[1], c[0]}{b[7:4],c[3:0]}

{cout, sum}{cout, sum}

MeaningsRepresentation



Parameter DeclarationParameter DeclarationParameters are not variables, they are constants.Typically parameters are used to specify delays and width of variablesExamples

module var_mux(out, i0, i1, sel);parameter width = 2, delay = 1;output [width-1:0] out;input [width-1:0] i0, i1;input sel;

assign #delay out = sel ? I1 : i0;endmodule

•If sel = 1, then i1 will be assigned to out;•If sel = 0, then i0 will be assigned to out;



Overriding the Values of ParametersOverriding the Values of ParametersModule instance parameter value assignment.Cannot skip any parameter assignment even you do not want to reassign it.

module top;……wire [1:0] a_out, a0, a1;wire [3:0] b_out, b0, b1;wire [2:0] c_out, c0, c1;

var_mux U0(a_out, a0, a1, sel);var_mux #(4,2) U1(b_out, b0, b1, sel);var_mux #(3, ) U2(c_out, c0, c1, sel);……

endmodule

The order of assign of parametersfollows the order of declaration of Parameters in the module.

You cannot skip the delay parameter assignment.



Overriding the Values of ParametersOverriding the Values of ParametersYou can use defparam to group all parameter value override assignment in one module.

module top;……wire [1:0] a_out, a0, a1;wire [3:0] b_out, b0, b1;wire [2:0] c_out, c0, c1;

var_mux U0(a_out, a0, a1, sel);var_mux U1(b_out, b0, b1, sel);var_mux U2(c_out, c0, c1, sel);……

endmodule

module annotate;defparam

top.U0.width = 2;top.U0.delay = 1;top.U1.width = 4;top.U1.delay = 2;top.U2.width = 3;top.U2.delay = 1;

endmodule



Gate and Switch Level ModelingGate and Switch Level ModelingPrimitives: bottom level of the hierarchy

Verilog Gate Level PrimitivesUser-defined Primitives (UDP): described by truth table

Conventional modulesBehavior statementsStructural statementsSwitch Level Modeling (using transistors)

Delay SpecificationSpecify gate delaySpecify module path delay



VerilogVerilog BuiltBuilt--in Primitivesin Primitives

andnandornorxorxnor

bufnotbufif0bufif1notif0notif1

nmospmoscmostrantranif0tranif1

rnmosrpmosrcmosrtranrtranif0rtranif1

pulluppulldown

IdealMOS switch

Resistivegates



MOS SwitchesMOS SwitchesTwo types of MOS switches can be defined with the keywords, nmosand pmos

nmos is used to model NMOS transistorsnmos n1(out, data, control);

pmos is used to model PMOS transistorspmos p1(out, data, control);

data dataout out

control controlNMOS transistor PMOS transistor

ZZZZZ

XXXZX

HH1Z1

LL0Z0

ZX10CD

ZZZZZ

XXZXX

HHZ11

LLZ00

ZX10CD

H: stands for 1 or zL: stands for 0 or z



CMOS SwitchesCMOS SwitchesCMOS switches are declared with the keyword cmos.A cmos device can be modeled with a nmos and a pmos device.

cmos c1(out, data, ncontrol, pcontrol);

The cmos gate is essentially a combination of two gates: one nmos and one pmos.

nmos n1(out, data, ncontrol);pmos p1(out, data, pcontrol);

data out

ncontrol

pcontrol

CMOS



Bidirectional SwitchesBidirectional SwitchesNMOS, PMOS, CMOS gates conduct from drain to source.It is important to have devices that conduct in both directions.In such cases, signals on either side of the device can be the driver signal.Bidirectional switches are typically used to provide isolation between buses or signals.

tran t1(inout1, inout2);tranif0 t2(inout1, inout2, control);tranif1 t3(inout1, inout2, control);

tran tranif1 tranif0

inout1 inout2 inout1 inout2control

inout1 inout2control



Power and GroundPower and GroundThe power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when transistor-level circuits are designed.Supply1 are equivalent to Vdd in circuits and place a logical 1 on a net.Supply0 are equivalent to ground or Vss in circuits and place a logical 0 on a net.

supply1 vdd;supply0 gnd;

assign a = vdd; // connect a to vddassign b = gnd; // connect b to gnd



Resistive SwitchesResistive SwitchesResistive switches have the same syntax as regular switches.Resistive devices have a high source-to-drain impedance. Regular switches have a low source-to-drain impedance.Resistive switches reduce signal strengths when signals pass through. Regular switches retain strength levels of signals from input to output.

HighHigh

SmallSmall

SmallMedium

MediumLarge

MediumWeak

WeakPull

PullStrong

PullSupply

Output StrengthInput Strength



Switches ExampleSwitches Examplea

bout

out

ba

gnd

pwr

// Define our own nor gate: nor_swmodule nor_sw (out, a, b);

output out;input a, b;

// internal wireswire c;

// set up power and ground linessupply1 pwr;supply0 gnd;

//instantiate pmos switchespmos (c, pwr, b);pmos (out, c, a);

//instantiate nmos switchesnmos (out, gnd, a);nmos (out, gnd, b);

endmodule



Primitives & UDPPrimitives & UDPPrimitives are simple modulesVerilog build-in primitive gate

not, buf:Variable outputs, single input (last port)

and, or, xor, nand, nor, xnor:Single outputs (first port), variable inputs

User defined primitive (UDP)Single output (first port), variable inputsThe function is specified by a truth tableZ state is not allowed



TruthTruth--Tables Models and UserTables Models and User--Defined PrimitivesDefined Primitives

Built-in primitives are for simple combinational logic gates and CMOS transistors

Primitives are memory efficient and simulate fast (good for ASIC libraries)

User-defined primitives accommodate combinational and sequential logic

Scalar output and multiple scalar inputs

Arrange inputs columns of truth table in same order as ports

Put output in last column, separated by :

Use a UDP like a built-in primitive

Table is searched top to bottom until match is found

z may not be used in table (z in simulation is treated as x)

No match results in propagation of x

See web site for more details



Example UDPExample UDPselect

1

0

mux_prim mux_out

primitive mux_prim (mux_out, select, a, b);output mux_out;input select, a, b; table

// select a b : mux_out0 0 0 : 0 ; // Order of table columns = port order of inputs0 0 1 : 0 ; // One output, multiple inputs, no inout0 0 x : 0 ; // Only 0, 1, x on input and output0 1 0 : 1 ; // A z input in simulation is treated as x0 1 1 : 1 ; // by the simulator 0 1 x : 1 ; // Last column is the output

// select a b : mux_out1 0 0 : 0 ; 1 1 0 : 0 ; 1 x 0 : 0 ;1 0 1 : 1 ; 1 1 1 : 1 ; 1 x 1 : 1 ;x 0 0 : 0 ; // Reduces pessimismx 1 1 : 1 ;

endtable // Note: Combinations not explicitly specified will drive ‘x’endprimitive // under simulation.



Alternative modelAlternative model

table// Shorthand notation:// ? represents iteration of the table entry over the values 0,1,x.// i.e., don't care on the input

select a b : mux_out

0 0 ? : 0 ; // ? = 0, 1, x shorthand notation.0 1 ? : 1 ;

1 ? 0 : 0 ; 1 ? 1 : 1 ;

? 0 0 : 0 ; ? 1 1 : 1 ;

endtable



UDPS FOR Sequential LogicUDPS FOR Sequential LogicOutput is viewed as next state Insert a column for the present state truth Declare output to have type reg

MODELING TIPThe output of a sequential user-defined primitive must bedeclared to have type reg.



Example: Transparent LatchExample: Transparent Latch

primitive latch_rp (q_out, enable, data);output q_out;input enable, data;reg q_out;

table// enable data state q_out/next_state

1 1 : ? : 1 ;1 0 : ? : 0 ;0 ? : ? : - ;

// Above entries do not deal with enable = x.// Ignore event on enable when data = state:

x 0 : 0 : - ;x 1 : 1 : - ;

// Note: The table entry '-' denotes no change of the output.endtable

endprimitive



Example: DExample: D--Type FlipType Flip--FlopFlopNotation for rising edge transition: (01), (0x), (x1) Notation for falling edge transition: (10), 1x), (x0)

d_prim1

q_out

clock

data

primitive d_prim1 (q_out, clock, data);output q_out;input clock, data;reg q_out;table

// clk data : state : q_out/next_state (01) 0 : ? : 0 ; // Rising clock edge(01) 1 : ? : 1 ;(0?) 1 : 1 : 1 ;

(?0) ? : ? : - ; // Falling or steady clock edge

? (??) : ? : - ; // Steady clock, ignore data transitionsendtable

endprimitive



Example: JK-Type Flip-FlopLevel-sensitive and edge-sensitive behavior can be mixed in a UDP Place level-sensitive behavior a the top of the table

q_out

clk

j

k

preset

clear

J-K functionality:- preset and clear override clock- no change if j=0, k=0- drive to 1 if j=1, k=0- drive to 0 if j=0, k=1- toggle if j=1, k=1



primitive jk_prim (q_out, clk, j, k, preset, clear);output q_out;input clk, j, k, preset, clear;reg q_out;table

// clk j k pre clr state q_out/next_state// Preset Logic

? ? ? 0 1 : ? : 1 ; ? ? ? * 1 : 1 : 1 ;

// Clear Logic? ? ? 1 0 : ? : 0 ;? ? ? 1 * : 0 : 0 ;

// Normal Clocking// clk j k pre clr state q_out/next_state

r 0 0 0 0 : 0 : 1 ;r 0 0 1 1 : ? : - ;r 0 1 1 1 : ? : 0 ; r 1 0 1 1 : ? : 1 ;r 1 1 1 1 : 0 : 1 ;r 1 1 1 1 : 1 : 0 ;f ? ? ? ? : ? : - ;

// j and k cases// clk j k pre clr state q_out/next_state

b * ? ? ? : ? : - ;b ? * ? ? : ? : - ;

// Reduced pessimismp 0 0 1 1 : ? : - ;p 0 ? 1 ? : 0 : - ;p ? 0 ? 1 : 1 : - ;(?0) ? ? ? ? : ? : - ;(1x) 0 0 1 1 : ? : - ;(1x) 0 ? 1 ? : 0 : - ;(1x) ? 0 ? 1 : 1 : - ;x * 0 ? 1 : 1 : - ;x 0 * 1 ? : 0 : - ;

endtableendprimitive Note: * denotes any transition, and is equivalent to (??)

ACCESS IC LAB


Timing and DelaysTiming and Delays



Timing and DelayTiming and DelayFunctional verification of hardware is used to verify functionality of the designed circuit.However, blocks in real hardware have delays associated with the logic elements and paths in them.Therefore, we must also check whether the circuit meets the timing requirements, given delay specifications for the blocks.



Delay Specification in PrimitivesDelay Specification in PrimitivesDelay specification defines the propagation delay of that primitive gate.

not #10 (out,in);



Delay Specification in PrimitivesDelay Specification in PrimitivesVerilog supports (rise, fall, turn-off) delay specification.



Delay Specification in PrimitivesDelay Specification in PrimitivesAll delay specification in Verilog can be specified as (minimum : typical : maximum) delayExamples

(min:typ:max) delay specification of all transitionor #(3.2:4.0:6.3) U0(out, in1, in2);

(min:typ:max) delay specification of RISE transition and FALL transition

nand #(1.0:1.2:1.5,2.3:3.5:4.7) U1(out, in1, in2);(min:typ:max) delay specification of RISE transition, FALL transition, and turn-off transition

bufif1 #(2.5:3:3.4,2:3:3.5,5:7:8) U2(out,in,ctrl);



Types of Delay ModelsTypes of Delay ModelsDistributed Delay

Specified on a per element basicDelay value are assigned to individual in the circuit

ab

c

d

e

f

out

#5

#7

#4

module and4(out, a, b, c, d);… …and #5 a1(e, a, b);and #7 a2(f, c, d);and #4 a3(out, e, f);

endmodule



Types of Delay ModelsTypes of Delay ModelsLumped Delay

Specified on a per module basicThey can be specified as a single delay on the output gate of the moduleThe cumulative delay of all paths is lumped at one location

ab

c

d

e

f

out#11

module and4(out, a, b, c, d);… …and a1(e, a, b);and a2(f, c, d);and #11 a3(out, e, f);

endmodule



Types of Delay ModelsTypes of Delay ModelsPin-to-Pin Delay

Delays are assigned individually to paths from each input to each output.Delays can be separately specified for each input/output path.

ab

c

d

e

f

out

Path a-e-out, delay = 9Path b-e-out, delay =9Path c-f-out, delay = 11Path d-f-out, delay = 11



Path Delay ModelingPath Delay Modeling

Specify blocksAssign pin-to-pin timing delay across module pathSet up timing checks in the circuitsDefine specparam constanys

module and4(out, a, b, c, d);… …// specify block with path delay statementsspecify

(a => out) = 9;(b => out) = 9;(c => out) = 11;(d => out) = 11;

endspecify

// gate instantiationsand a1(e, a, b);and a2(f, c, d);and a3(out, e, f);

endmodule



Parallel/Full ConnectionParallel/Full Connection

(a[0] => out[0]) = 9;(a[1] => out[1]) = 9;(a[2] => out[2]) = 9;(a[3] => out[3]) = 9;

(a => out) = 9;

(a => out) = 9;(b => out) = 9;(c => out) = 11;(d => out) = 11;

(a,b *> out) = 9;(c,d *> out) = 11;



SpecparamSpecparam StatementStatementSpecial parameters can be declared for use inside a specify block.Instead of using hardcoded delay numbers to specify pin-tp-pin delays

module and4(out, a, b, c, d);… …// specify block with path delay statementsspecifyspecparam delay1 = 9;specparam delay2 = 11;

(a,b *> out) = delay1;(c,d *> out) = delay2;

endspecify… …

endmodule



Rise, Fall, and TurnRise, Fall, and Turn--off Delaysoff DelaysPin-to-pin timing can also be expressed in more detail by specifying rise, fall, and turn-off delay values

// specify one delay statementsspecparam t_delay = 9;(clk => q) = t_delay;

// specify two delay statementsspecparam t_rise = 9;specparam t_fall = 13;

(clk => q) = (t_rise, t_fall);

// specify three delay statementsspecparam t_rise = 9;specparam t_fall = 13;specparam t_turnoff = 11;

(clk => q) = (t_rise, t_fall, t_turnoff);

// specify six delay statementsspecparam t_01= 9, t_10 = 13;specparam t_0z = 11, t_z1 = 9;specparam t_1z = 11, t_z0 = 13;

(clk => q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0);

// specify twelve delay statementsspecparam t_01= 9, t_10 = 13;specparam t_0z = 11, t_z1 = 9;specparam t_1z = 11, t_z0 = 13;specparam t_0x= 9, t_x1 = 13;specparam t_1x = 11, t_x0 = 9;specparam t_xz = 11, t_zx = 13;

(clk => q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0,t_0x, t_x1, t_1x, t_x0, t_xz, t_zx);



Min, Max, and Typical DelaysMin, Max, and Typical DelaysMin, max, and typical delay value were discussed earlier for gatesCan also be specified for pin-to-pin delays.

// specify two delay statementsspecparam t_rise = 8:9:10;specparam t_fall = 12:13:14;specparam t_turnoff = 10:11:12

(clk => q) = (t_rise, t_fall, t_turnoff);



Timing Checks Timing Checks setup and hold checks

setuptime

holdtime

clock

data

specify $setup(data, posedge clock, 3);

endspecify

specify $hold(posedge clock, data, 5);

endspecify



Timing ChecksTiming ChecksWidth check

width ofthe pulse

clock

specify $width(posedge clock, 6);

endspecify



Structural ModelsStructural ModelsVerilog primitives encapsulate pre-defined functionality of common logic gatesThe counterpart of a schematic is a structural model composed of VerilogprimitivesModel structural detail by instantiating and connecting primitives

module AOI_str (y_out, x_in1, x_in2, x_in3, x_in4, x_in5); output y_out; input x_in1, x_in2, x_in3, x_in4, x_in5; wire y1, y2;

nor (y_out, y1, y2); and (y1, x_in1, x_in2); and (y2, x_in3, x_in4, x_in5);endmodule

y1

y2

x_in1x_in2

x_in3x_in4

y_out

module name module ports

port modes

instantiatedprimitives

primaryinputs

primaryoutput

AOI_str

x_in5

internal wiresestablishconnectivity



Structural ConnectivityStructural ConnectivityWires in Verilog establish connectivity between primitives and/or modulesData type: nets (Example: wire)The logic value of a wire (net) is determined dynamically during simulation by what is connected to the wire.An undeclared identifier is treated by default as a wireUse nets to establish structural connectivity

Port connection by nameAdd_half_0_delay M1(.b(b),.c_out(w2),.a(a),.sum(w1));

Port connection by placeAdd_half_0_delay M1(w1, w2, a, b);

ACCESS IC LAB


Simulation & VerificationSimulation & Verification



Test Methodology Test Methodology Task: systematically verify the functionality of a model. Approaches: Simulation and/or formal verification Simulation: (1) detect syntax violations in source code (2) simulate behavior (3) monitor results

Unit_Under_Test (UUT)

StimulusGenerator

ResponseMonitor

Design_Unit_Test_Bench (DUTB)

D

Q

QSET

CLR



Components of a SimulationComponents of a Simulation

Stimulus Block

Design Block

OutputResults

InputPatterns

Dummy Top Block

DesignBlock

StimulusBlock

OutputResults

InputPatterns



EventEvent--Driven SimulationDriven SimulationA change in the value of a signal (variable) during simulation is referred to as an event Spice-like analog simulation is impractical for VLSI circuits Event-driven simulators update logic values only when signals change



Inertial DelayInertial Delay

y_out1x_in1

x_in2

tpd = 2

tpd = 2 y_out2

∆ = 1

∆ = 6

3

3

Descheduled

9 115

5

x_in1

x_in2

tsim = 4

Not scheduled

Note: The falling edge of x_in1 occurs before the response to the rising edge occurs.



TestbenchTestbench Template Template Consider the following template as a guide for simple testbenches:

module t_DUTB_name (); // substitute the name of the UUTreg …; // Declaration of register variables for primary inputs of the UUTwire …; // Declaration of primary outputs of the UUTparameter time_out = // Provide a value

UUT_name M1_instance_name ( UUT ports go here);

initial $monitor ( ); // Specification of signals to be monitored and displayed as text

initial #time_out $stop; // (Also $finish) Stopwatch to assure termination of simulation

initial // Develop one or more behaviors for pattern generation and/or// error detection

begin// Behavioral statements generating waveforms // to the input ports, and comments documenting// the test. Use the full repertoire of behavioral // constructs for loops and conditionals.

endendmodule



Example: Example: TestbenchTestbenchmodule t_Add_half();

wire sum, c_out;reg a, b; // Storage containers for stimulus waveforms

Add_half_0_delay M1 (sum, c_out, a, b); //UUT

initial begin // Time Out#100 $finish; // Stopwatchend

initial begin // Stimulus patterns#10 a = 0; b = 0; // Statements execute in sequence#10 b = 1; #10 a = 1;#10 b = 0;

endendmodule



Behaviors for Abstract Models Behaviors for Abstract Models Verilog has three types of behaviors for composing abstract models of functionality

Continuous assignment (Keyword: assign) -- later Single pass behavior (Keyword: initial) -- Note: only use in testbenchesCyclic behavior (Keyword: always) -- later

Single pass and cyclic behaviors execute procedural statements like a programming language The procedural statements execute sequentially A single pass behavior expires after the last statement executesA cyclic behavior begins executing again after the last statement executes



Signal GeneratorsSignal GeneratorsUse cyclic behaviors to describe stimulus generators Statements in a behavior may be grouped in begin … end blocks Execution begins at tsim = 0 # delay control operator temporarily suspends execution of a behavior The operator = denotes procedural assignment (also called blocking assignment)

MODELING TIP

Use procedural assignments to describe stimulus patterns ina testbench.



Simulation ResultsSimulation Results

MODELING TIP

A Verilog simulator assigns an initial value of x to allvariables.



Propagation Delay Propagation Delay Gate propagation delay specifies the time between an input change and the resulting output change Transport delay describes the time-of-flight of a signal transition Verilog uses an inertial delay model for gates and transport delay for nets Inertial delay suppresses short pulses (width less than the propdelay value)

MODELING TIP

All primitives and nets have a default propagation delay of 0.



Example: Propagation Delay Example: Propagation Delay Unit-delay simulation reveals the chain of events

module Add_full (sum, c_out, a, b, c_in);output sum, c_out;input a, b, c_in;wire w1, w2, w3;

Add_half M1 (w1, w2, a, b);Add_half M2 (sum, w3, w1, c_in);or #1 M3 (c_out, w2, w3);

endmodule

module Add_half (sum, c_out, a, b);output sum, c_out;input a, b;

xor #1 M1 (sum, a, b); // single delay value formatand #1 M2 (c_out, a, b); // others are possible

endmodule



Simulation with delaySimulation with delay



Simulation with Standard CellsSimulation with Standard Cells`timescale 1ns / 1 ps // time scale directive for units and resolution module Add_full_ASIC (sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire w1, w2, w3; wire c_out_bar; Add_half_ASIC M1 (w1, w2, a, b); Add_half_ASIC M2 (sum, w3, w1, c_in); norf201 M3 (c_out_bar, w2, w3); invf101 M4 (c_out, c_out_bar); endmodule

module Add_half_ASIC (sum, c_out, a, b); output sum, c_out; input a, b; wire c_out_bar; xorf201 M1 (sum, a, b); // Standard cells - down load from web page nanf201 M2 (c_out_bar, a, b); invf101 M3 (c_out, c_out_bar); endmodule



System TasksSystem TasksDisplaying information

$display(“ID of the port is %b”, port_id);ID of the port is 00101

Monitoring information$monitor($time, “Value of signals clk = %b rst = %b”, clk, rst);

0 Value of signals clk = 0 rst = 15 Value of signals clk = 1 rst = 110 Value of signals clk = 0 rst = 0

Stopping and finishing in a simulation$stop; // provided to stop during a simulation$finish; // terminates the simulator



Compiler DirectivesCompiler DirectivesThe `define directive is used to define text macros

The ìnclude directive allows you to include entire contents of a Verilog source file

`timescale <reference_time_unit>/<time_precision>

`define WORD_SIZE 32 // Used as `WORD_SIZE in the code`define STOP $stop; // define an alias`define WORD_REG reg[31:0] // define a 32-bit register

ìnclude header.vìnclude submodule.v

`timescale 1 ns / 10 ps`timescale 100 ns / 1ns



SummarySummaryUnderstand switch level modelingUnderstand gate level modelingSpecify timing delayFunction simulationTiming simulation



Homework #1Homework #1Try to build your design by using gate-levelCheck your syntax!! And record your miss errors!! Writing your testbench to verify your designSimulate and Verify your designOptional:

Simulation with delay information on gate-level

Design example: 16-bits Adder, 4-bits multiplier (booth)Counter, Clock generator (OSC)

Documents

Basic Concept of HDL - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_92second/ppt/20040305_Basic Concept... · Graduate Institute of Electronics Engineering, NTU Basic Concept