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Chapter 3

Boolean Algebra and Combinational Logic

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Logic Gate Network

• Two or more logic gates connected together.

• Described by truth table（真值表）, logic diagram（Schematic電路圖）, or Boolean expression（布林表示式）.

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Logic Gate Network

= +

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Boolean Expression for Logic Gate Network（邏輯電路的布林表示法）• Similar to finding the expression for a

single gate.• Inputs may be compound expressions

that represent outputs from previous gates（指輸入可能是前一個網路的輸出，因此可能是許多布林變數的組合）.

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Boolean Expression for Logic Gate Network

= +

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Bubble-to-Bubble Convention

• Choose gate symbols so that outputs with bubbles connect to inputs with bubbles, and vice versa.

• Results in a cleaner notation and a clearer idea of the circuit function.

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Bubble-to-Bubble Convention

+

= + +AB

/CD

DC

AB

U1A

14011

1

23

U2A

14071

1

23

U3A

14081

1

23

Y=AB+/CD

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Order of Precedence（運算先後順序）

• Unless otherwise specified, in Boolean expressions AND functions are performed first, followed by ORs.

• To change the order of precedence, use parentheses（括弧）.

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Order of Precedence+

+ + ++

+ +

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Simplification by Double Inversion

• When two bubbles touch, they cancel out.

• In Boolean expressions, bars of the same length cancel.

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Logic Diagrams from Boolean Expressions

• Use order of precedence.• A bar over a group of variables is the

same as having those variables in parentheses.

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Logic Diagrams from Boolean Expressions

= + +

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Truth Tables from Logic Diagrams or Boolean Expressions

• Two methods:– Combine individual truth tables from each

gate into a final output truth table, i.e, progressively（漸進式）.

– Develop a Boolean expression and use it to fill in the truth table.

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Truth Tables from Logic Diagrams or Boolean Expressions

+

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Truth Tables from Logic Diagrams or Boolean Expressions

, i.e., previous page

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Circuit Description Using Boolean Expressions

• Product term (minterm-No input variable is absent):– Part of a Boolean expression where one or

more true or complement variables are ANDed, e.g., .

• Sum term (Maxterm-No input variable is absent):– Part of a Boolean expression where one or

more true or complement variables are ORed, e.g., .

DCBA

)( DCBA +++

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Circuit Description Using Boolean Expressions

• Sum-of-products (SOP):– A Boolean expression where several

product terms are summed (ORed) together.

• Product-of-sum (POS):– A Boolean expression where several sum

terms are multiplied (ANDed) together.

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Examples of SOP and POS Expressions

)()()( :POS :SOP

CACBBAY

DACBABY

+•+•+=

++=

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SOP and POS Utility

• SOP and POS formats are used to present a summary of the circuit operation.

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Bus Form

• A schematic convention in which each variable is available, in true or complement form, at any point along a conductor.

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Bus Form

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Deriving a SOP Expression from a Truth Table

• SOP: Sum Of Product terms• Each line of the truth table with a 1 (HIGH)

output represents a product term.• Each product term is summed (ORed).• A product term with all the n input

variables, where n is number of inputs, is also called a minterm.

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Deriving a POS Expression from a Truth Table

• Each line of the truth table with a 0 (LOW) output represents a sum term.

• The sum terms are multiplied (ANDed).• A sum term with all the n input variables,

where n is number of inputs, is also called a Maxterm.

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Deriving a POS Expression from a Truth Table

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Theorems of Boolean Algebra

• Used to minimize a Boolean expression to reduce the number of logic gates in a network.

• 24 theorems.

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Commutative Property（交換律）

• The operation, i.e., AND, OR operator, can be applied in any order with no effect on the result.– Theorem 1: xy = yx– Theorem 2: x + y = y + x

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Associative Property（結合律）

• The operands（運算元） can be grouped in any order with no effect on the result.– Theorem 3: (xy)z = x(yz) = (xz)y– Theorem 4: (x + y) + z = x + (y + z) = (x + z) + y

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Distributive Property（分配律）

• Allows distribution (multiplying through) of AND across several OR functions.

• Theorem 5: x(y + z) = xy + xz• Theorem 6: (x + y)(w + z)

= (x + y)w + (x + y)z= xw + yw + xz +yz= xw + xz + yw + yz

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Distributive Property

Both in the form of SOP.

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Operations with Logic 0

• Theorem 7: x • 0 = 0• Theorem 8: x + 0 = x• Theorem 9: x ⊗ 0 = x, ⊗ means Exclusive

OR operation

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Operations with Logic 1

• Theorem 10: x • 1 = x• Theorem 11: x + 1 = 1 • xx 1 :12Theorem =⊗

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Operations with Logic 1

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Operations with the Same Variable

• Theorem 13: x • x = x• Theorem 14: x + x = x• Theorem 15: x ⊗ x = 0

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Operations with the Complement of a Variable

••• 1 :18 Theorem

1 :17 Theorem0 :16 Theorem

=⊗=+=•

xxxxxx

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Operations with the Complement of a Variable

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Double Inversion

• xx :19 Theorem =

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DeMorgan’s Theorem

•• yxyx

yxyx

:21 Theorem

: 20 Theorem

•=+

+=•

口訣：長線變短線加號變乘號反之亦然

Slogan：Replace a long line by a short lineReplace a plus by a dotAnd vice versa.

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Multivariable Theorems• Theorem 22: x + xy = x• Theorem 23: (x + y)(x + z) = x + yz

= xx + xz + xy + yz= xx + xy + xz + yz= ( x + xy ) + xz + yz= ( x + xz ) + yz= x + yz

• yxyxx :24 Theorem +=+ 定理證明在次頁；原講義錯誤！

Based on Theorem 22

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Multivariable Theorems

Based on Theorem 23x + x’y = ( x + x’ )( x + y) = 1( x + y ) = x +y

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Simplifying SOP and POS Expressions

• A Boolean expression can be simplified by:– Applying the Boolean Theorems to the

expression（直接由布林方程式畫簡之）– Application of graphical tool called a

Karnaugh map (K-map) to the expression

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Simplifying an Expression

BAYxx

BAYx

CBAYBA

CBABAY

) 1 ( :10 theorem applying

1 1) (1 :11 theorem applying

) (1 term common the out factoring

=

=••=

=++=

+=

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Simplifying an Expression

BAYBAY

xBCAY

AACBAY

ACBAY

ACBAY

(1)

1 1 11:theoremapplying 1) (1

outfactoring

20theoremsDeMorgan'applying ) (

20theoremsDeMorgan'applying ) (

+=

+=

=++•+=

•++=

++=

+•=

注意：原講義錯誤！

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Simplification By Karnaugh Mapping

• A Karnaugh map, called a K-map, is a graphical tool used for simplifying Boolean expressions.

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Construction of a Karnaugh Map• Square or rectangle divided into cells.• Each cell represents a line in the truth

table.（每一格都是真值表的一列）• Cell contents are the value of the output

variable on that line of the truth table.

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Construction of a Karnaugh Map

採用Gray code編碼順序

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Construction of a Karnaugh Map

採用Gray code編碼順序

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Construction of a Karnaugh Map

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K-map Cell Coordinates

• Adjacent cells differ by only one variable.• Grouping adjacent cells allows

canceling variables in their true and complement forms.

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Grouping Cells

• Cells can be grouped as pairs, quads, and octets.（兩個一組、四個一組或八個一組）

• A pair cancels one variable.（21=2）• A quad cancels two variables. （22=4）• An octet cancels three variables. （23=8）• See next page for examples.

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Grouping Cells

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Grouping Cells

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Grouping Cells

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Grouping Cells along the Outside Edge

• The cells along an outside edge are adjacent to cells along the opposite edge.（天涯若比鄰）

• In a four-variable map, the four corner cells are adjacent.（四個角落亦屬相鄰）

‧See next page for examples.

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Grouping Cells along the Outside Edge

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Loading a K-Map from a Truth Table

• Each cell of the K-map represents one line/row from the truth table.

• The K-map is not laid out in the same order as the truth table.（指K map使用Gray code，和一般真值表的二進位表示法順序不同）

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Loading a K-Map from a Truth Table

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Loading a K-Map from a Truth Table

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Multiple Groups

• Each group is a term in the maximum SOP expression.

• A cell may be grouped more than once as long as every group has at least one cell that does not belong to any other group. Otherwise, redundant terms will result.（畫簡時，每一儲存格可以被重複利用）

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Multiple Groups

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Maximum Simplification

• Achieved if the circled group of cells on the K-map are as large as possible.

• There are as few groups as possible.

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Maximum Simplification

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Using K-Maps for Partially Simplified Circuits

• Fill in the K-map from the existing product terms.（將既有的Product term填入Cell中）

• Each product term that is not a minterm will represent more than one cell.（每一個Cell都是一個minterm）

• Once completed, regroup the K-map for maximum simplification.

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Using K-Maps for Partially Simplified Circuits

See next page for K-Map

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Using K-Maps for Partially Simplified Circuits

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Don’t Care States

• The output state of a circuit for a combination of inputs that will never occur.

• Shown in a K-map as an “x”.

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Value of Don’t Care States

• In a K-map, set “x” to a 0 or a 1, depending on which case will yield the maximum simplification.

• Once determined, the value of the cell for the don’t care can not be altered.

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Value of Don’t Care States

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POS Simplification Using Karnaugh Mapping

• Group those cells with values of 0.（SOP是將1的Cell圈起來；而POS是將0的Cell圈起來）

• Use the complements of the cell coordinates as the sum term.（圈起群組後，仍是相同者留下，但是此時記得取留下變數之反相，並寫成Sum term形式）

• See next page for example.

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POS Simplification Using Karnaugh Mapping

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Bubble-to-Bubble Convention – Step 1

• Start at the output and work towards the input.

• Select the OR gate as the last gate for an SOP solution.

• Select the AND gate as the last gate for an POS solution.

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Bubble-to-Bubble Convention – Step 2

• Choose the active level of the output if necessary.（Use NOR instead of OR, and use NAND instead of AND if active low is required）

• Go back to the circuits inputs to the next level of gating.

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Bubble-to-Bubble Convention – Step 3

• Match the output of these gates to the input of the final gate. This may require converting the gate to its DeMorgan’s equivalent.（亦即依據下一級之輸入是否有Bubble來決定此一級輸出是否需以Demorgan’sTheorem進行轉換）

• Repeat Step 2 until you reach the circuits.

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Bubble-to-Bubble Convention – Step 3

CBACAB •

注意：原講義錯誤！

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Bubble-to-Bubble Convention – Step 3

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Universality of NAND/NOR Gates

• Any logic gate can be implemented using only NAND or only NOR gates.

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NOT from NAND

• An inverter can be constructed from a single NAND gate by connecting both inputs together.

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NOT from NAND

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AND from NAND

• The AND gate is created by inverting the output of the NAND gate.

BABAY •=•=

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AND from NAND

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OR and NOR from NAND

YXYX

YXYX

NOR

OR

+=•=

+=•=

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OR and NOR from NAND

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OR and NOR from NAND

Conform the bubble to bubble convention!

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NOT from NOR

• An inverter can be constructed from a single NOR gate by connecting both inputs together.

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NOT from NOR

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OR from NOR

• The OR gate is created by inverting the output of the NOR gate.

BABAY +=+=

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OR from NOR

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AND and NAND from NOR

YXYX

YXYX

NAND

AND

•=+=

•=+=

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AND and NAND from NOR

Conform the bubble to bubble convention!

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AND and NAND from NOR

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Practical Circuit Implementation in SSI

• Not all gates are available in TTL.• TTL components are becoming more

difficult to find.• In a circuit design, it may be necessary

to replace gates with other types of gates in order to achieve the final design.

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Pulsed Operation• The enabling and inhibiting properties of

the basic gates are used to pass or block pulsed digital signals.

• The pulsed signal is applied to one input.• One input is used to control

(enable/inhibit) the pulsed digital signal.

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Pulsed Operation

A

B

C

A+BY

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Pulsed Operation

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General Approach to Logic Circuit Design – 1

• Have an accurate description of the problem.

• Understand the effects of all inputs on all outputs.（you may need a Truth table for assistance）

• Make sure all combinations have been accounted for.

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General Approach to Logic Circuit Design – 2

• Active levels as well as the constraints on all inputs and outputs should be specified.

• Each output of the circuit should be described either verbally, i.e., in Boolean expression, or with a truth table.

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General Approach to Logic Circuit Design – 3

• Look for keywords AND, OR, NOT that can be translated into a Boolean expression if a verbal description is used.

• Use Boolean algebra or K-maps to simplify expressions or truth tables.

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