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Assembly Language for Intel-Based
Computers, 5th Edition
Chapter 2: IA-32 Processor
Architecture
(c) Pearson Education, 2006-2007. All rights reserved. You may modify and copy this slide show for your personal use,
or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.
Slides prepared by the author
Revision date: June 4, 2006
Kip Irvine
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 2
Chapter 2 Outline
• 2.1 General Concepts
• 2.2 IA-32 Processor Architecture
• 2.3 IA-32 Memory Management
• 2.4 Components of an IA-32 Microcomputer
• 2.5 Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 3
2.1 General Concepts
• 2.1.1 Basic microcomputer design
• 2.2.2 Instruction execution cycle
• 2.2.3 Reading from memory
• 2.2.4 How programs run
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 4
2.1.1 Basic Microcomputer Design
• The central processor unit (CPU): where all the calculations and logic
operations take place
• Clock: synchronizes internal CPU operations with other
components
• Control unit (CU): coordinates sequence of execution steps
• Arithmetic logic Unit (ALU): performs arithmetic and bitwise
processing
Central Processor Unit
(CPU)
Memory Storage
Unit
registers
ALU clock
I/O
Device
#1
I/O
Device
#2
data bus
control bus
address bus
CU
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 5
Basic Microcomputer Design (Cont.)
• The memory storage unit: where instructions anddata are held while a computer program is running.
• A bus: a group of parallel wires that transfer data
from one part of the computer to another.
• Data bus• Transfer instruction and data
• Address bus
• Hold the address of instruction and data
• Control bus
• Synchronize the actions of all devices
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 6
Clock
• Clock: repeatedly pulses at a constant time
• Synchronizes all CPU and BUS operations
• Machine cycle (clock cycle time): the most basic unit of time for machine instruction
• A machine instruction requires at least one clock cycleto execute.
• A few instructions (e.g., the multiply instruction) require inexcess of 50 clocks
one cycle
1
0
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 7
Clock (Cont.)
• The duration of a clock cycle is the reciprocal of theclock’s speed
• 1 GHz ( 1 billion oscillations per second)
=> clock cycle time = 1 ns (nanosecond)
• Synchronous operation: need a clock• Clock is used to trigger events
• Asynchronous operation: does not require a system
clock
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 8
2.1.2 Instruction Execution Cycle
• The execution of a single machine instruction can be
divided into a sequence of individual operations.
• Three primary operations: fe tc h , d e c o d e and e x ec u te .
• Two more steps are required when the instruction uses amemory operand: f e tc h o p e r a n d and s t o r e o u t p u t
o p e r a n d
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 9
2.1.2 Instruction Execution Cycle (cont.)
• Fetch
• Decode
• Fetch operands
• Execute
• Store output
I-1 I-2 I-3 I-4
PC program
I-1instruction
register
op1op2
memory fetch
ALU
registers
w r i t e
d e c o d e
execute
read
w r i t e
(output)
registers
flags
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 10
Instruction Execution Cycle (Cont.)
• Fetch
• Fetch the instruction indexed by PC (program counter)• Copy it from memory into the CPU
• Increment the PC
• Decode
• The control unit (CU) determine the type of instruction andtell the ALU
• Fetch operand
• If a memory operand is needed, the CPU retrieve theoperand from memory
• Execute
• Store output operand
• If the output operand is in memory, write it back
• p.s.
• Each step takes at least one clock cycle
• Each processor has its own steps, e.g, IA-32 has six stages
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 11
Multi-Stage Pipeline
• Pipelining makes it possible for processor to execute instructions in
parallel• Instruction execution divided into discrete stages
S1 S2 S3 S4 S5
1
C y c l e s
Stages
S6
2
3
45
6
7
8
9
10
11
12
I-1
I-2
I-1
I-2
I-1
I-2
I-1
I-2
I-1
I-2
I-1
I-2
Example of a non-
pipelined processor.
Many wasted cycles.
For k states and n instructions, the number of required cycles is:
n * k
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 12
Pipelined Execution
• More efficient use of cycles, greater throughput of instructions:
S 1 S 2 S 3 S 4 S 5
1
C y c l e s
S t a g e s
S 6
23
4
5
6
7
I - 1
I - 2 I - 1I - 2 I - 1
I - 2 I - 1
I - 2 I - 1
I - 2 I - 1
I - 2
For k states and n instructions, the number of required cycles is:
k + (n – 1)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 14
Superscalar
A superscalar processor has multiple execution pipelines. In the
following, note that Stage S4 has left and right pipelines (u and v).
S 1 S 2 S 3 u S 5
1
C y c l e s
S t a g e s
S 6
2
34
5
6
7
I - 1
I - 2
I - 3I - 4
I - 1
I - 2I - 3
I - 4
I - 1I - 2
I - 3
I - 4
I - 1
I - 3 I - 1
I - 2 I - 1
v
I - 2
I - 4
S 4
8
9
I - 3
I - 4
I - 2
I - 3
1 0 I - 4
I - 2
I - 4
I - 1
I - 3
For k states and n instructions, the number of required cycles is: k + n
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 15
2.1.3 Reading from Memory
• Memory access is a bottleneck and multiple machine cycles are
required when reading from memory• It responds much more slowly than the CPU.
• The steps are:• Address placed on address bus
• Read Line (RD) set low to notify memory that a value is to be read
• CPU waits one cycle for memory to respond
• Read Line (RD) goes to 1, indicating that the data is on the data
busCycle 1 Cycle 2 Cycle 3 Cycle 4
Data
Address
CLK
ADDR
RD
DATA
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 16
Cache Memory
• High-speed expensive s t at i c R A M both inside and
outside the CPU.
• Level-1 cache: inside the CPU
• Level-2 cache: outside the CPU
• Cache hit: when data to be read is already in cachememory
• Cache miss: when data to be read is not in cache
memory.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 18
How a Program Runs (Cont.)
• The user issues a command to run a certain program.
• The OS searches for the program’s filename (in thec u r r e n t directory or predetermined list of directories)
• If found, the OS retrieves basic information, like filesize, physical location, about the program’s file fromthe disk directory.
• The OS loads the program file into memory.
• The CPU begins to execute the program (process) by jumping to the first instruction of the program
• Now, the program is called a process
• The process runs by itself
• When the process ends, OS removes its handle andmemory
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 19
Multitasking
• OS can run multiple programs at the same time.
• A process may optionally contains multiple threads of execution.
• Scheduler assigns a given amount of CPU time toeach running program.
• Rapid switching of tasks
• Gives illusion that all programs are running at once
• The processor must support task switching.
• The processor saves the state (e.g., registers, variables,program counter) of each task before switching to a newone
• OS can assign varying priorities to tasks
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 20
Chapter 2: What's Next
• 2.1 General Concepts
• 2.2 IA-32 Processor Architecture
• 2.3 IA-32 Memory Management
• 2.4 Components of an IA-32 Microcomputer
• 2.5 Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 21
2.2 IA-32 Processor Architecture
• 2.2.1 Modes of operation
• 2.2.2 Basic execution environment
• 2.2.3 Floating-point unit
• 2.2.4 Intel Microprocessor history
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 22
2.2.1 Modes of Operation
• P r o t ec t e d m o d e
• The native mode of the processor and all instructions andfeatures are available
• Used by Windows and Linux
• Programs are given separate memory areas (called
segments) with proper protection
• R e al -a d d re ss m o d e
• Native MS-DOS
• Implements the programming environment of the Intel 8086
processor
• All Intel processors boot in Real-address mode
• Then the OS may switch to another mode
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 23
Modes of Operation (cont.)
• S y s t em m a n a g em en t m o d e
• Provides an operating system with a mechanism for
implementing
• power management, system security, diagnostics
• Implemented by computer manufactures
• Virtual-8086 mode
• While in Protected mode, the processor can directly execute
Real-address mode program in a safe multitasking environment.
• Each program has its own 8086 computer
• A special case of Protected Mode, so it is called Virtual
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 24
2.2.2 Basic Execution Environment
• Addressable memory
• General-purpose registers
• Index and base registers
• Specialized register uses
• Status flags
• Floating-point, MMX, XMM registers
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 25
Addressable Memory
• Protected mode• 4 GB
• 32-bit address
• Real-address and Virtual-8086 modes
• 1 MB space
• 20-bit address
• Protected mode while running program in Virtual-
8086 mode
• Each program can access its own separate 1MB
memory
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 26
Registers• Registers are high-speed storage locations directly inside the CPU
• Intel registers
• 8 general-purpose registers
• 6 segment registers
• EFLAGS: processor status flag
• EIP: instruction pointer
CS
SS
DS
ES
EIP
EFLAGS
16-bit Segment Registers
EA X
EB X
EC X
ED X
32-bit General-Purpose Registers
FS
GS
EB P
ES P
ES I
ED I
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 27
General-Purpose Registers
• Used for arithmetic and data movement
• EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
AH AL
16 bits
8
AX
EAX
8
32 bits
8 bits + 8 bits
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 28
Accessing Parts of Registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
AH AL
16 bits
8
AX
EAX
8
32 bits
8 bits + 8 bits
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 29
Index and Base Registers
• Some registers have only a 16-bit name for their lower half:
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 30
Some Specialized Register Uses (1 of 3)
• EAX
– extended accumulator register
• Used by multiplication and division instructions)
• ECX – loop counter
• ESP – stack pointer, extended stack pointer
register
• ESI, EDI – index registers• Extended source/destination index registers
• EBP – extended frame pointer (stack)
• Used by high-level languages to reference function
parameters and local variables
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 31
Some Specialized Register Uses (2 of 3)
• Segment register: as base locations for pre-assigned memory areas
• CS – code segment
• Hold instruction
• DS – data segment
• Hold variables
• SS – stack segment
• Hold local variables and function parameters
• ES, FS, GS - additional segments
• EIP – instruction pointer
• Containing the address of the next instruction to be executed
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 32
Some Specialized Register Uses (3 of 3)
• EFLAGS
• Status and control flags
• Each flag is a single binary bit
• Co n t ro l Fl ag
• Control the operation of the CPU
• Example, IF Flag (interrupt flag)
• Status Flag
• Reflect the outcome of some CPU operations
• Example
– Carry Flag (CF)
– Overflow Flag (OF)
– Sign Flag
– Zero Flag
– Auxiliary Carry Flag
– Parity Flag
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 33
Flags
• C o n t r o l Fl ag s
• Direction
• Interrupt
• S t at u s Fla g s
• Carry
• unsigned arithmetic out of range
• Overflow
• signed arithmetic out of range
• Sign
• result is negative
• Zero
• result is zero
• Auxiliary Carry
• carry from bit 3 to bit 4
• Parity
• sum of 1 bits is an even number
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 34
System Registers
• System registers
• Only permit access by programs running at the highest
privilege level (level 0), e.g., the Window XP
• IDTR (Interrupt Descriptor Table Register)
• GDTR (Global Descriptor Table Register)
• LDTR (Local Descriptor Table Register)
• Task Registers
• Control Registers: CR0, CR2, CR3, CR4
• Model-Specific Registers
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 35
2.2.3 Floating-Point, MMX, XMM Registers
• Floating-point unit: eight 80-bit floating-
point data registers
• ST(0), ST(1), . . . , ST(7)
• arranged in a stack
• used for all floating-point arithmetic
• Registers for multimedia programming• Eight 64-bit MMX registers
• Eight 128-bit XMM registers for single-
instruction multiple-data (SIMD) operations
ST(0)
ST(1)
ST(2)
ST(3)
ST(4)
ST(5)
ST(6)
ST(7)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 37
Early Intel Microprocessors
• Intel 8080
• 64K addressable RAM• 8-bit registers
• CP/M operating system
• S-100 BUS architecture
• 8-inch floppy disks!
• Intel 8086/8088
• Mark the beginning of the modern Intel Architecturefamily
• IBM-PC Used 8088
• 1 MB addressable RAM
• 16-bit registers
• 16-bit data bus (8-bit for 8088)
• separate floating-point unit (8087)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 39
Intel IA-32 Family
• Intel386• 4 GB addressable RAM, 32-bit registers,
paging (virtual memory)
• Intel486
• instruction pipelining
• Pentium
• superscalar, 32-bit address bus, 64-bit
internal data path
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 41
CISC and RISC
• CISC – c o m p l e x i n s t r u c t i o n s e t
• large instruction set
• high-level operations
• High-level language compilers would have less work
• requires microcode interpreter
• Complex instructions require a long time for theprocessor to decode and execute
• examples: Intel 80x86 family• RISC – r ed u c e d i n s t r u c t i o n s e t
• simple, atomic instructions
• small instruction set
• directly executed by hardware
• examples:
• ARM (Advanced RISC Machines)
• DEC Alpha (now Compaq)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 42
Chapter 2 Outline: What's Next
• 2.1 General Concepts
• 2.2 IA-32 Processor Architecture
• 2.3 IA-32 Memory Management
• 2.4 Components of an IA-32 Microcomputer
• 2.5 Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 43
2.3 IA-32 Memory Management
• 2.3.1 Real-address mode
• 2.3.2 Calculating linear addresses
• 2.3.3 Protected mode
• 2.3.4 Multi-segment model
• 2.3.5 Paging
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 44
IA-32 Memory Management
• Real-address mode
• Processor can run only one program at a time• Each program can address up to 1MB
• 1 MB RAM maximum addressable• (00000~FFFFFh)
• Application programs can access any area of memory
• Single tasking
• Supported by MS-DOS operating system
• Protected mode• Processor can run multiple program at the same time with
each process a total of 4GB memory
• MS-Windows and Linux
• Virtual-8086 mode
• Simulate an 80x86 running in real-address mode while inprotected mode
• Command windows in MS-Windows
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 45
Real-Address Mode
Real-address mode can address up to 1MB memory
(20-bit address) However, the original 8086 processor had only 16-bit
registers, which can not directly represent a 20-bit address
Solution: s eg m en t ed m e m o r y a d d r es s i n g
Memory is divided into 64KB (16-bit address) units calledsegment
Segment-offset address: use two 16-bit numbers to calculate
20-bit address
A 16-bit segment value stored in segment register
A 16-bit offset value
Thus, absolute (linear) address is a combination of a 16-bitsegment value added to a 16-bit offset
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 46
Segmented Memory Map, Real-address Mode
00000
10000
20000
30000
40000
50000
60000
70000
80000
90000
A0000
B0000
C0000
D0000
E0000
F0000
8000:0000
8000:FFFF
seg ofs
8000:0250
0250
l i n e a r a d d r e s
s e s
one segment
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 47
Calculating Linear Addresses
• Given a segment address, multiply it by 16 (add a
hexadecimal zero), and add it to the offset
• Example: convert 08F1:0100 to a linear address
Adjusted Segment value: 0 8 F 1 0
Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 48
Your turn . . .
What linear address corresponds to the segment/offsetaddress 028F:0030?
028F0 + 0030 = 02920
Always use hexadecimal notation for addresses.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 49
Your turn . . .
What segment addresses correspond to the linear address28F30h?
Many different segment-offset addresses can produce the
linear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 50
Protected Mode (1 of 2)
• 4 GB addressable RAM• (00000000 to FFFFFFFFh)
• Each program assigned a memory partition which
is protected from other programs
• Described by s eg m e n t d e s c r i p t o r t a b l es
• Designed for multitasking
• Supported by Linux & MS-Windows
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 51
Protected Mode (2 of 2)
• Program structure
• code, data, and stack areas
• CS, DS, SS segment descriptors
• global descriptor table (GDT)
• Has two memory model
• Flat segmentation model
• Multi-segment model
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 52
Flat Segmentation Model
• All segments are mapped to the entire 32-bit physical
address space of the computer.• At least two segments: one for program code and one
for data
• Each segment is defined by a s e g m e n t d es c r i p t o r ,a 64-bit value stored in a table known as the g l o b a l d e sc ri p t o r t a b l e (G D T)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 53
Multi-Segment Model
• Each program has a local descriptor table (LDT)
• Holds descriptor for each segment used by the program
3 0 0 0
R A M
0 0 0 0 3 0 0 0
L o c a l D e s c r ip t o r T a b l e
0 0 0 2
0 0 0 0 8 0 0 0 0 0 0 A
0 0 0 2 6 0 0 0 0 0 1 0
b a s e lim it a c c e s s
8 0 0 0
2 6 0 0 0
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 54
Paging
• Supported directly by the CPU
• A segment is further divided into 4096-byte (4KB)blocks of memory called pages
• Allow the memory used by programs can be larger than the computer ’s actual memory
• Virtual memory v.s. physical memory
• Part of running program is in memory, part is on disk• Virtual memory manager (VMM) – OS utility that
manages the loading and unloading of pages
• Page fault – issued by CPU when a page must beloaded from disk
• Page in: bring a requested page into memory• Page out: evict an unused page to the disk
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 55
Chapter 2 Outline: What's Next
• 2.1 General Concepts
• 2.2 IA-32 Processor Architecture
• 2.3 IA-32 Memory Management
• 2.4 Components of an IA-32 Microcomputer
• 2.5 Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 56
2.4 Components of an IA-32 Microcomputer
• 2.4.1 Motherboard• 2.4.2 Video output
• 2.4.3 Memory
• 2.4.4 Input-output ports
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 57
2.4.1 Motherboard
• CPU socket
• External cache memory slots
• Main memory slots
• BIOS chips
• Sound synthesizer chip (optional)
• Video controller chip (optional)• IDE, parallel, serial, USB, video, keyboard, joystick,
network, and mouse connectors
• PCI bus connectors (expansion cards)
I t l D850MD M th b d
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Intel D850MD Motherboard
dynamic RAM
Pentium 4 socket
Speaker
IDE drive connectors
mouse, keyboard,
parallel, serial, and USB
connectors
AGP slot
Battery
Video
Power connector
memory controller hub
Diskette connector
PCI slots
I/O Controller
Firmware hub
Audio chip
Source: Intel® Desktop Board D850MD/D850MV Technical Product
Specification
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2.4.2 Video Output
• Video controller • on motherboard, or on expansion card
• AGP (accelerated graphics port technology)*
• Video memory (VRAM)
• Video CRT Display
• uses raster scanning
• horizontal retrace
• vertical retrace
• Direct digital LCD monitors
• no raster scanning required
* This link may change over time.
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Sample Video Controller (ATI Corp.)
• 128-bit 3D graphics
performance powered byRAGE™ 128 PRO
• 3D graphics performance
• Intelligent TV-Tuner withDigital VCR
• TV-ON-DEMAND™
• Interactive Program Guide
• Still image and MPEG-2 motionvideo capture
• Video editing
• Hardware DVD video playback
• Video output to TV or VCR
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2.4.3 Memory
• ROM
• read-only memory
• EPROM
• erasable programmable read-only memory
• Dynamic RAM (DRAM)
• inexpensive; must be refreshed constantly
• Static RAM (SRAM)
• expensive; used for cache memory; no refresh required
• Video RAM (VRAM)
• dual ported; optimized for constant video refresh
• CMOS RAM
• complimentary metal-oxide semiconductor
• system setup information
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2.4.4 Input-Output Ports and Device Interfaces(cont)
• Serial
• RS-232 serial port
• one bit at a time
• uses long cables and modems
• 16550 UART (universal asynchronous receiver
transmitter)• programmable in assembly language
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Chapter 2 Outline: What's Next
• 2.1 General Concepts
• 2.2 IA-32 Processor Architecture
• 2.3 IA-32 Memory Management
• 2.4 Components of an IA-32 Microcomputer
• 2.5 Input-Output System
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2.5.1 Levels of Input-Output
• Level 3: Call a library function (C++, Java)
• easy to do; abstracted from hardware; details hidden
• slowest performance
• Level 2: Call an operating system function
• specific to one OS; device-independent
• E.g., writing entire strings to files, reading string from the
keyboard, allocating blocks of memory for application programs• medium performance
• Level 1: Call a BIOS (basic input-output system) function
• may produce different results on different systems
• knowledge of hardware required
• usually good performance
• Level 0: Communicate directly with the hardware
• May not be allowed by some operating systems
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Displaying a String of Characters
• When a HLL program displays a string of
characters, the following steps take place:1. Application program writes the string to
standard output.
2. The library function calls OS, passing a
string pointer.
3. OS passes the ASCII code and color of
each character to BIOS. OS also calls
BIOS function to control the cursor.
4. BIOS maps each character to a particular
system font and sends it to a hardware
port attached to the video controller card.
5. The video controller card generateshardware signals to the video display.
Application Program
OS Function
BIOS Function
Hardware Level 0
Level 1
Level 2
Level 3
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ASM Programming levels
ASM Program
OS Function
BIOS Function
Hardware Level 0
Level 1
Level 2
ASM programs can perform input-output ateach of the following levels:
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Playing a WAV File
• At the OS level, you do not have to know what type of
device was installed and the card’s features
• At the BIOS level, you would query the sound card and
find out whether it belongs to a certain class of sound
cards
• At the hardware level, you would fine-tune the program
for certain brands of audio cards, to take advantage of
each card’s special features
• Not all operating system permit user programs to directly
access system hardware
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Tradeoff
• Tradeoff
• Control (efficiency) v.s. portability
• However, some OSs, like Windows and Linux, do not
permit user programs to directly access system
hardware
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Summary
• Central Processing Unit (CPU)
• Arithmetic Logic Unit (ALU)
• Instruction execution cycle
• Multitasking
• Floating Point Unit (FPU)
• Complex Instruction Set• Real mode and Protected mode
• Motherboard components
• Memory types
• Input/Output and access levels