Institut fur Integrierte Systeme

Integrated Systems Laboratory

Analog Integrated CircuitsExercise 2: Introduction to Cadence

Philipp Schonle J64.2, Luca Bettini J93, Rene Blattmann J93

Hand out: 18.10.2013Hand in: 01.11.2013

The exercise takes place in room ETZ D96. The exercise startsat 13:15 and ends at 15:00.

1 Introduction

Analog integrated circuit design is usually done by ”paper and pencil” with very simple models in afirst stage. In a second stage, the behavior of the circuit is verified by a simulation software tool withmore precise models and the circuit is then modified based on these results. However, the results fromthe simulation software should more or less agree with the considerations made in the first stage, whenall components have been dimensioned. Currently, the most sophisticated and wide-spread softwarepackage for the analysis and synthesis of analog and digitalintegrated circuits is theDesign FrameworkII (DFII) of Cadence Inc., which is referred to asCadencein the following. The purpose of this exerciseis to become familiar with the schematic entry and simulation environment of Cadence. You are goingto perform the most important analyses on the basis of simpleanalog integrated circuits. Note that thematerial conveyed in this exercise forms the basis for all subsequent labs and is a prerequisite for theirsuccessful completion. We therefore suggest that you keep this exercise within reach in the future labs.

2 Getting Started

Open a terminal session and enter the following commands:

cd ˜mkdir uebung2cd uebung2icdesign ams-hk4.10 &

The last command starts — after approving the creation of a new cockpit structure — the DZ-cockpit1

(Fig. 1) for different processes of the Austrian chip foundry AMS (Austria Micro Systems2). We will1DZ stands for Mikroelektronik Designzentrum:www.dz.ee.ethz.ch2seehttp://www.ams.co.at

use theC35B4M30.35 µm 2P3M CMOS process throughout the AIC labs. The nominal supply voltagefor this process is 3.3 V. The process specific parameters forCadence are provided by the chip foundryas design kits. However, AMS calls its design kitAMS Hit Kit.Click onDesign Framework IIto start Cadence DFII.

Figure 1: DZ cockpit window.

When starting Cadence, multiple windows appear on the screen. Ignore and close theWhat’s New?windows. Fig. 2 shows theCommand Interpreter Window (CIW)of Cadence. In this window, toolsand functions may be invoked either through the menu or by typing aSKILLcommand in the commandline. SKILL is a Cadence proprietary dialect of the programming languageLISP. Note that the toolsdisplay important messages in the area above the command line! Therefore it is a good idea to enlargethis window a litte bit.

Figure 2: Command Interpreter Window (CIW).

The window of Fig. 3 entitledLibrary Manager is Cadence’s ”file manager” that manages librariesand cells. The Library Manager may be invoked from the Command Interpreter Window by clickingTools.Library Manager 3.

3Command1.Command2means you should clickCommand2in the menuCommand1.

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Figure 3: Library Manager.

3 The Library and Cell Hierarchy

Have a look at Fig. 3: the column to the far right shows the differentviewsof the transistornmos4.At the moment only theschematic view, needed to draw a circuit representation, and maybe thelayoutviewwith the physical layout of the transistor are relevant to us.

Generally, circuits may become large and complex. Therefore, it makes sense to sum up self-containedparts of a circuit as blocks - especially if these blocks are to be used more than once in the overall circuit.A hierarchy level above, only a graphical representation ofthe block is necessary, which is called thesymbol view. This concept allows to structure circuits in a hierarchical way.

Different cells may be arranged in categories for the sake ofmore clarity. The cells that have not beenassigned to a certain category appear in the categoryUncategorized. The category display may beenabled and disabled with the tick boxShow Categoriesin the upper left corner of the Library Manager.Note that a cell may belong to more than one category. Therefore, the category doesnot constitute ahierarchical structure.

Cells and categories are assigned to a library. At the moment, the librariesanalogLibandPRIMLIBare relevant to us. PRIMLIB is an AMS library and contains thecomponents (MOSFETs, resistors,capacitors, etc.) of the selected technology.

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Generate your own library for this exercise by clickingFile.New.Library in the Library Manager.EnterMyLibrary for Nameand clickOK. A technology file has to be assigned to your library. Ac-cept the defaultAttach to an existing technology library and selectTECHC35B4asTechnology Library in the subsequent dialog box. The generated library MyLibrary shouldnow appear in the Library Manager.

Now generate a cell callednmosdc and its schematic view. To do this, first selectMyLibrary inthe Library Manager. Then clickFile.New.Cell View and choosenmos dc for Cell Name,schematic for both, View Name and Type, andSchematics XL for Application. After clickingOKthe schematic entry window pops up and we are ready to assemble our circuit.

4 Schematic Entry in Virtuoso Composer

The composer serves as graphical schematic entry tool. Thissection introduces the most relevant com-mands by means of a simple example.

Figure 4: Composer Window.

If you followed the tutorial correctly so far, then you should have the window displayed in Fig. 4 on yourscreen now. Buttons for frequently used commands can be found in the toolbars. Moving the mousecursor over a button allows you to get a short help text such asCheck and Savefor the third button fromthe left.

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Further help for the active command is provided in the statusline of the composer window, where atthe momentHIT-Kit: ams˙4.10is displayed. By pressingESCyou can terminate the active commandbefore completion4.

Figure 5: Schematic for the NMOS DC characteristics.

The schematic of your first circuit is depicted in Fig. 5. At first, place the transistor by clickingCreateInstance i 5. In the dialog box, you can specify the wanted component either by filling in the fieldsLibrary, Cell, andViewby hand, or by using the browser. Now pressBrowse and look fornmos4 inthe libraryPRIMLIB and select thesymbol view.

Move the mouse cursor over the composer window. The mouse cursor now shows the symbol of theNMOS transistor. Before you place the transistor, enter0.7u for Width and0.35u for Length inthe Add Instance window. Use the same value forWidthStripe as forWidth . Note that nospace is allowed between the value and the factoru! Before you place the component it may be rotatedin 90◦ steps by pressingr . You may now finally place the transistor with the left mouse button.

In order to edit the parameters select the component with theleft mouse button. Then either click on theProperty q button in the toolbar or chooseEdit.Properties.Objects from the menu. As analternative theProperty Editor(usually on the left) can be used. For working efficiently with Cadenceit pays to memorize the shortcuts of the most often used commands. The shortcuts are shown in thepertaining menu entries, e.g. [Objects... q ]. Have a look at the menusEdit andCreate toget an overview of the most important commands for drawing a circuit!

From the analogLib, place the ground connectiongnd and a voltage sourcevdc for both the gate anddrain voltage according to Fig. 5. Use thesymbol view here as well. For both voltage sources enter 3V for the DC voltage .

Note: the gnd connection is absolutely needed by the simulator in order todefine a referencepotential and therefore has to be included in each circuit!!!

The ports of the components may be connected with the commandCreate.Wire (narrow) w .If this command is active, the composer suggests a connection with the symbol⋄ near the mouse cursor.Pressings (for snap) accepts the proposal and allows to connect the various components in a convenient

4Since uncompleted commands are ”stacked” astack overflowmay occur. PressESCa couple of times in such situations -possibly in different windows - in order to clear the stack.Nest Limitand the number ofUndosmay be set in the CommandInterpreter Window inOptions.User Preferences .

5Shortcut Keys are given in frames. An uppercase letterX denoteshift+X

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manner.

Usually a net is assigned a name automatically, e.g.net2. With the buttonCreate Wire Name lyou may assign names explicitly, e.g.vds andvgs as in Fig. 5. Enter the desired label in theNamesfield of the corresponding dialog box and position the label on the wire you would like to name.

Like wires, components are designated automatically as well, e.g. V0 in case of a voltage source. Tochange the name select the corresponding component and press q . You may now change the fieldInstance Nameaccordingly.

Now change all the net and instance names in your circuit according to Fig. 5 and save your design withFile.Check and Save X .

5 Simulation with Analog Design Environment

The circuit may now be simulated directly from the Composer Window. There are different kinds ofsimulations. One of them is theDC analysis. The DC analysis returns the DC operating points of thecircuit components. Additionally, a parameter such as the voltage of a voltage source or the temperaturemay be varied to determine the DC operating points for each condition.

The transient analysisdetermines the behavior of the circuit in the time domain, e.g. the step responsefor a low pass filter.

The AC analysislinearizes the circuit around the specified operating pointand then determines thebehavior of the circuit in the frequency domain in steady state for a sinusoidal source. It can e.g. returnthe amplitude and phase response of an amplifier. The AC analysis is a small signal analysis whichmeans that the nonlinear components are linearized in theirbias points first. Only then is the actualfrequency analysis performed by the simulator.

Besides the mentioned analyses there are many others. However, these are not in our interest at themoment.

Now start the simulation tool Analog Design Environment (ADE) from the Composer with the commandLaunch.ADE L . If dialogs appear asking for permission to check for a(G)XL licence, clickO.K.. Thewindow depicted in Fig. 6 will appear on your screen.

The menu entrySetup.Simulator/Directory/Host allows you to select the simulator (we aregoing to usespectre ) and to specify the directory inProject Directory where the simulationdata should be written to. Accept the defaults here.

The file path to the simulation models may be specified withSetup.Model Libraries . Again,accept the defaults.

5.1 The DC Analysis

SelectAnalyses.Choose in the Analog Environment and click ondc in the following dialog box.Make sure to tickSave DC Operation Point and clickOK. Now run the simulation by click-ing Simulation.Netlist and Run . First, the netlist is generated which is then passed to the

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Figure 6: Analog Design Environment.

simulator along with the model parameters and simulation settings. Finally, the simulator is invoked.

After the simulation has completed you can have the DC bias values printed by first clickingResults.Print.DC Operating Points and then selecting the NMOS transistor symbol.

5.1.1 The DC Sweep

Now we want to simulate the steady state behavior of the NMOS transistor when the drain sourcevoltage is rising from 0 to 3.6 V. SelectAnalyses.Choose → dc → Component Parameter→ Select Component and select the voltage source V1 in the composer (see Fig. 7).A dialog boxwith a selection of parameters pops up. ChooseDC voltage and clickOK. For theSweep Rangeuse 0-3.6 and proceed withOK. With these settings, a DC analysis is performed for each relevant valueof VDS within the given range. Before you start the simulation, youhave to define which voltagesand currents should be saved. ChooseOutputs.Save All in the Analog Design Environment andmake sure thatallpub is ticked for Select signals to output (save) and thatall isticked for Select device currents (currents) . Set thesubcircuit probe levelto 1. Proceed withOKand start the simulation.

After the simulation has completed, open the window shown inFig. 8 with Tools.Calculator .Have a look at the second toolbar from the top (vt , vf , . . . ). The first letter stands for voltage and thesecond one denotes the type of analysis:t for transient analysis,f for frequency analysis,s for DCsweep, anddc for DC analysis. The second row of the toolbar contains the same analyses pertaining tocurrents.In order to plot the drain currentIDS as a function of the drain source voltageVDS, click is in thecalculator and then on the drain port (marked by a red square)of the transistor in the Composer Window.Now the display line of the calculator readsIS("/M1/D") . If so, use theTools.Plot function toget the characteristic shown on the left of Fig. 9.

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Figure 7: DC Sweep.

Instead of using the calculator you may plot the simulation results directly from the Analog Environmentwith help of the commandResults.Direct Plot.DC and by selecting the port or net of interestwith the mouse in the schematic. PressESCto terminate the selection and to plot the curve.

A third possibility is to use the results browser (Fig. 9) which you start from the ADE withTools.ResultsBrowswer . It gives direct access to all saved signals, operating points et.c. Click on thedc folder toshow the saved results of the DC (sweep) analysis. A double-click on a signal directly plots it in thewindow on the right. More options can be accessed with the right mouse button, such as using theselected signal in the calculator or exporting the simulation results as a .csv file.

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Figure 8: Calculator.

Figure 9: Results Browser and output characteristic of the NMOS transistor.

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5.1.2 The Parametric Analysis

The parametric analysis allows you to simulate theIDS(VDS) characteristic for variousVGS in a singlepass. For this, replace the DC voltage value of the source V0 with the variablevgs and save the changeswith File.Check and Save . Now click Variables.Copy from Cellview in the ADE inorder to import your variable. The commandTools.Parametric Analysis brings the windowdepicted in Fig. 10 to your screen.

Figure 10: Input window for the parametric analysis.

Type or selectvgs for Variable , set theRange Type to From/To and choose a range of 1 to3.5. SetStep Mode to Linear Steps and enter 0.5 forStep Size . Make sure thatSweep? ischecked. Now start the simulation withAnalysis.Start Selected .

The plot may be produced the same ways as for the DC sweep analysis, e.g. chooseis in the calculator,click on the drain port, and hitTools.Plot afterwards. This should result in theIDS(VDS, VGS)characteristic of Fig. 11. However, if you have kept the plotwindow from the DC sweep open, the newgraphs will be added without removing the old one. You can hide a graph with the ’eye’ button or deleteit by first selecting and then pressingDel .

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Figure 11:IDS(VDS, VGS) characteristic.

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Problems:

DC Analysis of a MOSFET

1. (a) The range where the output characteristic is almost flat may be interpreted as a finite output-resistance source controlled by itsVGS voltage. What kind of source is this?

(b) What is the value of this resistance(

dVDS

dIDS

)

atVGS = 3V andVDS = 3V?

Use the following two procedures to determine the resistance:

i. Determine the operating points of the transistor. Use thecommandResults.Print.DCOperating Points and click on the transistor in the composer. Determine thewanted resistance with the help of the parametergds .

ii. Calculate the resistance from the slope of the corresponding characteristic. SelectSpecial Functions in theFunction Panel and click onderiv (for deriva-tion). The display line of the calculator now readsderiv(IS("/M1/D")) . PressingTools.Plot (without deleting the former plot) results in the the wantedset of curvesthat are shown together with theIDS(VDS, VGS) characteristics in the same plot. Youcan rearange the curves by drag & drop to separate plots. A newset of axis can be cre-ated with the commandsFile.New Window andFile.New Subwindow . Zoomin on the area aroundVDS = 3V:Zoom In: Draw a rectangle with the right mouse button pressedX-Axis Zoom: Shift + mouse wheel

Y-Axis Zoom: Ctrl + mouse wheel

Fit: fSet a marker to read out the slope at a certain point. Use the dialogMarker.CreateMarker or:Horizontal Marker: hVertical Marker: vPoint Marker: m

A marker can be deleted by selecting it and then pressDel .

2. In the following three problems you are going to simulate the output characteristic of varioustransistor channel lengths and widths. We are going to use variables for these parameters so wedo not have to adjust the quantities in the composer each time.

First close the Plot Window and the parametric analysis window. Select the transistor in the com-poser and open theEdit Object Property window by pressingq. If you get the ”wrong”window here, pressESCand try again. Now enter the variablewfor Width andWidth Stripeand use the variablel for Length . Make sure that the factoru does not stay there undeliberately.Click OKandFile.Check and Save X .

Remember that you have to copy the new variables from the composer withVariables.CopyFrom Cellview into the ADE. The variables may now be edited with. Choosevgs=3 ,w=0.7u , l=0.35u and start the simulation withSimulation.Netlist and Run . PlottheIDS(VDS) characteristic. Now double the channel width W and simulateagain!

(a) How did the currentIDS change in response to the new channel width W?

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3. Now also double the channel length L! Compare the output characteristic forW = 0.7µm,L = 0.35µm to the characteristic forW = 1.4µm, L = 0.7µm!

(a) How did the controlled source change?

(b) How did its resistance change?

4. SetW = 50µm, L = 2µm and repeat the parametric analysis from the beginning of this section.Choose a range of 0.8-1.8 V for the variablevgs and set theStep Control to Linear . Enter11 for Total Steps and start the simulation withAnalysis.Start Selected .

After you have plotted the characteristics, print the curves to a file and send it through the VPPhomepage to the prefered printer.

Close the Analog Environment withSession.Quit . A dialog box will ask you whether youwant to save the current state. AnswerYes. Next, options on what to save are presented. Ac-cept the default by pressingOK. You could also save the current state without quitting AnalogEnvironment withSession.Save State . At a later point in time, you may load the simula-tion settings again withSession.Load State . Now close all windows except the CommandInterpreter Window and the Library Manager.

Simple Amplifier Circuit

A simple single-stage amplifier is to be built with a n-channel MOSFET as shown in Fig. 12.VDD is 3.3V and the n-channel MOSFET has the following dimensions:W = 50µm, L = 2µm. The MOSFETshould operate at a gate source bias ofVGS = 1.4V and a drain source bias ofVDS = 2.3V.

R

VOUT

VDD

VIN

Figure 12: Simple NMOS amplifier.

1. Mark the operating point on your characteristics sheet obtained before!

2. Draw the load line! How large is the load resistance?

3. Create a new cellamplifier in your library MyLibrary . Open the schematic view for thiscell and draw the amplifier circuit of Fig. 12 in the same manner as in section 4. Use the cellresof analogLib to model the resistor R.

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Simulate the output voltageVOUT as a function ofVIN with the help of the DC sweep analysis.Choose the range 0-3.3 V forVIN. After the simulation, click onvs in the calculator window andthen on the net representingVOUT in the composer.

(a) Based upon yourVOUT = f(VIN) plot, specify the range ofVIN in which the circuit worksas an amplifier!

(b) Is this range also visible on your sheet with the load line? Mark the range on this sheet!

(c) Determine the gaindVOUT

dVINin a couple of operating points with help ofVOUT = f(VIN) plot!

4. As you may see, the gain is fairly small.

(a) How must the load resistance or the load line be changed inorder to achieve a higher gain?

(b) Is it reasonable to replace the load R with an ideal current source? Draw the load line of anideal current source in a qualitative manner!

Now quit the Analog Environment withSession.Quit and close all windows except the CommandInterpreter Window and the Library Manager.

5.2 The AC Analysis

In this section, you are going to simulate the amplitude and phase response of a RLC network.

Create a new schematic cell view namedRLC net in your library MyLibrary and draw the circuitshown in Fig. 13 using the componentsvdc , ind , cap , res andgnd of theanalogLib library.

Figure 13: RLC network.

Select the voltage source and pressq (or use the Property Editor subwindow). SetAC Magnitude to1 V. Save the design and start the Analog Environment. ClickAnalyses.Choose and selectac . ForSweep Range choose1K for the start frequency and1G for the stop frequency. PickLogarithmicas Sweep Type and set the number of points per decade to 100. Proceed withOK and start thesimulation.

In order to plot the amplitude response of the circuit, pressthevf button in the calculator and select theVOUT net in the composer. Now click ontodB20 (is found in theModifier functions set) and thenTools.Plot . Repeat the procedure for the phase response but usephase instead ofdb20 this time.

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5.3 The Transient Analysis

Now we would like to simulate the step response for the RLC network. Replace the voltage sourceV0with the cellvpulse from the libraryanalogLib and set the following values:

Voltage1 :=0VVoltage2 :=5VDelay time :=500nsRise time :=20nsFall time :=20nsPulse Width :=5usPeriod :=10us

Save the design and clickAnalyses.Choose in the Analog Environment. Now pick thetrananalysis and enter9u for Stop Time . Make sure thatEnabled in the lower left corner of the windowis ticked and proceed withOK. Delete the contents of the Waveform Window and start the simulation.Now plot the input voltage by pressingvt in the calculator and clicking on the netV IN in the composer.PressTools.Plot afterwards. Use the same procedure to plot the output voltage V OUT. Measurethe peak of over- and undershoot with help of point markersm .

Now conduct the same analysis with the initial conditionsVC(t=0) = −5V andIL(t=0) = 400mA. Forthis, select the capacitor and pressq (or use the Property Editor subwindow). You may now specifythe initial voltage in the fieldInitial condition . The same procedure applies to the inductor.Save the design and start the simulation. Use the commandFile.Reload.Current SubwindowCtrl + r of the Waveform Window to refresh the input and output voltage plots. Again, measure the

peak of over- and undershoot.

This completes the introduction to Cadence. You may now close the Analog Environment and quitCadence with the commandFile.Exit of the Command Interpreter Window.

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