Cadence Tutorial

Cadence is an Electronic Design Automation (EDA) environment that supports all the stages of IC design and verification from a single environment. These tools are completely general, supporting different fabrication technologies.

This tutorial covers the following topics:

I. Setting up the Cadence Environment………………………………2

II. Running Cadence Tools…………………………………………….4

III. Drawing the Schematic of an Inverter…………………………….6

IV. Creating a symbol for the inverter………………………………..11

V. Testing the designed inverter………………………………………14

VI. Simulation of the Inverter Schematic……………………………..15

VII. Drawing the layout of an Inverter……………………………...17

VIII. Simulation of the Inverter layout……………………………….28

IX. Extracting……………………………………………………………31

X. Layout Simulation……………………………………………………32

XI. Generating GDS File…………………………………………………36

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I. Setting up the Cadence environment

Start the below mentioned programs to run the cadence tutorial.

1. Exceed: It allows the PC to access other machines running X clients and X11 connections.Go to StartAll ProgramsApplicationsHumming bird connectivity V7.1 Exceed Exceed

2. SSH secure client program: It is typically used to log into a remote machine and execute commands, but it also supports tunneling. (It provides a secure path through an untrusted network).Go to StartAll ProgramsApplicationsSSH Secure ShellSSH secure client

On the SSH Secure Client:

Click on Profiles Add Profile (name the profile as cadence).The following window will pop up. Enter the below mentioned details in the window:

Host name: rx1.sce.umkc.eduUser name: Your Umkc user idPort number: 22

Click on connect and enter your Umkc password.

*Go to profiles again and click on Edit profiles cadence profile tunneling tab check the tunnel X11 connections box.

On the SSH Secure Client type:

mkdir cadence [Enter] cd cadence [Enter] cp /usr/cadence/ncsu-cdk-1-5-0/cdssetup/cdsinit ./.cdsinit [Enter] cp /usr/cadence/ncsu-cdk-1-5-0/cdssetup/cds.lib ./cds.lib [Enter]

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You will do this only once – the first time you use Cadence tools. The next time you login, simply change to the cadence directory and run the icfb tool by typing:

cd cadence [Enter] icfb & [Enter]

3. X-window Initialization Failure:

If the following warning “*WARNING* X Window Display Initialization failure” pops up after entering the icfb command, follow the procedure below.

Go to StartRun and type cmd. The cmd window will appear after this.Enter the ipconfig command at the prompt. This will give you the system’s IP address.

Type export DISPLAY=134.193.126.133:0 [Enter]icfb & [Enter]

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II. Running Cadence Tools

The command icfb & starts Cadence in the background and, after a couple of "update" messages that you can ignore for now (just click Continue) you should get a window with the icfb as below:

In the icfb window go to FileNewLibrary. Enter ECE5635 as the Library Name and Attach to an existing techfile under the Technology File and click OK. The window would look like this:

The following window will pop up after you click Ok.

Select the NCSU_TechLib_ami06 in the Technology Library and then click OK.

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In the icfb window, go to File New Cell view. In the window that appears enter inverter as the Cell Name, schematic as the View and Composer-Schematic as the tool. The window would look like this:

Then click OK. You should get the Composer schematic capture window. Spend some time analyzing the window. On the left side you have various shortcuts to common used commands such as: placing component instances, drawing wires, placing ports, stretching, copying, zooming in and out, saving, etc.

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III. Drawing Schematic of an Inverter

1. Circuit diagram of an Inverter

2. Adding components to the virtuoso schematic window:

Follow the below steps: Go to menu and select Add instance (or press i) In component browser window

Select NCSU_Analog_Parts under LibrarySelect N_TransistorsSelect nmos transistor

The Add instance window, that appears will allow you to change the length, width, diffusion lengths etc;

When you move mouse into schematic window, nfet symbol will follow your pointer.

Type "Esc" to exit adding component action. Repeat the same procedure to add pmos transistor under P-Transistors in

component browser window. Change the width of the pmos transistor to 3.0u M. The properties of the added components can also be changed after placing them on the schematic editor window. This can be done by selecting the component and pressing “Q” or by selecting the component and clicking on the properties symbol, on the left side of the window.

- Properties symbol

The component browser and add instance window would look like below.The add instance window a pmos transistor of width 3uM is also shown.

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Now let us add vdd and gnd.7

Vdd: Add instanceSupply_NetsVdd. Gnd: Add instanceSupply_NetsGnd.

The schematic window should look like this:

Connect each component using wires. Wire: Add Wire (narrow) or press “w”. Place mouse pointer on one of the node you want to connect. Click "mouse Left button", drag to other node to connect and click "mouse

Left button" to finish.

The window should like this after wiring all the components:

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Now let us add input and output pins. Input pin: Add pin or press “P”. Pin name: In, Direction: Input. The

window should look like shown below. Click on hide and you can see that the Input symbol follows the mouse.

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Output pin: Add pin or press “P”. Pin name: Out, Direction: Output. The window should look like shown below. Click on hide and you can see that the Output symbol follows the mouse.

The Inverter schematic should look like this after placing the input and output pins. Go to Designcheck and save. The icfb window should show 0 errors.

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IV. Creating a symbol for the Inverter

Design Create cell view From cell view

Make sure the view name is symbol and cell name is inverter. The cell view from cell view window should look like this:

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The following window will pop up:

Select the red box (selection box) and press “delete” key. Select the green box (symbol shape) and press “delete” key. Now let us draw a symbol for inverter. Select “Line” from the tool bar on the left and the window looks like this: Then draw the shape of a buffer.

Select “Line” from the tool bar on the left and select the shape “circle” Then draw a bubble to place in front of the buffer we just drew.

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After drawing the inverter symbol, Select Add Selection box Automatic. A red box appears around the

drawn inverter symbol. Select Designcheck and save. The icfb window should show no errors. The

inverter symbol and the icfb window should look like this:

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V. Testing the designed inverter

In the icfb window go to File Newcell view. Give the cell name as inverter_test, view name as schematic and Tool as Composer_Schematic. Then Click OK. A new virtuoso schematic window will appear.

Go to Add instance or press “i”. Now change the library to “ECE5635”. You can see the inverter in your library. Click on the inverter symbol and move the mouse on to the schematic window. The symbol you have just created for the inverter will appear on the window.

Now let us add Vdc and Vpulse to test the inverter designed Vdc: Add instanceVoltage_SourcesVdc (Enter 5v in the DC voltage

column) Vpulse: Add instance Voltage_SourcesVpulse (Enter 0v for voltage 1,

5v for voltage 2, delay time as 20n, rise and fall times as 100p) Create an output pin “O1”.

Now label the input and output wires. Select the wire you want to name and click on the “wire name” at the left side of the window. Click on Hide and then double click on the wire you want to name.Check and save the schematic, icfb window should show 0 errors.

The window would look like this for naming the wires:

The Inverter_test schematic window should look like this:

VI. Simulation of the Inverter Schematic 14

Click on the menu ToolsAnalog Environment in the Virtuoso Schematic window.The following window will appear:

This is the Analog Design Environment window. Click on SetupSimulator/directory/hostSpectreS (as simulator)OK

Click on AnalysisChooseTran under analysis 200n in the stop time moderate under Accuracy DefaultsOK. The window should look like this:

Make sure moderate and enabled are selected.

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Click on Simulation Run. Wait until you get a successful message in your icfb window.

Click on ResultsDirect PlotTransient Signal.

The Virtuoso Schematic window will prompt you to select the node voltages you want to plot. Click on the wires with the labels in and out and hit ESC in your keyboard.A window with the plots like this will appear.

VII. Drawing Layout of an Inverter 16

Now let us go through the steps to practice layout of a CMOS inverter.

1. Create Layout Cell view From the icfb window, choose File New Cell view A dialog box will appear prompting you for the design library, cell name and cell

view. Make sure that the library name corresponds to your design library (ECE5635),

choose a name for your cell (inverter) and choose Virtuoso as the design tool, then click OK. The cellview will be selected as layout.

The window would look like this:

The LSW (Layer Selection Window) and an empty Virtuoso windows will pop-up after you have entered the design name.

The LSW contains all the layers and their color formats that will be used to layout the circuitry.

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We can either draw the PMOS and NMOS transistors or can directly use the pCells available in Cadence. We shall use the pcells to draw the layout of individual transistors.

A pCell is a predefined object whose layout is generated automatically but can be user defined.

2. Drawing NMOS transistor:

Go to Create Instance [Enter]

This is called the Create Instance window. Click on the button Browse. The Library Browser window will appear. Under the Library section select NCSU_TechLib_ami06. Under the Cell section select nmos and under the View section select layout. At this point you will notice that the mouse cursor changes to a yellow box every time you move it above the Layout Editor window.

Don’t place the transistor yet.

Go back to the Create Instance window, scroll down and take a look at the different parameters. You can change the Width (W) and the Length (L) of the transistor. For now, we will keep the default values, i.e. W=1.5u, L=0.6u.

Go to the Layout Editor window and click somewhere in the lower half of the window to place the NMOS transistor. If you see a red box with the text nmos, press shift + F to view all the layers. By pressing Ctrl + F you can go back to the box view.

3. Drawing PMOS transistor:

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Go to CreateInstance[enter]. Follow the same procedure as for NMOS but select pmos under the cell selection.

Don’t place the transistor yet.

Go back to the Create Instance window and change the Width to 3.0u. Click somewhere on the upper half of the Layout Editor to place the PMOS.

Make sure the components are placed symmetrically about the X and Y axis for look and feel. Placing them anywhere else, will not give any errors.

Your Layout Editor window should look like this:

The green area around the PMOS is the nwell layer. The NMOS transistor does not have a pwell because it has a p substrate.

4. Drawing the metal and poly connections:

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To draw the metal wire that connects the drain of the NMOS with the drain of the PMOS you will have to draw a metal1 rectangle. Press “R” on the key board. The following window will appear:

Click on Hide and select the metal1 layer (in blue) from the LSW window.

Click once at the starting point (drain of the PMOS transistor) and move the cursor to the finish point (drain of the NMOS transistor).The layout editor would look like this:

In the LSW select the layer poly(in red).

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You are going to draw a poly rectangle connecting the two gates as shown in the next figure:

To delete any wrongly placed rectangles, select the component and press “Delete” key or you can try to use the tools available on the left.

5. Power Rails and Ground Rails:

We will add Power and Ground rails. Usually a layout consists of a large number of cells, and all of which need power or ground connections. Therefore, it is common to design cells such that they all share a pair of continuous and wide power rail and ground rail with various cells placed side by side. Metal-1 is suggested or the horizontal power and ground lines.

Draw the Power Rail in metal1(VDD) above the PMOS by hitting “R”.Draw the Ground Rail in metal(GND) below the NMOS by hitting “R”.

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Draw the following metal1 rectangles as shown in the next figure (you might need to zoom out. To zoom out hit Shift + Z. To zoom in hit Ctrl + Z. Hitting f centers the layout on the screen i.e it fits the layout to the window.

Don’t forget to save your layout as you progress. You can save your layout by clicking the DesignSave

6. Adding contacts between different layers:

1. poly and metal1:

CreateInstance. Click the Browse button. In the Library Browser window that will appear select NCSU_TechLib_ami06 under Library, m1_poly under Cell and layout under View. Place the poly-metal1 contact as shown in the figure below.

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Add a metal1 and a poly rectangle to connect the gate to the m1_poly.Make sure the sources of the PMOS and NMOS are connected to power rail and ground rail respectively. Zoom the window and cover the m1_poly contact well. The layout editor window would appear as shown below:

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Try to zoom the window while making any connections to avoid errors.

2. N-well to metal1:

Create Instance and choose Library NCSU_TechLib_ami06, choose Cell m1_n and View layout. The mouse cursor will change to a square. Place the contact on top of the metal that will be the connecting VDD.

3. p-well to metal1:

CreateInstance and choose Library NCSU_TechLib_ami06, choose Cell m1_p and View layout. Place the contact on the metal connecting GND.

4. N-well:

The n-well of the PMOS transistor has to be extended to cover the n-well/metal1 contact we have just added. Select the layer nwell in the LSW and draw a rectangle around the m1_n contact, touching the n-well. The layout window would look like this:

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5. Adding Labels:

CreateLabel. On the window that appears type in the Labels box: VDD! GND! IN and OUT. The pop up window would look like this:

Click on the VDD metal, on the GND metal, on the input metal and finally on the output metal. It is important that you follow the same order in which you typed the labels in. The window should look like this:

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6. Checking for DRC (Design Rules Check):

To check for design rules violations (i.e. errors in your layout), click on the menu VerifyDRC. Make sure the Rules File text box reads divaDRC.rul and that the Rules Library text box reads U_TechLib_ami06. The window should look like as shown below.

A check of your layout for design rules violations will start. If no errors are present you will read a no error message on the icfb window. If there are errors, they will be highlighted on the Layout Editor window in white color and a list of the errors will appear on your icfb.

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7. Example of a DRC error:

Notice the white trapezoid highlighting the error. To view a description of a particular error click on EditProperties and then click on the trapezoid highlighting your error. A description will appear in the icfb window. Correct the error and run DRC again.

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VIII. Simulation of the Inverter Layout

Now, let us draw a poly1-poly2 capacitor and connect it to the output of Inverter.

The Layout Editor provides a rule tool to measure distances. To enable the rule tool, hit k on your keyboard. Click once on the starting point and move the mouse to the end position. Click again. You will see a ruler being drawn as you move the mouse.

To delete all rules, hit Shift + k on your keyboard.

First, we will draw the bottom plate which is made up of poly1 layer. The area of the bottom plate will be slightly larger than the calculated area because we want space to add a contact to the bottom plate.

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Draw a rectangle using the layer poly from the LSW window. The poly square would look like this in the virtuoso layout editor:

Draw the top plate using the layer elec from LSW window. This is the layer designation for poly2. T

The distance between poly1 and poly2 should be 1.5um. If not the design would show DRC errors when you verify the design.

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The layout window with the capacitor would look like as shown below:

Now, we are going to connect the bottom plate to GND and the top plate to the output of the inverter. For the bottom plate, go to create instance, NCSU_TechLib_ami06 library, choose Cell m1_poly and View layout. For the top plate, go to create instance, NCSU_TechLib_ami06 library, choose Cell m1_elec and View layout.

Save your layout and run DRC. Fix any errors that you might find.

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IX. Extracting

Now, we are going to extract the electrical connectivity from the layout.

Click on the menu Verify –> Extract. On the window that will appear next, click on the button Set Switches. In the next window, click on Extract_parasitic_caps then click OK. Click OK once more in the next window.

You will see a message on the icfb window indicating that the extraction operation was successful. The icfb window would show the following message:

You can take a look at the extracted circuit by opening the extracted View of your Cell inverter from the icfb window. The extracted view of the inverter would look like this:

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X. Layout Simulation

Open the schematic of the test circuit by clicking on FileOpen on the icfb window. Select the library ECE5635, the Cell inverter_test and the View schematic. Click OK.

Click on ToolsAnalog Environment.

Select hspiceS as the simulator and a transient analysis from 0 to 600n by 50n increments.

On the Analog Environment window, click on SetupEnvironment. The following window will appear:

On the Switch View List textbox add the word extracted to the list. It should look something like this:

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Click OK.

Run the simulation. The icfb window should show “successful” message.

Got to ResultsDirect Plot Transient Signal in the simulation window and select the in and out wires you want to plot on the inverter_test schematic.

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When you plot the results, you should get similar waveforms than when you ran the pre-layout simulation. If there is a substantial difference, then there is an error in your layout. Go back and check. The plot should look like this:

A good way to debug your layout is with the help of the extracted netlist. To see the extracted netlist, on the Analog Environment window click on Simulation – Netlist – Create Final. A window with the netlist will pop up as shown below.

Most netlists either contain or refer to descriptions of the parts or devices used. Each time a part is used in a netlist, this is called an "instance." Thus, each instance has a "master", or "definition". These definitions will usually list the connections that can be made to that kind of device, and some basic properties of that device. These connection points are called "ports" or "pins", among several other names.

An "instance" could be anything from a MOSFET transistor or a bipolar transistor, to a resistor, capacitor, or integrated circuit chip.

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Nets are the "wires" that connect things together in the circuit. Net-based netlists usually describe all the instances and their attributes, then describe each net, and say which port they are connected on each instance. This allows for attributes to be associated with nets.

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XI. Generating GDS File

GDS II stream format, common acronym GDSII, is a database file format which is an industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photo masks.These files are needed when we submit our designs to MOSIS for fabrication.

On the icfb window, click on FileExportStream. Click on the Library Browser button.In the Library Browser window that appears next, select your Library ECE5635, Cell inverter and View layout. In the Output File textbox write inverter.gds. The window, would look like this:

Click OK.

Wait until you get a message saying that the operation was successful.Verify the file inverter.gds has been created in your work directory.

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To verify the file, go to SSH secure file window, click on the new file transfer window icon. Open the file with your library name and you can view the gds file created.

The SSH window would with the gds file for the inverter would look like this:

For your final project you will submit your GDS file along with your report.

Your entire project can be opened using this gds file from the icfb window.

Congratulations. Now you are ready to start your project!!!

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