Standard Verification Rule ManualCalibre LVS Option
2007/01
By :python
OPTION LVS CHECK PORT NAMES {YES | NO} LVS RECOGNIZE GATE {ALL |
SIMPLE | NONE} LVS REDUCE SPLIT GATES {YES/NO} LVS ABORT ON SUPPLY
ERROR {YES | NO} LVS ALL CAPACITOR PINS SWAPPABLE {NO | YES} LVS
CHECK PORT NAMES {NO | YES} VIRTUAL CONNECT COLON {NO|YES} LVS BOX
LVS COMPARE CASE {NO / YES} LAYOUT DEPTH { ALL | PRIMARY} PORT
DEPTH {ALL | PRIMARY |number} TEXT DEPTH {ALL | PRIMARY |number }
LVS ABORT ON SOFTCHK {NO |YES} LVS REPORT OPTION V S A AV B C D F G
P R RA
LVS SOFT SUBSTRATE PINS {NO | YES} LVS Filter Unused Option { B
D E O } LVS Filter Unused Option {AB RC RE RG} LVS Filter Unused
Bipolar { YES | NO } LVS Globals Are Ports {NO | YES} TEXT PRINT
MAXIMUM {ALL | NUMBER} LVS Property Resolution Maximum {number |
All}
LVS Softchk Pwell_all contact Trace Property C1 C2 C3
trace_val
OPTION {}
precision 1000 //()1000 resolution 10 // layout grid size
0.01um(10/1000) database unit LAYOUT PATH "***" // layout database
LAYOUT PRIMARY "PA6368A1" // layout database top cell SOURCE
PRIMARY "PA6368_TOP" // netlist SOURCE PATH "**" //layout database
top cellnetlist top cell UNIT LENGTH u // , u=1e-6 m u (umil
mmcminchm) UNIT CAPACITANCE fF // f=1e-15F=(aF
fFpFnFuFmFFkFmegFgFtF) UNIT RESISTANCE OHM //ohm=1 (ohmaohm
fohmpohmnohmuohmmohmkohmmegohmgohmtohm) layout system gdsii //
layout database source system spice // netlsit erc results database
erc.db ascii //ascii LVS REPORT lvs.rep //lvs report
OPTION {}
MASK SVDB DIRECTORY svdb QUERY XRC // lvs report RVElvs report
XRC for rc extraction LVS POWER NAME "VGH" "VCC" "VDDD" "VDDA"
//layout power name LVS GROUND NAME "VGL" "VSSD" "VSS" "VSSA"
//layout ground name LVS SPICE PREFER PINS NO //subcircuitpin name
global LVS REDUCE PARALLEL BIPOLAR YES //bipolar LVS REPORT MAXIMUM
ALL // showlvs error report
XRC
for rc extraction
OPTION {}LVS REDUCE PARALLEL MOS YES //mos LVS REDUCE PARALLEL
DIODES YES //diodes LVS REDUCE PARALLEL CAPACITORS YES // LVS
REDUCE PARALLEL RESISTORS YES // LVS REDUCE SERIES RESISTORS YES //
LVS REDUCE SERIES CAPACITORS YES // LVS SIGNATURE MAXIMUM ALL //
layout,net , , source
OPTION {}
LVS CHECK PORT NAMES YES // LVS port name LVS CHECK PORT NAMES
YES // LVS port name LVS IGNORE PORTS NO //LVS,layout source pin
name
LVS RECOGNIZE GATELVS RECOGNIZE GATE
ALL Specifies that all gates are recognized. SIMPLE Specifies
that simple gates are recognized. NONE Specifies that no gates are
recognized. () LVS REDUCE SPLIT GATES YES LVS to reduce split
gates. gate NO LVS not to reduce split gates. gate
LVS ABORT ON SUPPLY ERROR {YES | NO} NO
Define No lvs short ,
YES lvsshort report short(lvs.report.short)
LVS ALL CAPACITOR PINS SWAPPABLE {NO | YES} YES NO pin pin
LVS CHECK PORT NAMES {NO | YES} NO NOnetlistlayoutlvs
YES
lvsLayout netlistport name lvs.rep
VIRTUAL CONNECTVIRTUAL CONNECT COLON {NO|YES}Correct X V V X V
Pin_NAME1 Pin_NAME2 Pin_NAME3 Note VDDA VCI: VDDA: VCI: VCI: VDDA:
VCI: VDDA:EFG VCI VCI VDDA:ABC VCI:ABC VCI:ABCVDDA VDDA
VCI VDDAVCI:VCI:ABCVCI VCInet If pin_name3&pin_name2
netVCI
VIRTUAL CONNECT NAME PIN_NAME Incorrect Correct PIN_NAME
LVS BOXLVS BOX LAYOUT CELL_NAME LVS BOX SOURCE CELL_NAME TOP
CELLMAPPING CELLcommand file CELLOK CELL
LVS COMPARE CASE NO / YES LVS COMPARE CASE: YES SOURCE CASE
& LAYOUT CASE SOURCE CASE NO / YES :source netlist (device
& pin name) LAYOUT CASE NO / YES :layout netlist (device &
pin name)
LAYOUT CASE
YES
Layout device type lvs command filedevicelayer lvs correct
LAYOUT DEPTH ALL | PRIMARY.when option set , shapes are read
from the top-level cell to the bottom of the hierarchy. .when
option set only.top
ALL
PRIMARY, shapes are read from the top-level cell
LAYOUT DEPTH PRIMARY
Lvs.rep Nothing in layoutNOT COMPARED
PORT DEPTH ALL | PRIMARY |numberUsed only in Calibre LVS/LVS-H
option set PRIMARY, the tool to use freestanding port objects from
only the top-level cell. topcellports) . when option set ALL, the
tool to use free-standing port objects from throughout the
hierarchy. cellports) when option set number, from number levels
below the top-level cell. Specifying zero is equivalent to PRIMARY.
topports, number0top.when
PORT DEPTH ALL,lvsMissing port
Lvs. rep
TEXT DEPTH ALL | PRIMARY |number.when
option set PRIMARY, only text objects from the top-level cell
are selected. topcelltexts) option set ALL, text objects from
throughout the hierarchy are used as top-level text. cell
texts)
.when
option set number, text objects from number levels below the
top-level cell. Specifying zero is equivalent to PRIMARY. top
texts,number0top.when
TEXT DEPTH ALL ,lvs Correct
Naming or swapoverride errors
Lvs.rep:Lvs. rep
LVS ABORT ON SOFTCHK NO |YES.when option set
NO, tool not to abort processing when a violation is detected.
tool
.when option set
YES, tool to abort processing when a violation is detected.
toolLVS SOFTCHK & SCONNECT)
SCONNECT
LVS REPORT OPTION V. Virtual Connect Colon YES & Virtual
Connect Name ?Virtual connections are reported as notes in the
Extraction report and Warnings section of the LVS report.
LAYOUT port VDDA ,but MT
LVS REPORT OPTION S.that enables the detailed reporting of
Sconnect conflicts in thetranscript and the LVS Report.SCONNECT
short)
S
A
A:MT2 B B:MT2
VIA1
MT1 MT1
DC
OD OD
p+
HVPW HVPW
VIA1
DC
P+
LVS REPORT OPTION (A AV)A DETAIL INSTANCE CONNECTION REPORT
CONECTIONSHORT OPEN, Incorrect Devices On This Net correct Devices
On This Net AV AREPORT POWER GNDcorrect Devices On This Net
AAAV
LVS REPORT OPTION (B C D)B DETAIL INSTANCE CONNECTION
REPORTSHORT OPEN
Missing Net NOT Similar Net Missing Instance Missing Gate REPORT
detailed instance connections B C D RULE FILE
C D
LVS REPORT OPTION ( B C D) REPORT REPORT
Net 8(800,500) ---------------- ---------------** unmatched
connection * 53(530,500):D *
DOG * X1/M5:D * unmatched connection
LVS REPORT OPTIONF unbalanced smashed MOSFET summary warning ,(
W=10,M=1lay W=5 ,M=2); respective warnings Information and Warnings
section ,F
(F)
LVS REPORT OPTION ( G )G detailed instance connections in
Property Error discrepancies.
LVS REPORT OPTION ( P )P An optional argument that disables
thereporting of Direct connections between different ports warnings
in the connectivity extractor. REPORTWARNING
Direct connections between different ports PORT
LVS REPORT OPTION ( P )LAYOUT
LVS REPORT OPTION ( R RA )RAn optional argument that disables
reporting of ambiguity resolution points in LVS when the overall
comparison result is CORRECT. This option controls reporting of
ambiguity resolution points in the Information and Warnings section
of the LVS report as well as reporting of ambiguity resolution
status messages in the Overall Comparison Results and Cell
Comparison Results sections of the LVS report. When the overall
comparison result is other than CORRECT, ambiguity resolution
points are reported as usual, regardless of this option.
overall comparison result is CORRECT ambiguity resolution
pointsINCORRECT OPTION ambiguity resolution points INFORMATION AND
WARNINGS
LVS SOFT SUBSTRATE PINS {NO | YES}LVS SOFT SUBSTRATE PINS {NO |
YES} YES indicates that substrate and bulk pins should be treated
with less importance in circuit comparison. YESsubstratebulkpins NO
indicates that substrate and bulk pins should be treated like any
other pins. NOsubstratebulkpins .
LVS Filter Unused Option { B D E O }LVS Filter Unused Option { B
D E O } B Filters MOS devices if the following conditions are both
satisfied: (a) the gate is floating or has no path to any pad, and
(b) either the source or drain is floating. MOS aGatefloatingPAD b)
MOSsourcedrainfloating D Filters MOS devices if the gate is
floating, either source or drain have a path to power, and neither
source nor drain have paths to non-power pads. MOS aGatefloatingPAD
b) MOSsourcedrainpower
LVS Filter Unused Option { B D E O}E Filters MOS devices if the
gate is floating, either source or drain have a path to ground, and
neither source nor drain have paths to non-ground pads. MOS
aGatefloatingPAD b) MOSsourcedrainpower O Repeats all unused device
filtering until no more devices can be filtered. Also repeats
series and parallel reduction of capacitor, resistor, diode, and
MOS devices, split gate reduction, and semiseries MOS reduction.
device
LVS Filter Unused { B D E O}Not power
DE
Not ground
B
Gate & Source Floating Or Gate & Drain Floating
power Gate Floating
ground
Gate Floating And S DGnd
And S DPower
O DIODE gateMOS
LVS Filter Unused Option {AB RC RE RG}LVS Filter Unused Option
{AB RC RE RG} AB Filters MOS devices with source, drain, and gate
pins tied together. GateSourceDrainMOS RC Filters resistors with
POS and NEG pins tied together. RE Filters capacitors with POS and
NEG pins tied together. RF Filters diodes with POS or NEG pin
floating. FloatingDiode RG Filters diodes with POS and NEG pins
tied together. Diode
LVS Filter Unused Option {AB RE RC RE RG}AB
RC
RG
RF
LVS Filter Unused Option ExampleB D RC
layout B,D,E,AB,R C,RG,RF
E
AB
RG
RF
LVS Filter Unused Option Example
lvs commandfile lvs7match
LVS Filter Unused Option Example
LVS Filter Unused Option ExampleD,Edevice
D
E
LVS Filter Unused Bipolar { YES | NO }LVS Filter Unused Bipolar
{ YES | NO } NO Bipolar YES Bipolar
LVS Filter Unused Bipolar Option Example
LVS Filter Unused Bipolar Option Example
Lvs Globals Are Ports {NO | YES}LVS GLOBALS ARE PORTS {NO | YES}
YES NETLIST *.GLOBAL PORT NO NETLIST *.GLOBAL PORT
Lvs Globals Are Ports Option Example
Lvs Globals Are Ports Option Example
TEXT PRINT MAXIMUM {ALL | NUMBER} TEXT PRINT MAXIMUM { ALL |
NUMBER }ALL top celltextportreport NUMBER top
cellnumbertextportreport
Lvs Property Resolution Maximum Option
Lvs Property Resolution Maximum {number | All} Number number LVS
ALL LVS
Lvs Softchk Pwell_all contactLvs Softchk Pwell_all contact
Reports regions on a pwell layer that connect to more than one
node. pwell
Trace Property C1 C2 C3 trace_valTrace Property C1 C2 C3
trace_val Trace Property C1 C2 C3 trace_val
TraceDevice AB ADevice BDevice eg. R(NI) NI R(LR) LR
Netlistdevice eg. .SUBCKT TOP C01 A1 B1 C=100 C02 A2 B2 C=100
.ENDS
Layoutdevice eg. .SUBCKT TOP C01 A1 B1 C=101 C02 A2 B2 C=105
.ENDS
eg.
2
Trace Property C1 C2 C3 trace_valTraceDevice M C R D Q MOS
transistor Capacitor Resistor Diode Bipolar transistor TraceDevice
W MOS width C Capacitance L MOS length A Diode area M Multiplier
factor P Diode perimeter R Resistance
Trace Property C1 C2 C3 trace_val Example
1168
Trace Property C1 C2 C3 trace_val Example
1168.29
Trace Property C1 C2 C3 trace_val Example
1168.29
