Experimental Analysis of a Cascaded Multilevel Inverter Using Buck EIE Converters

Natália M. A. Costa, Luiz C. de Freitas, João Batista V. Junior, Ernane A. A. Coelho, Valdeir J. Farias, and Luiz C. G. Freitas

Núcleo de Pesquisa em Eletrônica de Potência (NUPEP) Universidade Federal de Uberlândia (UFU) - Faculdade de Engenharia Elétrica (FEELT)

Uberlândia, Minas Gerais, Brasil 38400-902 E-mails: nataliamcosta@yahoo.com.br; lcgfreitas@yahoo.com.br

Abstract- The multilevel inverters are pointed in the literature as one of the most suitable solutions for high-power applications, in medium and high voltage levels. These inverters are based on the association of converters, either in parallel or in series, aiming to process a smaller amount of the total output power in each converter. Generally, the output voltage and/or current is a staircase waveform and the output voltage has low harmonic distortion. In this context, a novel approach on cascaded multilevel inverters is presented in this paper. The proposed topology is based on the cascaded association of Buck EIE inverters, developed from the EIE active commutation cell. The output voltage is totally controlled and follows a desired reference signal, which assures low harmonic distortion without the necessity of using passive filters on the converter output. The voltage stress levels over the power semiconductor devices, especially switches and diodes, are kept low even for high voltage applications. Detailed circuit description is given as well as simulation and experimental results of a Multilevel Buck EIE Inverter prototype, in order to confirm the operation principles of the proposed topology.

I. INTRODUCTION Power electronics applications requiring medium-voltage

and high-voltage power converters have been increasing over the years. Countless topologies have been developed to supply this potential necessity and most of them led to the multilevel inverters [1]. Researches show that the first multilevel converter was presented over 30 years ago when an inverter with an AC staircase voltage output was developed by the connection of two full-bridge cells. Presently, there are three main types of multilevel converters: diode-clamped topology, capacitor-clamped topology and cascaded topology [2-4]. Among those topologies, diode-clamped and Cascaded H-Bridge topologies are the most widely used in industrial applications [5].

The diode-clamped topology affords, for its three-level arrangement, three values of output voltage: 0, +Vdc/2 and –Vdc/2. The capacitor clamped topology also provides an ac staircase output voltage and, for a three-level converter, the levels of output voltage are the same of the diode-clamped topology. These topologies are widely used due to their relative small number of switches but they become

impracticable to high-power applications, since that the number of components (diodes and capacitors) necessary, as well as their blocking voltage, increases critically. For cascaded topology, in ordinary designs, each level is fed by an independent dc source and the ac staircase output voltage waveform is very close to a sinusoid, eliminating the necessity of using passive filters at the output of the inverter. Briefly, each converter cell provides three output voltage levels: 0, +Vdc, and –Vdc and the total output voltage of the converter, obtained by the addition of each voltage cell, looks like the waveform presented in Fig 1.

Figure 1. Output Voltage Waveform for a Conventional Cascaded

Multilevel Converter.

Clamped topologies do not require independent dc source for each level of the inverter, which explains the reason why great part of the studies focus on the development of this kind of topology [6]. However, the cascaded topology shows some advantages, mainly because of its modular circuit [4]. Many studies show that the cost of implementation of cascaded topologies is 15% lower than the diode-clamped topological arrangements [7]. In addition, most of the multilevel converters presented in the literature, especially the clamped ones, are designated to medium-voltage applications, since each power semiconductor device must support severe voltage

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stress. Hence, to make possible having high-voltage power multilevel inverters, it is also necessary to have power semiconductor devices able to support high voltage and current levels. It is well known that, although power semiconductors manufacturers are in constant development, it is notorious that, as voltage and current specifications of power semiconductors increases, their price increases exponentially [2]-[3].

In this context, this paper aims to contribute presenting a novel multilevel topology that presents as its main advantage the possibility of being used in high-voltage applications with low voltage stress over power semiconductors. It also provides a sinusoidal output voltage with low harmonic distortion, without the necessity of using passive filters at the output of the inverter. The proposed multilevel inverter is a result of the combination of Buck EIE converters fed by individual and independent dc sources [8-11]. A detailed description of the principle of operation and the applied control strategy, as well as simulation results, are presented in this paper.

II. PROPOSED CONVERTER TOPOLOGY

A. Traditional Cascaded Multilevel Inverter. Figure 2 presents a traditional cascaded multilevel inverter,

as well as its operational voltage waveforms. Briefly, according to [2], a cascaded muticell inverter is constituted by single-phase inverters connected in series with separated dc sources. Each cell of the inverter stores energy on its output capacitor and the total converter output voltage is synthesized by the addition of these capacitor voltages, generated by different cells.

Figure 2. Traditional Cascaded Multilevel Inverter.

B. Buck EIE Multilevel Inverter. Focus on the development of new converter topologies, an

active commutation cell using two switches has been developed, as shown in Fig. 3(a) [8-11]. This commutation

cell was called EIE due to its characteristics (voltage-current-voltage) and, from it, a whole new family of PWM DC-DC converters has also been created. Among these converters, one can outline the Buck EIE converter portrayed in Fig. 3(b). The Buck EIE converter differs from the ordinary Buck converter due to the use of an additional switch and an extra diode. Comparing these topologies, may be noted that the main advantage of the Buck EIE converter resides in the fact that it operates without presenting overshoots on the output voltage, since the input inductor current (IL) and the capacitor voltage (VC) are controlled separately [9]. Hence, owing to this operational characteristic, the use of Buck EIE converter in DC-AC applications has demonstrated itself to be very interesting.

(a)

(b) Figure 3. (a) EIE Commutation Cell (b) Buck EIE converter.

Supported by this commutation cell and expecting to develop a new multilevel topology to be used in application supplied by any voltage levels, a novel approach on cascaded multilevel inverters was achieved. To make that possible, the main constraint to be overcome was the high voltage stress levels over the semiconductors, especially the switches. So the potential solution was to develop an arrangement where these levels would be lower. Therefore, in this paper, it is presented a novel proposal of multilevel inverter topology derived from the association of Buck EIE inverters. Each cell of the multilevel topology here presented consists of the association of two Buck EIE converters, as shown in Fig. 4. The construction of the proposed converter was based on the presented concepts of a conventional multicell inverter. Each cell of the proposed converter stores energy on its output capacitor and the total output voltage is synthesized by the addition of these voltage levels. In other words, each cell of the converter contributes with a portion of the total output voltage.

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Figure 4. Multilevel Buck EIE Inverter – One Level.

The Buck EIE Converter, as said before and shown in Fig 1(b), is a topology developed from a commutation cell, called EIE and its basic operation is divided in two stages: (1) the switches S1 and S2 are turned on and the energy stored in the inductor L1 is transferred to the output capacitor C1; (2) the switches S1 and S2 are turned off and the remaining energy stored is L1 is given back to the source V1 through the diodes D1 and D2 that, at this moment, are forward biased. The output voltage is totally controlled without presenting overshoots. Using the adequate control strategy, this converter can operate as a “voltage follower”, which means that the converter output voltage will follow a desired reference signal. Two Buck EIE converters, associated as shown in Fig 4, compose a Buck EIE Inverter and so, it is possible to impose a sinusoidal reference signal on its output capacitor.

Based on the assumptions above, the proposal of the buck EIE Multilevel Inverter is to have Buck EIE Inverters associated in series. Once that each cell of the whole converter is composed by two Buck EIE converters, and that each Buck EIE converter is fed by one independent dc source, each cell of the proposed multilevel inverter is composed by two independent dc sources. Considering the operation of the Buck EIE Converter, described above, each cell of the multilevel inverter will have a sinusoidal output voltage imposed across the output capacitor. The total converter output voltage will be synthesized by the addition of each cell voltage. Once that each cell voltage is sinusoidal, the total output voltage will also be sinusoidal. In Fig. 5 it is portrayed a Four-Level Buck EIE Inverter and in Fig. 6 the total output voltage, represented by the sum of the four capacitors voltage levels, is shown.

The main advantages of this converter are: (1) a totally controlled output voltage, (2) the possibility to use the multilevel inverter in high-voltage applications, thanks to the reduced stress voltage over the semiconductor devices, (3) a sinusoidal waveform output voltage, independent of the number of levels of the converter and without the necessity of using passive filters and (4) a simple control strategy, as described in section III of this paper.

It is well-known that, for conventional multilevel topologies, the number of levels of the converter is directly related to the number of step levels on the output voltage. However, for the novel proposed topology, due to its operational characteristic and applied control strategy, the output voltage waveform is already sinusoidal, which means that there are no steps on the output voltage. So, in order to maintain the nomenclature similar to one used for conventional multilevel topologies, the number of levels for Multilevel Buck EIE Inverters is associated to the number of voltage levels that contributes to the total output voltage level. In other words, for the proposed topology the number of levels

of the converter is represented by the number of cells that composes the whole structure.

Figure 5. Case Study – Four-Level Buck EIE Converter.

Figure 6. Multilevel Buck EIE Inverter – Voltage Levels.

The multilevel Buck EIE inverter operates with as many levels as necessary to provide the output voltage required by the load. The higher the number of levels, the higher will be the cost but, on the other hand, greater number of levels provides higher output voltage, keeping the voltage and current stress in the switches the same. The requirements of the application define the converter arrangement that gives the best cost benefits relation.

It is important to emphasize that unlike traditional multilevel inverter, the output voltage of the proposed converter is really close to a sinusoid, independent of the number of levels of the converter. For conventional topologies, for higher number of levels, the output voltage will have more steps and, therefore, it will be close to a sinusoidal waveform. Besides, conventional topologies require passive filter application at the converter output in order to filter the output voltage waveform.

In this paper, it is presented a study case using a four-level Buck EIE inverter fed by eight independent dc sources of 48V

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each, with the capability to provide a 115V (rms) and 60Hz sinusoidal voltage. This arrangement is presented in Fig. 5 and it is composed by 16 switches (M1 to M16), responsible to charge and/or discharge the inductors (L1 to L8) and capacitors (C1 to C8).

The basic concept of proposed inverter is based on the association of eight Buck EIE cells, each one fed by an independent dc source. Since the converter has a totally controlled output voltage, it is possible to define the mentioned topology as a DC-AC converter in which the output voltage waveform follows a desired reference signal. The converter features makes it suitable for linear and non-linear loads, as well as in low, medium, and high power applications, without losing its capability to operate with fully controlled output voltage.

The principle and stages of operation of the converter are presented in section III of this paper and describes the hole operation of the converter.

III. PRINCIPLE AND STAGES OF OPERATION The operation mechanism of the multilevel Buck EIE inverter can be explained with the description of only two distinctive

operation stages. The mainly reason for that is the fact that the switches located on the left part of the inverter (S1 to S8) and

the ones located on the right part (S9 to S16) are turned on and off in a complementary way, which means that, when S1 to S8 are turned on S9 to 16 are turned off simultaneously, and vice

versa. So, based on the assumption above and considering that

the dc sources are independent and ripple-free, the proposed circuit can be illustrated and explained as it follows.

A. First Stage – Increase of the output voltage. In this first stage, the switches S1-S8 are turned on while

S9-S16 are turned off. At this moment, the energy stored on the inductors L1-L4 is transferred to the output capacitors C1-C4 and to the load as well, respectively. Therefore, due to the applied voltages V1-V4, the voltage across capacitors C1-C4 increases.

The remaining stored energy on inductors L5-L8 is given back to the DC sources V5-V6, though diodes D10-D16 that, at this moment, are forward biased. Figure 7 shows the schematic circuit that represents this operation stage. B. Second Stage – Decrease of the output voltage

On the second stage, the switches S1-S8 are now turned off while S9-S16 are turned on. At this moment, the independent DC sources V5-V8 and the inductors L5-L8 constitute current sources, which make the voltage across the output capacitors decrease. As observed during the first stage of operation, the remaining stored energy on inductors L1-L4 is transferred to the DC sources V1-V4 through the diodes D1-D8. Figure 8 shows the schematic circuit that represents this operation stage.

For both operation stages, each level of the converter has two switches commutating in a single interval but, the voltage stress over each one of these power semiconductors is

different. Considering the independent DC sources V1-V8 as the referential, the voltage stress over the “first” switches (S1,S3,S5,S7 – left part and S10,S12,S14,S16 – right part) represents, at most, the sum of the value of the DC source and the voltage drop over the diodes. The other switches (S2, S4, S6, S8 – left part and S9,S11, S13, S15 – right part) are submitted to a higher voltage stress level, depending on the characteristics of the load. Considering the worst case, when the load is closest to a pure inductance, for a short period of time, there is current flowing through inductors L1-L4 (for the first operation stage) or L5-L8 (for the second operation stage) while the voltage on the load still has positive values (for the first operation stage) or negative values (for the second operation stage). That means that, during this period of time, the voltage stress level over the switch is represented by the sum of the DC source value and the peak voltage multiplied by the static gain of the converter, as shown in (1).

S dc peakV V V G= + ⋅ (1)

Where, Vs – Stress voltage over the switch Vdc – Independent dc source Vpeak – Output peak voltage G – Static Gain

Figure 7. Stages of Operation: First Stage

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Figure 8. Stages of Operation: Second Stage

It is important to emphasize that the static gain of the converter (G) is determinate by the reference signal amplitude. However, for the proposed topology, the maximum gain achieved is 85%. This and others control strategy details applied to the proposed multilevel inverter are presented in details in section IV.

IV. CONTROL STRATEGY One of the advantages of this topology is to require an

easy control strategy, comparatively to others. The control circuit consists of basically only an analog comparator. A sample of the output voltage is sent to the inverting input of the analog comparator. The non-inverting input receives the reference signal. From the comparison of these two signals the gate drive signal are obtained, as portrayed in Fig. 9.

The analog comparator output is connected to a gate-drive circuit. When the feedback signal is greater than the reference signal, the gate-drive circuit send pulses to the switches on the right part of the converter (S9 to S16); and when the reference signal is greater than the feedback signal, the gate-drive circuit send pulses to the switches on the left part of the converter (S1 to S8). At this point, the gate-drive also provides isolate pulses, since the reference potential of each converter level is different. Using the proposed control strategy, the output capacitor voltages will follow the reference signal and the desired waveform will be imposed to the output voltage.

The control strategy is also responsible to determinate the output voltage amplitude. Once the output voltage follows a reference signal, its amplitude is directly related to the amplitude of the reference voltage. The maximum static gain achieved by this converter is 85% and, as shown in (1), this value interferes directly on the specification of the converters’ switches. A static gain of 85% means that the output voltage

will represent 85% of the input voltage. Numerically speaking, for the proposed case study presented in this paper, the load voltage is equal to the sum of the output capacitors voltages (C1 to C4). Therefore, one can conclude that, for a four-level Buck EIE converter, fed by 48V independent DC sources the total input voltage is 192V. So, with a maximum static gain of 85%, the maximum output voltage achieved will be around 163V, which represents 115V rms at rated load.

Figure 9. Control Strategy Schematic Circuit – One level.

V. SIMULATION AND EXPERIMENTAL RESULTS In order to validate the proposed converter, a computing

simulation was built using PSPICE@ platform. For that, the operational waveforms of the four-level Buck EIE converter, were analyzed in two different conditions: (1) A four-level EIE converter feeding a linear load and (2) A four-level Buck EIE converter feeding a non-linear load. For the second condition, a diode bridge rectifier (DBR) was considered as the load. The converter was proposed to supply a 1kW load and, to make that possible, the design specifications are described in Table I.

TABLE I. DESIGN SPECIFICATIONS – MAIN PARAMETERS AND ITS VALUES

PARAMETER ELEMENT VALUE

INPUT DC SOURCES V1~V8 48V INDUCTORS L1~L8 100UF

OUTPUT CAPACITORS C1~C4 22UF

DIODES D1~D16 IDEAL SWITCHES S1~S16 IDEAL

Downwards, the simulation results, for both cases, are presented, including the values of voltage and current on the load as well as voltage across the switches.

From the graphic presented in Fig. 10, it is possible to observe that a sinusoidal output voltage was achieved, with a period of 20ms, the equivalent of 50Hz. The output voltage peak is around 160V, affording a rms value of approximately 115V. An output voltage of 160V also reinforces the idea of a 85% maximum static gain can be achieved with the proposed inverter, as explained in section III of this paper.

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Figure 10. Load Voltage and Load Current - Linear load – R = 10 ohms

In Fig. 11 and Fig. 12 the drain-to-source voltage over the switches, S1 and S2 respectively, are shown and, analyzing the graphs, it is possible to conclude that the maximum voltage stress level over a switch, for linear loads, is around the value of the independent dc source used to feed a single level of the proposed topology, added to the voltage drop in the diodes. These statements reassure the proposal of this work, ensuring that the voltage stress levels over the switches are reduced, compared to conventional multilevel topologies.

Figure 11. Drain-to-source voltage of S1 - Linear load – R = 10 ohms.

Figure 12. Drain-to-source voltage of S2 - Linear load – R = 10 ohms.

Analyzing the simulation results for non-linear load condition (single-phase rectifier with high output capacitor filter), shown in Fig. 13, one can observe that, even though the load current presents high harmonic content (83.95%), the

load voltage supplied by the proposed inverter does not present significant distortion (5%), as presented in Table II.

TABLE II. 'VOLTAGE AND CURRENT THD LEVELS – LINEAR AND NON-LINEAR LOADS

PARAMETER LINEAR LOAD NON-LINEAR LOAD

CURRENT THD [%] 1.29 % 83.95 % VOLTAGE THD [%] 1.29% 1.55 %

Figure 13. Load voltage and load current – Non-linear load.

Also from Fig. 13, it is possible to assure that the output voltage maintains its sinusoidal waveform, with a period of 20ms, the equivalent to 50Hz, affording an output voltage peak around 160V, which means an rms value of approximately 115V.

Fig. 14 and Fig. 15 the drain-to-source voltage over the switches, S1 and S2 respectively, are shown. Analyzing the graphs, it is possible to conclude that the maximum voltage stress level over a switch, for non-linear loads, is around two times the value of the independent dc source used to feed a single level of the proposed topology.

Figure 14. Drain-to-source voltage of S1– Non-linear load.

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Figure 15. Drain-to-source voltage of S1– Non-linear load.

Even though the voltage stress level over the switches for the non-linear loads is greater than the one afford by the linear load condition, these levels are still lower than the ones found in ordinary multilevel inverters. Moreover, in both situations, the voltage stress level were directly related to the values of the independent dc source, which means that it is possible to limit and control these levels by limiting the values of the dc sources of the converter. All the statements presented above corroborate with the proposal of this work, ensuring that the voltage stress levels over the switches are reduced, comparing to conventional topologies, feeding linear and/or non-linear loads.

In order to verify, experimentally, the operation performance of the proposed multilevel inverter, a laboratory prototype was developed. The experimental results presented herein were obtained from a two and three-level Buck EIE inverter and are presented from Figs. 16 to 22.

Figure 16. Reference signal and output voltage for linear load – 2-level Buck

EIE inverter.

Figure 17. Drain-to-source voltage across S1 and S3 for linear load – 2-level

Buck EIE inverter.

Figure 18. Drain-to-source voltage across S2 and S4 for linear load – 2-level

Buck EIE inverter.

Figure 19. Transient response for a load step up for linear load.

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Figure 20. Output voltage and current for nom-linear load –2-level Buck EIE inverter.

Figure 21. Output voltage for linear load - 3-level Buck EIE Inverter.

Figure 22. Prototype of a 3-level Buck EIE Inverter.

VI. CONCLUSIONS This paper presented a novel multilevel inverter topology,

using Buck EIE. The proposed converter is characterized by imposing load voltage through an efficient and simple control strategy.

The topology adopted reduces the voltage stress level over the switches and the output voltage is sinusoidal, independent of the number of levels of the inverter, and characterized by having low harmonic distortion without the necessity of using passive filters on the output of the inverter.

Simulation results reassure that the converter operates properly, turning up as a good alternative for low, medium, and high power applications. It also can affords an adequate output voltage supplying linear and/or non-linear loads in accordance with IEC61000-3-2.

Experimental results of a Two and Three-Level Buck EIE Inverter were presented in order to corroborate with the theoretical analysis also included.

ACKNOWLEDGMENT The authors would like to thanks CAPES, CNPq, and

FAPEMIG for the financial supports to this project.

REFERENCES [1] L. Batschauer, M. L. Heldwein, S.A. Mussa and A.J. Perin, “Hybrid

Multilevel Converter Employing Half-Bridge Modules”, Brazilian Power Electronics Conference, pp.369-376, Sep. 2009.

[2] J. Rodríguez, J.S. Lai and F.Z.Peng, “Multilevel Inverters: A Survey of Topologies, Controls, and Applications”, IEEE Trans.Ind. Electronics vol. 49, no. 4, pp. 724-738, Aug. 2002.

[3] G.J. Su, “Multileve DC Link Inverter”, IEEE/IAS Annual Metting, vol. 2, pp. 806-812, Oct. 2004.

[4] A.A.Sneineh, M.Wang and K. Tian, “A New Topology of Capacitor-Clamp Cascade Multilevel Converters”, Power Electronics and Motion Control Conference IPEMC CES/IEEE, vol. 2, pp. 1-5, Aug. 2006.

[5] K.Wang, Y. Li and Z. Zheng, “A new transformerless cascaded multilevel converter topology”, IEEE Energy Conversion Congress and Exposition ECCE, pp.3124-3129, Sept. 2009.

[6] B. Hu, G. Xu, M. Zhang, J. Kang and L. Xia, “Study on a Novel Clamped Topology of Multilevel Converters”, Electric Machines and Drivers Conference IEMDC, pp. 379-384, May. 2009.

[7] P. Panagis, F. Stergiopoulos, P. Marabeas and S. Manias, “Comparison of the Art Multilevel Inverters”, PESC’08, pp.806-812, Jun. 2008.

[8] C.A. Bissochi Jr., “Proposta de Uma Nova Família de Conversores Denominados EIE: Aplicações em Áudio, Análise Genérica e Resultados Experimentais”, PhD Dissertation, UFU, Uberlândia, MG. Brasil.

[9] C.A. Bissochi Jr, F.R.S. Vicenzi, V.J. Farias, J.B. Vieira Jr and L.C. de Freitas, “A New Family of EIE Converters”, in Proc. of VI COBEP, 2001.

[10] L.C. G. Freitas, E.A.A. Coelho, J.B. Vieira Jr., V.J. Farias and L.C. Freitas, “A New Proposal of Switched Power Oscillator Applied as a Self-oscillating Auxiliary Medium Open Loop Power Supply”, IEEE PESC’03, vol. 2, pp. 600-605, Jun. 2003.

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