Cell-Based Design Flow

1

林丞蔚

cultom@viplab.cs.nctu.edu.tw

Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment2

Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment3

Cell-based Design Flow Overview

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• A design flow is a set of procedures that allows designers to progress from a specification for a chip to the final chip implementation in an error-free way.

Cell-based Design Flow

Specification DevelopmentSystem Models

RTL code developmentFunctional Verification

SynthesisTiming Verification

Physical Synthesis/Place and RoutePhysical Verification

PrototypeBuild and Test

System Architecture

RTL

Synthesis

Physical Design

System Integration and Software Test

Source: CM: 5086 VLSI Design Lab

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Cell-based Design Tool

• System Architecture/SW simulation

– C/C++, Matlab, System C, System Verilog…

• RTL

– NC-Verilog, NC-VHDL, nLint, Debussy…

• Synthesis

– RTL Compiler, Design Compiler, PrimePower…

• Physical Design

– SoC Encounter, Astro, Calibre, Nanosim…

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Source: CM: 5086 VLSI Design Lab

Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment7

RTL Development

• Development / simulation

– NC-verilog

• Unix:> ncverilog <your_testbench_file> +access+r

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RTL Development

• Check the simulation output

– Dump waveform from testbench when simulation

• $fsdbDumpfile(“triangle.fsdb”);

– nWave

• Unix:> nWave

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RTL Development

• Verilog dump related command

– VCD file format(Value Change Dump)

• $dumpfile()

– FSDB file format(from Novas)

• $fsdbDumpfile(“output.fsdb”);

• Fsdb file is the input of Verdi

• Verdi(debussy): a powerful debugging tool provided by NOVAS

– Unix:> Verdi

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RTL Development

• nLint from NOVAS

– Unix:> nLint –gui &

– Run->Compile

– Run->Lint

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/cad/EDA/spring/verdi/2006.04v1/nLint/doc/pdf/rules.pdf

Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment12

Synthesis

• Synthesis=translation+ optimization+ mapping

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Residue = 16’h0000;If(high_bits==2’b10)

residue = state_table[i];Else state_table[i] = 16’h0000;

HDL Source(RTL)

Translate(HDL Compiler)

Optimize + Map

(Design Compiler)

Generic Boolean

Target Technology

NO Timing Info =>

Timing Info =>

Source: CIC Jan.08 Design Compiler

Synthesis

• Design Compiler

– It synthesizes your designs (Verilog) into optimized technology-dependent, gate-level designs.

• Use Design Compiler GUI

– Startup x-win ( or any other X terminal application)

– $design_vision

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Synthesis

• Environment Setup

– /home directory/.cshrc : set path and license of synthesis tool

– /your working directory/.synopsys_dc.setup : setup technology file, designware library file…etc

• Use DC-TCL script file(.tcl)

– Set design constraints

– Unix:> design_vision-xg -f syn.tcl

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Synthesis

• Detail of synopsys_dc.setup

ASIC Technology file

For schematic

For Designware

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Your Design Name

Synthesis

• Modify the syn.tcl

Your Design Name

Synopsys

Design

Constain

sdc file:synopsys design constrains

sdf file:standard delay format

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Synthesis

• SDC file : synopsys design constrain

– Setup input/output delay and loading

• SDF file : standard delay format

– Setup the rising/holding/falling time for each cell of your design

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Synthesis

• Put the “RTL file”, “.synopsys_dc.setup” and “syn.tcl” to your working directory, or assert the setup commands by hand, while synthesis.

• Under your working directory, make new directories, Report and Netlist, for saving synthesis reports.

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Synthesis

• Output result

command

Command return result(error)

command

Command return result(done)

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Synthesis

• The synthesis information is in your “Report” directory

Timing.txt

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Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment22

Gate Level Simulation

• Verify your synthesis result

– Modify your testbench

• sdf_annotate(“triangle.sdf“, top)

• `include “CHIP.v”

• Unix:> ncverilog <YourTestBench.v> -v ./tsmc13_neg.v +access+r

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Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment24

SOC Encounter Placing & Routing Flow

IO, P/G Placement

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Netlist(verilog)

Timing Constrain(sdc)

IO Constrain

Specify floorplan

Timing Analysis

Pre-CTS OptimizePower Planning

Power Analysis

Clock Tree Synthesis

Timing AnalysisPost-CTS Optimize

Power Route

SI Driven RouteTiming/SI AnalysisPost-Route Optimize

GDS file

Netlist, DEF

4 Main Step(must be in order):

IO Placement, Cell Placement, CTS, SI Driven Routing

Source: CIC Jan. 2008, SoC Encounter

Basic View

• $encounter

Floorplan view

Ameoba view

Physical view

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Project Setup

• Design -> Design Import

netlist

Cell Library

Physical

Library

IO Map file

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IO, Power/Ground Placement

• Floorplan -> Connect Global Nets…

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Floorplan

• Floorplan -> Specify Floorplan

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Cell Placement

• Place -> Standard Cell And Blocks

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Power Planning

• Power -> Power Planning -> Add Rings

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Clock Tree Synthesis

• Clock -> Design Clock…

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Rounting

• Route -> Special Route…

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Rounting

• Route -> NanoRoute…

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Result Analysis

• Final step

– DRC LVS verification

• Verify -> Verify Connectivity

– Timing analysis

• Timing -> Analysis Timing

– Post layout simulation

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Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment36

Example Design

• Triangle Rendering Engine

– Get 3 consecutive pairs of coordinate for a triangle from system testbench

– Input will meet the following relation.(This means that

one side of the triangle will be vertical!)

– Output (xo, yo) coordinate

– Output “po” is active to indicate there is a valid coordinate output (xo, yo)

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Example Design

• I/O Interface :

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Example Design

• Basic Algorithm

– Given 2 point (x1, y1), (x2, y2). The line equation of 2 point form are :

– Any points in the right side of this line will satisfy the equation:

– Any points in the left side of this line will satisfy the equation:

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Example Design

• Design Implementation

– Use 2 counters to count 0~7(3 bits), when (count_x, count_y) located in the triangle, active “po” as high.

– When count_x is betwee X1 and X_bound, active “po” as high.

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Design Implement

• Finite State Machine

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case(state)0: begin

if(nt) state = 1;end1: begin

state = 2;end2: state = 3;3: begin

if(&{cnt_x, cnt_y})beginstate = 0;

endend

Extra state for 3 pairs of input

Design Implement

• Input : Register shift module

– 3 register for x and y coord.

– Input data state : shift data to next register

– Computation state : keep data.

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Assign mux = (compu_state) ? output : input;always@(posedge clk)begin

if(rst)output <= 3’b0;

elseoutput <= mux;

end

Output pass to the input port of next register

Design Implement

• X_bound calculation

– Case 1: x_bound += (y1-y2/x1-x2)

– Case 2: x_bound -= (y0-y1/x1-x0)

– Case 3: x_bound -= (y1-y2/x1-x2)

– Case 4: x_bound += (y0-y1/x0-x1)

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v1v1

v2

v0

Case 1

Case 2

Case 3

Case 4

If(cnt_y < y1 && cnt_y >= y2)if(x1 > x2)

x_bound <= x_bound + dx1;else

x_bound <= x_bound – dx1;Else if(cnt_y >= y1)

if(x1 > x2)x_bound <= x_bound – dx2;

elsex_bound <= x_bound + dx2;

Design Implement

• “po” specification

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assign po = (state = computation_state)

&& (cnt_y >= y2 && cnt_y <= y0 && x1 > x2 && cnt_x >= x2 && cnt_x <= x_bound)

&& (cnt_y >= y2 && cnt_y <= y0 && x1 <= x2 && cnt_x >= x_bound && cnt_x <= x2)

v1v1

v2

v0

Case 1

Case 2

Case 3

Case 4

Case 1, 2

Case 3, 4

Design Implement

• System architecture

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Outline

• Overview

• Design Flow – 1

– RTL Development

– Synthesis

– Gate Level Simulation

• Design Flow – 2

– Placement and Routing

• Example Design

– IC Contest 2006

• Project Assignment46

Mini Project

• Goal : Compile / Simulate / Synthesis an Ethernet MAC project at opencores.org

– Tool(platform) used:

• Compile : ModelSim (win)

• Simulate : ModelSim(win)

• Synthesis : Design Compiler(Unix)

• Gate level simulation : ModelSim(win)

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Mini Project

• Server IP

– 140.113.17.123~140.113.17.130 port: 22 (SSH)

– 140.113.17.158~140.113.17.159 port: 22 (SSH)

– 140.113.17.217~140.113.17.219 port: 22 (SSH)

• ID/password will be announced

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Compile / Simulate - 1

• Just fallow the README instruction

– Open the project file

– Execute the scripts file

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Compile / Simulate - 2

• Compiling and simulation message show in the command line window, and the waveform window pop up.

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Synthesis

• Uncompress prepared file in Unix server

• Modify “syn.tcl”

– set DESIGN “eth_rxstatem”

– create_clock –period 40 [get_ports MRxClk]

• Unix:> design_vision-xg –f syn.tcl

• Check out the Report and Netlist file

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Gate-Level Simulation - 1

• Get file at Netlist directory from Unix server

– eth_rxstatem_SYN.v, eth_rxstatem_SYN.sdf, tsmc13_neg.v

• Modify tb_eth.do in the project directory

– Comment line 82, type in line 83– (use gate-level v file instead of original one)

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Gate-Level Simulation - 2

• Modify eth_rxethmac.v

– Add these lines as below and copy the “eth_rxstatem_SYN.sdf” file to where do.do is located

– (add the timing information for the new gate level v file)

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Gate-Level Simulation - 3

• Modify eth_wave.do file

– Add these line as below– (add the Rx signal to the waveform window)

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• Execute the simulation scripts again

• Modelsim > do do.do

Mini Project

• TODO list

– Take screen shot of each important step or result with text explanation

– Check out some signals in RX module in certain period of time, then find out the corresponding verilog code

– What is the main difference between two simulations (logic level v.s. gate level) in their waveform?

– Demo and turn-in a short report at 1:00-4:00PM 3/20(Fri.) at 715 電資大樓

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Term Project

• Goal : Write a network hardware simulation module in verilog

– Quick scan of the top testbench file : tb_ethernet.v

– Select some properties of this project, ex : full duplex/half duplex

– Develop a simple test case to simulate the properties you choose, and explain the result

• Synthesis the corresponding module and take this gate level verilog file into term project testbench

• (just copy and modify from tb_ethernet.v)56