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Chapter 0 - reVieWChapter 0 - reVieW
• Combinational Logic Circuit, Combinational Logic Circuit, • Propagation Delay,Propagation Delay,• Programmable Logic.Programmable Logic.
EKT 221 / 4EKT 221 / 4DIGITAL ELECTRONICS IIDIGITAL ELECTRONICS II
What have been discussedWhat have been discussed
Design hierarchyDesign hierarchy– Top – down Top – down – Bottom – up Bottom – up
CAD (Computer Aided Design)CAD (Computer Aided Design)
HDL (Hardware Description Language)HDL (Hardware Description Language)
Logic synthesisLogic synthesis
Analysis ProcedureAnalysis Procedure
Analysis Analysis – To determine the function of a circuitTo determine the function of a circuit
Derive Boolean equationDerive Boolean equation
Derive truth tableDerive truth table
Analyze this logic diagramAnalyze this logic diagram
T1
T3
T2
T4
T5
Boolean EquationBoolean Equation
T1 =BCT1 =BC
T2 =ABT2 =AB
T3 =A+T1=A+BCT3 =A+T1=A+BC
T4 =T2 + D = AB + DT4 =T2 + D = AB + D
T5 =AB+DT5 =AB+D
F1 = (A+BC) + (AB + D)F1 = (A+BC) + (AB + D)
F2 = T5 = AB + DF2 = T5 = AB + D
Analyze this Binary AdderAnalyze this Binary Adder
R1
R2R3
C
Truth TableTruth Table
XX YY ZZ CC CC R1R1 R2R2 R3R3 SS
Truth TableTruth Table
XX YY ZZ
00 00 00
00 00 11
00 11 00
00 11 11
11 00 00
11 00 11
11 11 00
11 11 11
CC CC R1R1 R2R2 R3R3 SS
00 11 00 00 00 00
00 11 00 11 11 11
00 11 00 11 11 11
11 00 00 11 00 00
00 11 00 11 11 11
11 00 00 11 00 00
11 00 00 11 00 00
11 00 11 11 00 11
Logic SimulationLogic Simulation
A fast and accurate method of analyzing a A fast and accurate method of analyzing a combinational circuitcombinational circuit
Using simulator softwareUsing simulator software
Results :Results :– Waveforms Waveforms – A complete truth tableA complete truth table– Part of a truth tablePart of a truth table
Logic SimulationLogic Simulation
How is the circuit described in the software How is the circuit described in the software ??– SchematicsSchematics– HDLHDL
Schematic for Binary Adder in Schematic for Binary Adder in XilinxXilinx
Waveforms for Binary AdderWaveforms for Binary Adder
Simulation in Max Plus IISimulation in Max Plus II
Waveforms in MaxPlus IIWaveforms in MaxPlus II
Point to ponder….Point to ponder….
Why do we compare the simulation results Why do we compare the simulation results vs the theoretical results?vs the theoretical results?
Design ProcedureDesign Procedure
Given : Specifications of the problemGiven : Specifications of the problem
1.1. Determine input & outputDetermine input & output
2.2. Derive truth tableDerive truth table
3.3. Obtain Boolean equation (K-map)Obtain Boolean equation (K-map)
4.4. Draw schematicsDraw schematics
5.5. Verify designVerify design
Design of BCD to Excess – 3 Design of BCD to Excess – 3 Code ConverterCode Converter
Specifications :Specifications :
Input in decimal numbers, 0 – 9, in binary Input in decimal numbers, 0 – 9, in binary formform
Output is excess – 3 codeOutput is excess – 3 code
E.g E.g – Decimal = 5 (101)Decimal = 5 (101)– Excess – 3 code = 5 + 3 = 8 (1000)Excess – 3 code = 5 + 3 = 8 (1000)
BCD BCD Excess – 3 Excess – 3
Step 1.Step 1.– Input : 0 to 9, 4 – bit binary codeInput : 0 to 9, 4 – bit binary code
A, B, C, DA, B, C, D
– Output : 3 to 12, 4 – bit binary codeOutput : 3 to 12, 4 – bit binary code
W, X, Y, ZW, X, Y, Z
BCD BCD Excess – 3 Excess – 3Step 2 : Truth TableStep 2 : Truth Table
DecDec
00
11
22
33
44
55
66
77
88
99
AA BB CC DD
00 00 00 00
00 00 00 11
00 00 11 00
00 00 11 11
00 11 00 00
00 11 00 11
00 11 11 00
00 11 11 11
11 00 00 00
11 00 00 11
WW XX YY ZZ
00 00 11 11
00 11 00 00
00 11 00 11
00 11 11 00
00 11 11 11
11 00 00 00
11 00 00 11
11 00 11 00
11 00 11 11
11 11 00 00
BCD BCD Excess – 3 Excess – 3
Step 3 : Boolean equationStep 3 : Boolean equation
W W = A + BC + BD= A + BC + BD
X X = BC + BD + BCD= BC + BD + BCD
Y Y = CD + CD= CD + CD
ZZ = D= D
BCD BCD Excess – 3 Excess – 3
Step 4 : Schematic diagramStep 4 : Schematic diagram
BCD BCD Excess – 3 Excess – 3Step 4 : Schematic diagramStep 4 : Schematic diagram
BCD BCD Excess – 3 Excess – 3
Step 5 : Verify that schematic diagram Step 5 : Verify that schematic diagram agrees with truth tableagrees with truth table
Design of BCD to 7 –segment Design of BCD to 7 –segment decoderdecoder
Specifications :Specifications :
Input in decimal numbers, 0 – 9, in binary Input in decimal numbers, 0 – 9, in binary formform
7 Outputs – to display input number7 Outputs – to display input number
7 – segment Display7 – segment Display
BCD to 7 –segment decoderBCD to 7 –segment decoder
Step 1 :Step 1 :
BCD to 7 – segment decoderBCD to 7 – segment decoderStep 2 : Truth TableStep 2 : Truth Table
AA BB CC DD
00 00 00 00
00 00 00 11
00 00 11 00
00 00 11 11
00 11 00 00
00 11 00 11
00 11 11 00
00 11 11 11
11 00 00 00
11 00 00 11
All other inputsAll other inputs
aa bb cc dd ee ff gg
11 11 11 11 11 11 00
00 11 11 00 00 00 00
11 11 00 11 11 00 11
11 11 11 11 00 00 11
00 11 11 00 00 11 11
11 00 11 11 00 11 11
11 00 11 11 11 11 11
11 11 11 00 00 00 00
11 11 11 11 11 11 11
11 11 11 11 00 11 11
00 00 00 00 00 00 00
ExerciseExercise
A traffic light system has the following A traffic light system has the following specifications for a part of its controller. There specifications for a part of its controller. There are 3 parallel lanes, each with its own red / are 3 parallel lanes, each with its own red / green light. One of these lanes, the priority lane, green light. One of these lanes, the priority lane, is given priority for a green light over the other 2 is given priority for a green light over the other 2 lanes. On the other hand, an alternating scheme lanes. On the other hand, an alternating scheme is used for the other 2 lanes, which are left and is used for the other 2 lanes, which are left and right lane. Design the circuit that determines right lane. Design the circuit that determines which light is to be green at a particular time. which light is to be green at a particular time. The specifications for the controller are as The specifications for the controller are as follows :follows :
ExerciseExercise
Inputs :Inputs :PS – Priority Lane Sensor ( car present = 1; car absent = 0 )PS – Priority Lane Sensor ( car present = 1; car absent = 0 )LS – Left Lane Sensor ( car present = 1; car absent = 0 )LS – Left Lane Sensor ( car present = 1; car absent = 0 )RS – Right Lane Sensor ( car present = 1; car absent = 0 )RS – Right Lane Sensor ( car present = 1; car absent = 0 )AS – Alternating Signal ( select left = 1; select right = 0 )AS – Alternating Signal ( select left = 1; select right = 0 )
Outputs :Outputs :PL – Priority Lane Light ( green = 1; red = 0 )PL – Priority Lane Light ( green = 1; red = 0 )LL – Left Lane Light ( green = 1; red = 0 )LL – Left Lane Light ( green = 1; red = 0 )RL – Right Lane Light ( green = 1; red = 0 )RL – Right Lane Light ( green = 1; red = 0 )
ExerciseExercise
1.1. If there is a car in the priority lane, PL = 1.If there is a car in the priority lane, PL = 1.
2.2. If there are no cars in the priority lane and the right lane, and there If there are no cars in the priority lane and the right lane, and there is a car in the left lane, LL = 1.is a car in the left lane, LL = 1.
3.3. If there are no cars in the priority lane and in the left lane, and there If there are no cars in the priority lane and in the left lane, and there is a car in the right lane, RL = 1.is a car in the right lane, RL = 1.
4.4. If there is no car in the priority lane, there are cars in both the left If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 1, then LL = 1.and right lanes, and AS = 1, then LL = 1.
5.5. If there is no car in the priority lane, there are cars in both the left If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 0, then RL = 1.and right lanes, and AS = 0, then RL = 1.
6.6. If any PL, LL or RL is not specified to be 1 above, then it has value If any PL, LL or RL is not specified to be 1 above, then it has value 0.0.
Chapter 0Chapter 0
Propagation Delay & Propagation Delay & Programmabe LogicProgrammabe Logic
Propagation DelayPropagation Delay
Propagation delay is the time for a change on an input of a Propagation delay is the time for a change on an input of a gate to propagate to the output.gate to propagate to the output.
Delay is usually measured at the 50% point with respect to Delay is usually measured at the 50% point with respect to the H and L output voltage levels.the H and L output voltage levels.
High-to-low (tHigh-to-low (tPHLPHL) and low-to-high (t) and low-to-high (tPLHPLH) output signal ) output signal
changes may have different propagation delays.changes may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, defined with respect to the output, notnot the input. the input.
An HL input transition causes:An HL input transition causes:– an LH output transition if the gate inverts andan LH output transition if the gate inverts and– an HL output transition if the gate does not invert.an HL output transition if the gate does not invert.
Propagation Delay (continued)Propagation Delay (continued)
Propagation delays measured at the midpoint between Propagation delays measured at the midpoint between the L and H valuesthe L and H values
What is the expression for the tWhat is the expression for the tPHLPHL delay for: delay for:– a string of a string of nn identical buffers? identical buffers? – a string of a string of nn identical inverters? identical inverters?
IN
OUT tPHL tPLH
tpd5 max (tPHL , tPLH )
IN OUT
Propagation Delay ExamplePropagation Delay ExampleFind tFind tPHLPHL, t, tPLHPLH and t and tpdpd for the signals given for the signals given
IN (
volt
s)O
UT
(vo
lts)
t (ns)1.0 ns per division
Implementation TechnologyImplementation Technology
Programmable Implementation TechnologiesProgrammable Implementation Technologies
– Read-Only Memories, Programmable Logic Arrays, Read-Only Memories, Programmable Logic Arrays, Programmable Array LogicProgrammable Array Logic
Technology mapping to programmable logic Technology mapping to programmable logic devicesdevices
Why Programmable Logic?Why Programmable Logic?Facts:Facts:– It is most economical to produce an IC in large volumesIt is most economical to produce an IC in large volumes– Many designs required only small volumes of ICsMany designs required only small volumes of ICs
Need an IC that can be:Need an IC that can be:– Produced in large volumesProduced in large volumes– Handle many designs required in small volumesHandle many designs required in small volumes
A programmable logic part can be:A programmable logic part can be:– made in large volumesmade in large volumes– programmed to implement large numbers of different programmed to implement large numbers of different
low-volume designslow-volume designs
Programmable Logic - Additional AdvantagesProgrammable Logic - Additional Advantages
Many programmable logic devices areMany programmable logic devices are field- field- programmableprogrammable, i. e., can be programmed outside of the , i. e., can be programmed outside of the manufacturing environmentmanufacturing environment
Most programmable logic devices are Most programmable logic devices are erasableerasable and and reprogrammablereprogrammable..
– Allows “updating” a device or correction of errorsAllows “updating” a device or correction of errors
– Allows reuse the device for a different design - the ultimate in Allows reuse the device for a different design - the ultimate in re-usability!re-usability!
– Ideal for course laboratoriesIdeal for course laboratories
Programmable logic devices can be used to prototype Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs.design that will be implemented for sale in regular ICs.
– Complete Intel Pentium designs were actually prototype with Complete Intel Pentium designs were actually prototype with specialized systems based on large numbers of VLSI specialized systems based on large numbers of VLSI programmable devices! programmable devices!
Technology CharacteristicsTechnology CharacteristicsPermanent - Cannot be erased and reprogrammedPermanent - Cannot be erased and reprogrammed
Mask programmingMask programming
FuseFuse
AntifuseAntifuse
ReprogrammableReprogrammable– Volatile - Programming lost if chip power lost Volatile - Programming lost if chip power lost
Single-bit storage elementSingle-bit storage element– Non-VolatileNon-Volatile
Erasable Erasable
Electrically erasableElectrically erasable
Flash (as in Flash Memory)Flash (as in Flash Memory)– Build lookup tablesBuild lookup tables
Storage elements (as in a memory) Storage elements (as in a memory) – Transistor Switching Control Transistor Switching Control
Stored charge on a floating transistor gateStored charge on a floating transistor gate– Erasable Erasable – Electrically erasableElectrically erasable– Flash (as in Flash Memory)Flash (as in Flash Memory)
Storage elements (as in a memory)Storage elements (as in a memory)
Programmable ConfigurationsProgrammable Configurations
Read Only MemoryRead Only Memory ( (ROMROM) - a fixed array of AND ) - a fixed array of AND gates and a programmable array of OR gatesgates and a programmable array of OR gatesProgrammable Array LogicProgrammable Array Logic ( (PALPAL)) - a - a programmable array of AND gates feeding a fixed programmable array of AND gates feeding a fixed array of OR gates.array of OR gates.Programmable Logic ArrayProgrammable Logic Array ( (PLAPLA) - a ) - a programmable array of AND gates feeding a programmable array of AND gates feeding a programmable array of OR gates.programmable array of OR gates.Complex Programmable Logic DeviceComplex Programmable Logic Device ( (CPLDCPLD) ) //Field- Programmable Gate ArrayField- Programmable Gate Array ( (FPGAFPGA) - ) - complex enough to be called “architectures” - complex enough to be called “architectures” - See See VLSI Programmable Logic Devices reading supplement VLSI Programmable Logic Devices reading supplement
The EndThe End
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